tree 533a48d7ef3592984d117786b7de2900a1abf554
parent c47265ad64fa793657ce7ecf1a8f636c794e9f40
author Jose Abreu <Jose.Abreu@synopsys.com> 1462181945 +0100
committer Stephen Boyd <sboyd@codeaurora.org> 1462556104 -0700

clk/axs10x: Add I2S PLL clock driver

The ARC SDP I2S clock can be programmed using a
specific PLL.

This patch has the goal of adding a clock driver
that programs this PLL.

At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>