tree 3d5145f97924f4e359037ce6e2093dbf6eced066
parent d9df9fb901d25b941ab2cfb5b570d91fb2abf7a3
author Yasha Cherikovsky <yasha.che3@gmail.com> 1537960575 +0300
committer Paul Burton <paul.burton@mips.com> 1537994298 -0700
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCW6vuQRUccGF1bC5idXJ0
 b25AbWlwcy5jb20ACgkQPqefrLV1AN1cuQD+LW2QWv8vKZRNbj4fjAk5zQSZ5ezL
 LMtYgoqM4zX91+MBAIJZ7b0oud3vqOibIgBeKPdEF9aF/fQyEDWrWKIghYsE
 =vO2Q
 -----END PGP SIGNATURE-----

MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions

MIPSR6 CPUs do not support unaligned load/store instructions
(LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit).

Currently the MIPS tree has some special cases to avoid these
instructions, and the code is testing for !CONFIG_CPU_MIPSR6.

This patch declares a new Kconfig variable:
CONFIG_CPU_HAS_LOAD_STORE_LR.
This variable indicates that the CPU supports these instructions.

Then, the patch does the following:
- Carefully selects this option on all CPUs except MIPSR6.
- Switches all the special cases to test for the new variable,
  and inverts the logic:
    '#ifndef CONFIG_CPU_MIPSR6' turns into
    '#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR'
    and vice-versa.

Also, when this variable is NOT selected (e.g. MIPSR6),
CONFIG_GENERIC_CSUM will default to 'y', to compile generic
C checksum code (instead of special assembly code that uses the
unsupported instructions).

This commit should not affect any existing CPU, and is required
for future Lexra CPU support, that misses these instructions too.

Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20808/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org