| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/media/renesas,fdp1.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Renesas R-Car Fine Display Processor (FDP1) |
| |
| maintainers: |
| - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| |
| description: |
| The FDP1 is a de-interlacing module which converts interlaced video to |
| progressive video. It is capable of performing pixel format conversion |
| between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are |
| supported as an input to the module. |
| |
| properties: |
| compatible: |
| enum: |
| - renesas,fdp1 |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| power-domains: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 1 |
| |
| renesas,fcp: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: |
| A phandle referencing the FCP that handles memory accesses for the FDP1. |
| Not allowed on R-Car Gen2, mandatory on R-Car Gen3. |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - power-domains |
| - resets |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a7795-sysc.h> |
| |
| fdp1@fe940000 { |
| compatible = "renesas,fdp1"; |
| reg = <0xfe940000 0x2400>; |
| interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 119>; |
| power-domains = <&sysc R8A7795_PD_A3VP>; |
| resets = <&cpg 119>; |
| renesas,fcp = <&fcpf0>; |
| }; |
| ... |
