Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys IntelliDDR Multi Protocol memory controller

maintainers:
  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
  - Manish Narani <manish.narani@xilinx.com>
  - Michal Simek <michal.simek@xilinx.com>

description: |
  The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
  32-bit bus width configurations.

  The Zynq DDR ECC controller has an optional ECC support in half-bus width
  (16-bit) configuration.

  These both ECC controllers correct single bit ECC errors and detect double bit
  ECC errors.

properties:
  compatible:
    enum:
      - xlnx,zynq-ddrc-a05
      - xlnx,zynqmp-ddrc-2.40a

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: xlnx,zynqmp-ddrc-2.40a
    then:
      required:
        - interrupts
    else:
      properties:
        interrupts: false

additionalProperties: false

examples:
  - |
    memory-controller@f8006000 {
        compatible = "xlnx,zynq-ddrc-a05";
        reg = <0xf8006000 0x1000>;
    };

  - |
    axi {
        #address-cells = <2>;
        #size-cells = <2>;

        memory-controller@fd070000 {
            compatible = "xlnx,zynqmp-ddrc-2.40a";
            reg = <0x0 0xfd070000 0x0 0x30000>;
            interrupt-parent = <&gic>;
            interrupts = <0 112 4>;
        };
    };