* Marvell Armada 375 Ethernet Controller (PPv2.1)
  Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
  Marvell CN913X Ethernet Controller (PPv2.3)

Required properties:

- compatible: should be one of:
    "marvell,armada-375-pp2"
    "marvell,armada-7k-pp2"
- reg: addresses and length of the register sets for the device.
  For "marvell,armada-375-pp2", must contain the following register
  sets:
	- common controller registers
	- LMS registers
	- one register area per Ethernet port
  For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
  sets:
	- packet processor registers
	- networking interfaces registers
	- CM3 address space used for TX Flow Control

- clocks: pointers to the reference clocks for this device, consequently:
	- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
	- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
	- MG clock (only for armada-7k-pp2)
	- MG Core clock (only for armada-7k-pp2)
	- AXI clock (only for armada-7k-pp2)
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
  "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).

The ethernet ports are represented by subnodes. At least one port is
required.

Required properties (port):

- interrupts: interrupt(s) for the port
- port-id: ID of the port from the MAC point of view
- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the
  GOP (Group Of Ports) point of view. This ID is used to index the
  per-port registers in the second register area.
- phy-mode: See ethernet.txt file in the same directory

Optional properties (port):

- marvell,loopback: port is loopback mode
- phy: a phandle to a phy node defining the PHY address (as the reg
  property, a single integer).
- interrupt-names: if more than a single interrupt for is given, must be the
                   name associated to the interrupts listed. Valid names are:
                   "hifX", with X in [0..8], and "link". The names "tx-cpu0",
                   "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
                   for backward compatibility but shouldn't be used for new
                   additions.
- marvell,system-controller: a phandle to the system controller.

Example for marvell,armada-375-pp2:

ethernet@f0000 {
	compatible = "marvell,armada-375-pp2";
	reg = <0xf0000 0xa000>,
	      <0xc0000 0x3060>,
	      <0xc4000 0x100>,
	      <0xc5000 0x100>;
	clocks = <&gateclk 3>, <&gateclk 19>;
	clock-names = "pp_clk", "gop_clk";

	eth0: eth0@c4000 {
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		port-id = <0>;
		phy = <&phy0>;
		phy-mode = "gmii";
	};

	eth1: eth1@c5000 {
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		port-id = <1>;
		phy = <&phy3>;
		phy-mode = "gmii";
	};
};

Example for marvell,armada-7k-pp2:

cpm_ethernet: ethernet@0 {
	compatible = "marvell,armada-7k-pp22";
	reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
		 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
	clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";

	eth0: eth0 {
		interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
				  "hif5", "hif6", "hif7", "hif8", "link";
		port-id = <0>;
		gop-port-id = <0>;
	};

	eth1: eth1 {
		interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
				  "hif5", "hif6", "hif7", "hif8", "link";
		port-id = <1>;
		gop-port-id = <2>;
	};

	eth2: eth2 {
		interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
			     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
				  "hif5", "hif6", "hif7", "hif8", "link";
		port-id = <2>;
		gop-port-id = <3>;
	};
};