// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2023 MediaTek Inc.
 *
 */

/dts-v1/;
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>

/ {
	compatible = "mediatek,mt8188";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x000>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x400>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x500>;
			enable-method = "psci";
			clock-frequency = <2000000000>;
			capacity-dmips-mhz = <282>;
			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
		};

		cpu6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x600>;
			enable-method = "psci";
			clock-frequency = <2600000000>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
		};

		cpu7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x700>;
			enable-method = "psci";
			clock-frequency = <2600000000>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&cpu_off_b &cluster_off_b>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};

				core4 {
					cpu = <&cpu4>;
				};

				core5 {
					cpu = <&cpu5>;
				};

				core6 {
					cpu = <&cpu6>;
				};

				core7 {
					cpu = <&cpu7>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			cpu_off_l: cpu-off-l {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010000>;
				local-timer-stop;
				entry-latency-us = <50>;
				exit-latency-us = <95>;
				min-residency-us = <580>;
			};

			cpu_off_b: cpu-off-b {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010000>;
				local-timer-stop;
				entry-latency-us = <45>;
				exit-latency-us = <140>;
				min-residency-us = <740>;
			};

			cluster_off_l: cluster-off-l {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010010>;
				local-timer-stop;
				entry-latency-us = <55>;
				exit-latency-us = <155>;
				min-residency-us = <840>;
			};

			cluster_off_b: cluster-off-b {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010010>;
				local-timer-stop;
				entry-latency-us = <50>;
				exit-latency-us = <200>;
				min-residency-us = <1000>;
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <131072>;
			cache-line-size = <64>;
			cache-sets = <512>;
			next-level-cache = <&l3_0>;
			cache-unified;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <262144>;
			cache-line-size = <64>;
			cache-sets = <512>;
			next-level-cache = <&l3_0>;
			cache-unified;
		};

		l3_0: l3-cache {
			compatible = "cache";
			cache-level = <3>;
			cache-size = <2097152>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-unified;
		};
	};

	clk13m: oscillator-13m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <13000000>;
		clock-output-names = "clk13m";
	};

	clk26m: oscillator-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	gpu_opp_table: opp-table-gpu {
		compatible = "operating-points-v2";
		opp-shared;

		opp-390000000 {
			opp-hz = /bits/ 64 <390000000>;
			opp-microvolt = <575000>;
			opp-supported-hw = <0xff>;
		};
		opp-431000000 {
			opp-hz = /bits/ 64 <431000000>;
			opp-microvolt = <587500>;
			opp-supported-hw = <0xff>;
		};
		opp-473000000 {
			opp-hz = /bits/ 64 <473000000>;
			opp-microvolt = <600000>;
			opp-supported-hw = <0xff>;
		};
		opp-515000000 {
			opp-hz = /bits/ 64 <515000000>;
			opp-microvolt = <612500>;
			opp-supported-hw = <0xff>;
		};
		opp-556000000 {
			opp-hz = /bits/ 64 <556000000>;
			opp-microvolt = <625000>;
			opp-supported-hw = <0xff>;
		};
		opp-598000000 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <637500>;
			opp-supported-hw = <0xff>;
		};
		opp-640000000 {
			opp-hz = /bits/ 64 <640000000>;
			opp-microvolt = <650000>;
			opp-supported-hw = <0xff>;
		};
		opp-670000000 {
			opp-hz = /bits/ 64 <670000000>;
			opp-microvolt = <662500>;
			opp-supported-hw = <0xff>;
		};
		opp-700000000 {
			opp-hz = /bits/ 64 <700000000>;
			opp-microvolt = <675000>;
			opp-supported-hw = <0xff>;
		};
		opp-730000000 {
			opp-hz = /bits/ 64 <730000000>;
			opp-microvolt = <687500>;
			opp-supported-hw = <0xff>;
		};
		opp-760000000 {
			opp-hz = /bits/ 64 <760000000>;
			opp-microvolt = <700000>;
			opp-supported-hw = <0xff>;
		};
		opp-790000000 {
			opp-hz = /bits/ 64 <790000000>;
			opp-microvolt = <712500>;
			opp-supported-hw = <0xff>;
		};
		opp-835000000 {
			opp-hz = /bits/ 64 <835000000>;
			opp-microvolt = <731250>;
			opp-supported-hw = <0xff>;
		};
		opp-880000000 {
			opp-hz = /bits/ 64 <880000000>;
			opp-microvolt = <750000>;
			opp-supported-hw = <0xff>;
		};
		opp-915000000 {
			opp-hz = /bits/ 64 <915000000>;
			opp-microvolt = <775000>;
			opp-supported-hw = <0x8f>;
		};
		opp-915000000-5 {
			opp-hz = /bits/ 64 <915000000>;
			opp-microvolt = <762500>;
			opp-supported-hw = <0x30>;
		};
		opp-915000000-6 {
			opp-hz = /bits/ 64 <915000000>;
			opp-microvolt = <750000>;
			opp-supported-hw = <0x70>;
		};
		opp-950000000 {
			opp-hz = /bits/ 64 <950000000>;
			opp-microvolt = <800000>;
			opp-supported-hw = <0x8f>;
		};
		opp-950000000-5 {
			opp-hz = /bits/ 64 <950000000>;
			opp-microvolt = <775000>;
			opp-supported-hw = <0x30>;
		};
		opp-950000000-6 {
			opp-hz = /bits/ 64 <950000000>;
			opp-microvolt = <750000>;
			opp-supported-hw = <0x70>;
		};
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
	};

	pmu-a78 {
		compatible = "arm,cortex-a78-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
		clock-frequency = <13000000>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <4>;
			#redistributor-regions = <1>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x40000>,
			      <0 0x0c040000 0 0x200000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;

			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
				};

				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu6 &cpu7>;
				};
			};
		};

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt8188-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg_ao: syscon@10001000 {
			compatible = "mediatek,mt8188-infracfg-ao", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt8188-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8188-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11c00000 0 0x1000>,
			      <0 0x11e10000 0 0x1000>,
			      <0 0x11e20000 0 0x1000>,
			      <0 0x11ea0000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
				    "iocfg_lm", "iocfg_rt", "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 176>;
			interrupt-controller;
			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
			#interrupt-cells = <2>;
		};

		scpsys: syscon@10006000 {
			compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
			reg = <0 0x10006000 0 0x1000>;

			/* System Power Manager */
			spm: power-controller {
				compatible = "mediatek,mt8188-power-controller";
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <1>;

				/* power domain of the SoC */
				mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
					reg = <MT8188_POWER_DOMAIN_MFG0>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8188_POWER_DOMAIN_MFG1 {
						reg = <MT8188_POWER_DOMAIN_MFG1>;
						clocks = <&topckgen CLK_APMIXED_MFGPLL>,
							 <&topckgen CLK_TOP_MFG_CORE_TMP>;
						clock-names = "mfg", "alt";
						mediatek,infracfg = <&infracfg_ao>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8188_POWER_DOMAIN_MFG2 {
							reg = <MT8188_POWER_DOMAIN_MFG2>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_MFG3 {
							reg = <MT8188_POWER_DOMAIN_MFG3>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_MFG4 {
							reg = <MT8188_POWER_DOMAIN_MFG4>;
							#power-domain-cells = <0>;
						};
					};
				};

				power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
					reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
					clocks = <&topckgen CLK_TOP_VPP>,
						 <&topckgen CLK_TOP_CAM>,
						 <&topckgen CLK_TOP_CCU>,
						 <&topckgen CLK_TOP_IMG>,
						 <&topckgen CLK_TOP_VENC>,
						 <&topckgen CLK_TOP_VDEC>,
						 <&topckgen CLK_TOP_WPE_VPP>,
						 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
						 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
						 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>,
						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>,
						 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>,
						 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
						 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
						 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
						 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
						 <&vppsys0 CLK_VPP0_SMI_RSI>,
						 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
						 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
						 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>,
						 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
					clock-names = "top", "cam", "ccu", "img", "venc",
						      "vdec", "wpe", "cfgck", "cfgxo",
						      "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
						      "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
						      "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
						      "ss-sram-rdr", "ss-iommu", "ss-imgcam",
						      "ss-emi", "ss-subcmn-rdr", "ss-rsi",
						      "ss-cmn-l4", "ss-vdec1", "ss-wpe",
						      "ss-cvdo-ve1";
					mediatek,infracfg = <&infracfg_ao>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
						reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
						clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
							 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
							 <&vdosys0 CLK_VDO0_SMI_GALS>,
							 <&vdosys0 CLK_VDO0_SMI_COMMON>,
							 <&vdosys0 CLK_VDO0_SMI_EMI>,
							 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
							 <&vdosys0 CLK_VDO0_SMI_LARB>,
							 <&vdosys0 CLK_VDO0_SMI_RSI>,
							 <&vdosys0 CLK_VDO0_APB_BUS>;
						clock-names = "cfgck", "cfgxo", "ss-gals",
							      "ss-cmn", "ss-emi", "ss-iommu",
							      "ss-larb", "ss-rsi", "ss-bus";
						mediatek,infracfg = <&infracfg_ao>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
							reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
							clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
								 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
								 <&vppsys1 CLK_VPP1_GALS5>,
								 <&vppsys1 CLK_VPP1_GALS6>,
								 <&vppsys1 CLK_VPP1_LARB5>,
								 <&vppsys1 CLK_VPP1_LARB6>;
							clock-names = "cfgck", "cfgxo",
								      "ss-vpp1-g5", "ss-vpp1-g6",
								      "ss-vpp1-l5", "ss-vpp1-l6";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_VDEC1 {
							reg = <MT8188_POWER_DOMAIN_VDEC1>;
							clocks = <&vdecsys CLK_VDEC2_LARB1>;
							clock-names = "ss-vdec";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_VDEC0 {
							reg = <MT8188_POWER_DOMAIN_VDEC0>;
							clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
							clock-names = "ss-vdec";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
							reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
							clocks = <&topckgen CLK_TOP_CAM>,
								 <&topckgen CLK_TOP_CCU>,
								 <&topckgen CLK_TOP_CCU_AHB>,
								 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
							clock-names = "cam", "ccu", "bus", "cfgck";
							mediatek,infracfg = <&infracfg_ao>;
							#address-cells = <1>;
							#size-cells = <0>;
							#power-domain-cells = <1>;

							power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
								reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
								clocks = <&camsys CLK_CAM_MAIN_LARB13>,
									 <&camsys CLK_CAM_MAIN_LARB14>,
									 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
									 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
									 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>;
								clock-names= "ss-cam-l13", "ss-cam-l14",
									     "ss-cam-mm0", "ss-cam-mm1",
									     "ss-camsys";
								mediatek,infracfg = <&infracfg_ao>;
								#address-cells = <1>;
								#size-cells = <0>;
								#power-domain-cells = <1>;

								power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
									reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
									clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>,
										 <&camsys_rawb CLK_CAM_RAWB_LARBX>,
										 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
									clock-names = "ss-camb-sub",
										      "ss-camb-raw",
										      "ss-camb-yuv";
									#power-domain-cells = <0>;
								};

								power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
									reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
									clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>,
										 <&camsys_rawa CLK_CAM_RAWA_LARBX>,
										 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
									clock-names = "ss-cama-sub",
										      "ss-cama-raw",
										      "ss-cama-yuv";
									#power-domain-cells = <0>;
								};
							};
						};

						power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
							reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
							clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
								 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
								 <&vdosys1 CLK_VDO1_SMI_LARB2>,
								 <&vdosys1 CLK_VDO1_SMI_LARB3>,
								 <&vdosys1 CLK_VDO1_GALS>;
							clock-names = "cfgck", "cfgxo", "ss-larb2",
								      "ss-larb3", "ss-gals";
							mediatek,infracfg = <&infracfg_ao>;
							#address-cells = <1>;
							#size-cells = <0>;
							#power-domain-cells = <1>;

							power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
								reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
								clocks = <&topckgen CLK_TOP_HDMI_APB>,
									 <&topckgen CLK_TOP_HDCP_24M>;
								clock-names = "bus", "hdcp";
								mediatek,infracfg = <&infracfg_ao>;
								#power-domain-cells = <0>;
							};

							power-domain@MT8188_POWER_DOMAIN_DP_TX {
								reg = <MT8188_POWER_DOMAIN_DP_TX>;
								mediatek,infracfg = <&infracfg_ao>;
								#power-domain-cells = <0>;
							};

							power-domain@MT8188_POWER_DOMAIN_EDP_TX {
								reg = <MT8188_POWER_DOMAIN_EDP_TX>;
								mediatek,infracfg = <&infracfg_ao>;
								#power-domain-cells = <0>;
							};
						};

						power-domain@MT8188_POWER_DOMAIN_VENC {
							reg = <MT8188_POWER_DOMAIN_VENC>;
							clocks = <&vencsys CLK_VENC1_LARB>,
								 <&vencsys CLK_VENC1_VENC>,
								 <&vencsys CLK_VENC1_GALS>,
								 <&vencsys CLK_VENC1_GALS_SRAM>;
							clock-names = "ss-ve1-larb", "ss-ve1-core",
								      "ss-ve1-gals", "ss-ve1-sram";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_WPE {
							reg = <MT8188_POWER_DOMAIN_WPE>;
							clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
								 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>;
							clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};
					};
				};

				power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
					reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
					mediatek,infracfg = <&infracfg_ao>;
					clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
					clock-names = "ss-pextp-fmem";
					#power-domain-cells = <0>;
				};

				power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
					reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
					clocks = <&topckgen CLK_TOP_SENINF>,
						 <&topckgen CLK_TOP_SENINF1>;
					clock-names = "seninf0", "seninf1";
					#power-domain-cells = <0>;
				};

				power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
					reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
					#power-domain-cells = <0>;
				};

				power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
					reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
					clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
						 <&topckgen CLK_TOP_ADSP>;
					clock-names = "bus", "main";
					mediatek,infracfg = <&infracfg_ao>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
						reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
						mediatek,infracfg = <&infracfg_ao>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
							reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
							clocks = <&topckgen CLK_TOP_ASM_H>;
							clock-names = "asm";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_AUDIO {
							reg = <MT8188_POWER_DOMAIN_AUDIO>;
							clocks = <&topckgen CLK_TOP_A1SYS_HP>,
								 <&topckgen CLK_TOP_AUD_INTBUS>,
								 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>;
							clock-names = "a1sys", "intbus", "adspck";
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8188_POWER_DOMAIN_ADSP {
							reg = <MT8188_POWER_DOMAIN_ADSP>;
							mediatek,infracfg = <&infracfg_ao>;
							#power-domain-cells = <0>;
						};
					};
				};

				power-domain@MT8188_POWER_DOMAIN_ETHER {
					reg = <MT8188_POWER_DOMAIN_ETHER>;
					clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
					clock-names = "ethermac";
					mediatek,infracfg = <&infracfg_ao>;
					#power-domain-cells = <0>;
				};
			};
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt8188-wdt";
			reg = <0 0x10007000 0 0x100>;
			mediatek,disable-extrst;
			#reset-cells = <1>;
		};

		apmixedsys: syscon@1000c000 {
			compatible = "mediatek,mt8188-apmixedsys", "syscon";
			reg = <0 0x1000c000 0 0x1000>;
			#clock-cells = <1>;
		};

		systimer: timer@10017000 {
			compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
			reg = <0 0x10017000 0 0x1000>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk13m>;
		};

		pwrap: pwrap@10024000 {
			compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
			reg = <0 0x10024000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
			clock-names = "spi", "wrap";
		};

		gce0: mailbox@10320000 {
			compatible = "mediatek,mt8188-gce";
			reg = <0 0x10320000 0 0x4000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <2>;
			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
		};

		gce1: mailbox@10330000 {
			compatible = "mediatek,mt8188-gce";
			reg = <0 0x10330000 0 0x4000>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
			#mbox-cells = <2>;
			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
		};

		scp: scp@10500000 {
			compatible = "mediatek,mt8188-scp";
			reg = <0 0x10500000 0 0x100000>,
			      <0 0x10720000 0 0xe0000>;
			reg-names = "sram", "cfg";
			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
		};

		adsp_audio26m: clock-controller@10b91100 {
			compatible = "mediatek,mt8188-adsp-audio26m";
			reg = <0 0x10b91100 0 0x100>;
			#clock-cells = <1>;
		};

		uart0: serial@11001100 {
			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
			reg = <0 0x11001100 0 0x100>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11001200 {
			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
			reg = <0 0x11001200 0 0x100>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11001300 {
			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
			reg = <0 0x11001300 0 0x100>;
			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart3: serial@11001400 {
			compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
			reg = <0 0x11001400 0 0x100>;
			interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		auxadc: adc@11002000 {
			compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
			reg = <0 0x11002000 0 0x1000>;
			clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
			clock-names = "main";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		pericfg_ao: syscon@11003000 {
			compatible = "mediatek,mt8188-pericfg-ao", "syscon";
			reg = <0 0x11003000 0 0x1000>;
			#clock-cells = <1>;
		};

		spi0: spi@1100a000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x1000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi1: spi@11010000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11010000 0 0x1000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi2: spi@11012000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11012000 0 0x1000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi3: spi@11013000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11013000 0 0x1000>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi4: spi@11018000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11018000 0 0x1000>;
			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi5: spi@11019000 {
			compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11019000 0 0x1000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
				 <&topckgen CLK_TOP_SPI>,
				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		xhci1: usb@11200000 {
			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
			reg = <0 0x11200000 0 0x1000>,
			      <0 0x11203e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
			phys = <&u2port1 PHY_TYPE_USB2>,
			       <&u3port1 PHY_TYPE_USB3>;
			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
					  <&topckgen CLK_TOP_SSUSB_XHCI>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
				 <&topckgen CLK_TOP_SSUSB_TOP_REF>,
				 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
			clock-names = "sys_ck", "ref_ck", "mcu_ck";
			mediatek,syscon-wakeup = <&pericfg 0x468 2>;
			wakeup-source;
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
			reg = <0 0x11230000 0 0x10000>,
			      <0 0x11f50000 0 0x1000>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MSDC50_0>,
				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
				 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>;
			clock-names = "source", "hclk", "source_cg", "crypto_clk";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
			reg = <0 0x11240000 0 0x1000>,
			      <0 0x11eb0000 0 0x1000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&topckgen CLK_TOP_MSDC30_1>,
				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
			clock-names = "source", "hclk", "source_cg";
			assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
			status = "disabled";
		};

		i2c0: i2c@11280000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11280000 0 0x1000>,
			      <0 0x10220080 0 0x80>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11281000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11281000 0 0x1000>,
			      <0 0x10220180 0 0x80>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@11282000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11282000 0 0x1000>,
			      <0 0x10220280 0 0x80>;
			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_c: clock-controller@11283000 {
			compatible = "mediatek,mt8188-imp-iic-wrap-c";
			reg = <0 0x11283000 0 0x1000>;
			#clock-cells = <1>;
		};

		xhci2: usb@112a0000 {
			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
			reg = <0 0x112a0000 0 0x1000>,
			      <0 0x112a3e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
			phys = <&u2port2 PHY_TYPE_USB2>;
			assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
					  <&topckgen CLK_TOP_USB_TOP_3P>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
				 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
			clock-names = "sys_ck", "ref_ck", "mcu_ck";
			status = "disabled";
		};

		xhci0: usb@112b0000 {
			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
			reg = <0 0x112b0000 0 0x1000>,
			      <0 0x112b3e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
			phys = <&u2port0 PHY_TYPE_USB2>;
			assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
					  <&topckgen CLK_TOP_USB_TOP_2P>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
				 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
			clock-names = "sys_ck", "ref_ck", "mcu_ck";
			mediatek,syscon-wakeup = <&pericfg 0x460 2>;
			wakeup-source;
			status = "disabled";
		};

		nor_flash: spi@1132c000 {
			compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
			reg = <0 0x1132c000 0 0x1000>;
			clocks = <&topckgen CLK_TOP_SPINOR>,
				 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>,
				 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
			clock-names = "spi", "sf", "axi";
			assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
			status = "disabled";
		};

		i2c1: i2c@11e00000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11e00000 0 0x1000>,
			      <0 0x10220100 0 0x80>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@11e01000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11e01000 0 0x1000>,
			      <0 0x10220380 0 0x80>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_w: clock-controller@11e02000 {
			compatible = "mediatek,mt8188-imp-iic-wrap-w";
			reg = <0 0x11e02000 0 0x1000>;
			#clock-cells = <1>;
		};

		u3phy0: t-phy@11e30000 {
			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x11e30000 0x1000>;
			status = "disabled";

			u2port0: usb-phy@0 {
				reg = <0x0 0x700>;
				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>,
					 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
				clock-names = "ref", "da_ref";
				#phy-cells = <1>;
			};
		};

		u3phy1: t-phy@11e40000 {
			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x11e40000 0x1000>;
			status = "disabled";

			u2port1: usb-phy@0 {
				reg = <0x0 0x700>;
				clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
					 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
				clock-names = "ref", "da_ref";
				#phy-cells = <1>;
			};

			u3port1: usb-phy@700 {
				reg = <0x700 0x700>;
				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>,
					 <&clk26m>;
				clock-names = "ref", "da_ref";
				#phy-cells = <1>;
				status = "disabled";
			};
		};

		u3phy2: t-phy@11e80000 {
			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x11e80000 0x1000>;
			status = "disabled";

			u2port2: usb-phy@0 {
				reg = <0x0 0x700>;
				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>,
					 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
				clock-names = "ref", "da_ref";
				#phy-cells = <1>;
			};
		};

		i2c5: i2c@11ec0000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11ec0000 0 0x1000>,
			      <0 0x10220480 0 0x80>;
			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@11ec1000 {
			compatible = "mediatek,mt8188-i2c";
			reg = <0 0x11ec1000 0 0x1000>,
			      <0 0x10220600 0 0x80>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
			clock-div = <1>;
			clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>,
				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		imp_iic_wrap_en: clock-controller@11ec2000 {
			compatible = "mediatek,mt8188-imp-iic-wrap-en";
			reg = <0 0x11ec2000 0 0x1000>;
			#clock-cells = <1>;
		};

		gpu: gpu@13000000 {
			compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
			reg = <0 0x13000000 0 0x4000>;

			clocks = <&mfgcfg CLK_MFGCFG_BG3D>;
			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "job", "mmu", "gpu";
			operating-points-v2 = <&gpu_opp_table>;
			power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
					<&spm MT8188_POWER_DOMAIN_MFG3>,
					<&spm MT8188_POWER_DOMAIN_MFG4>;
			power-domain-names = "core0", "core1", "core2";
			status = "disabled";
		};

		mfgcfg: clock-controller@13fbf000 {
			compatible = "mediatek,mt8188-mfgcfg";
			reg = <0 0x13fbf000 0 0x1000>;
			#clock-cells = <1>;
		};

		vppsys0: clock-controller@14000000 {
			compatible = "mediatek,mt8188-vppsys0";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		wpesys: clock-controller@14e00000 {
			compatible = "mediatek,mt8188-wpesys";
			reg = <0 0x14e00000 0 0x1000>;
			#clock-cells = <1>;
		};

		wpesys_vpp0: clock-controller@14e02000 {
			compatible = "mediatek,mt8188-wpesys-vpp0";
			reg = <0 0x14e02000 0 0x1000>;
			#clock-cells = <1>;
		};

		vppsys1: clock-controller@14f00000 {
			compatible = "mediatek,mt8188-vppsys1";
			reg = <0 0x14f00000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys: clock-controller@15000000 {
			compatible = "mediatek,mt8188-imgsys";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys1_dip_top: clock-controller@15110000 {
			compatible = "mediatek,mt8188-imgsys1-dip-top";
			reg = <0 0x15110000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys1_dip_nr: clock-controller@15130000 {
			compatible = "mediatek,mt8188-imgsys1-dip-nr";
			reg = <0 0x15130000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys_wpe1: clock-controller@15220000 {
			compatible = "mediatek,mt8188-imgsys-wpe1";
			reg = <0 0x15220000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipesys: clock-controller@15330000 {
			compatible = "mediatek,mt8188-ipesys";
			reg = <0 0x15330000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys_wpe2: clock-controller@15520000 {
			compatible = "mediatek,mt8188-imgsys-wpe2";
			reg = <0 0x15520000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys_wpe3: clock-controller@15620000 {
			compatible = "mediatek,mt8188-imgsys-wpe3";
			reg = <0 0x15620000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys: clock-controller@16000000 {
			compatible = "mediatek,mt8188-camsys";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_rawa: clock-controller@1604f000 {
			compatible = "mediatek,mt8188-camsys-rawa";
			reg = <0 0x1604f000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_yuva: clock-controller@1606f000 {
			compatible = "mediatek,mt8188-camsys-yuva";
			reg = <0 0x1606f000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_rawb: clock-controller@1608f000 {
			compatible = "mediatek,mt8188-camsys-rawb";
			reg = <0 0x1608f000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys_yuvb: clock-controller@160af000 {
			compatible = "mediatek,mt8188-camsys-yuvb";
			reg = <0 0x160af000 0 0x1000>;
			#clock-cells = <1>;
		};

		ccusys: clock-controller@17200000 {
			compatible = "mediatek,mt8188-ccusys";
			reg = <0 0x17200000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys_soc: clock-controller@1800f000 {
			compatible = "mediatek,mt8188-vdecsys-soc";
			reg = <0 0x1800f000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: clock-controller@1802f000 {
			compatible = "mediatek,mt8188-vdecsys";
			reg = <0 0x1802f000 0 0x1000>;
			#clock-cells = <1>;
		};

		vencsys: clock-controller@1a000000 {
			compatible = "mediatek,mt8188-vencsys";
			reg = <0 0x1a000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdosys0: syscon@1c01d000 {
			compatible = "mediatek,mt8188-vdosys0", "syscon";
			reg = <0 0x1c01d000 0 0x1000>;
			#clock-cells = <1>;
			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
		};

		vdosys1: syscon@1c100000 {
			compatible = "mediatek,mt8188-vdosys1", "syscon";
			reg = <0 0x1c100000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
		};
	};
};