tree 7037c7fa930875fdd4a541ba629d56e801b5c386
parent 431c1646e1f86b949fa3685efc50b660a364c2b6
parent 880799fc7a3a127c43143935c1a8767d77c19cae
author Linus Torvalds <torvalds@linux-foundation.org> 1725225540 -0700
committer Linus Torvalds <torvalds@linux-foundation.org> 1725225540 -0700
mergetag object 880799fc7a3a127c43143935c1a8767d77c19cae
 type commit
 tag irq-urgent-2024-08-25
 tagger Thomas Gleixner <tglx@linutronix.de> 1724590439 +0200
 
 A set of fixes for interrupt chip drivers:
 
   - Unbreak the PLIC driver for Allwinner D1 systems
 
     The recent conversion of the PLIC driver to a platform driver broke
     Allwinnder D1 systems due to the deferred probing of platform drivers.
 
     Due to that the only timer available on D1 systems cannot get an
     interrupt, which causes the system to hang at boot. Other RISCV
     platforms are not affected because they provide the architected SBI
     timer which uses the built in core interrupt controller.
 
     Cure this by probing PLIC early on D1 systems
 
   - Cure a regression in ARM/GIC-V3 on 32-bit ARM systems caused by the
     recent addition of a initialization function, which accesses system
     registers before they are enabled. On 64-bit ARM they are enabled
     prior to that by sheer luck.
 
     Ensure they are enabled.
 
   - Cure a use before check problem in the MSI library. The existing NULL
     pointer check is too late.
 
   - Cure a lock order inversion in the ARM/GIC-V4 driver
 
   - Fix a IS_ERR() vs. NULL pointer check issue in the RISCV APLIC driver
 
   - Plug a reference count leak in the ARM/GIC-V2 driver
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Merge tag 'irq-urgent-2024-08-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
 "A set of fixes for interrupt chip drivers:

   - Unbreak the PLIC driver for Allwinner D1 systems

     The recent conversion of the PLIC driver to a platform driver broke
     Allwinnder D1 systems due to the deferred probing of platform
     drivers.

     Due to that the only timer available on D1 systems cannot get an
     interrupt, which causes the system to hang at boot. Other RISCV
     platforms are not affected because they provide the architected SBI
     timer which uses the built in core interrupt controller.

     Cure this by probing PLIC early on D1 systems

   - Cure a regression in ARM/GIC-V3 on 32-bit ARM systems caused by the
     recent addition of a initialization function, which accesses system
     registers before they are enabled. On 64-bit ARM they are enabled
     prior to that by sheer luck.

     Ensure they are enabled.

   - Cure a use before check problem in the MSI library. The existing
     NULL pointer check is too late.

   - Cure a lock order inversion in the ARM/GIC-V4 driver

   - Fix a IS_ERR() vs. NULL pointer check issue in the RISCV APLIC
     driver

   - Plug a reference count leak in the ARM/GIC-V2 driver"

* tag 'irq-urgent-2024-08-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/irq-msi-lib: Check for NULL ops in msi_lib_irq_domain_select()
  irqchip/gic-v3: Init SRE before poking sysregs
  irqchip/gic-v2m: Fix refcount leak in gicv2m_of_init()
  irqchip/riscv-aplic: Fix an IS_ERR() vs NULL bug in probe()
  irqchip/gic-v4: Fix ordering between vmapp and vpe locks
  irqchip/sifive-plic: Probe plic driver early for Allwinner D1 platform