tree be1dd5142a92968b5756b99893f4f69ea145dc0d
parent 14b14a57e642e0dab9be4e9d0866fb2c4332f7c5
author Xingyu Wu <xingyu.wu@starfivetech.com> 1689248336 +0800
committer Conor Dooley <conor.dooley@microchip.com> 1689786480 +0100

dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>