// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 NXP
 */

#include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/fsl,imx93-power.h>

#include "imx93-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		i2c0 = &lpi2c1;
		i2c1 = &lpi2c2;
		i2c2 = &lpi2c3;
		i2c3 = &lpi2c4;
		i2c4 = &lpi2c5;
		i2c5 = &lpi2c6;
		i2c6 = &lpi2c7;
		i2c7 = &lpi2c8;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &lpuart1;
		serial1 = &lpuart2;
		serial2 = &lpuart3;
		serial3 = &lpuart4;
		serial4 = &lpuart5;
		serial5 = &lpuart6;
		serial6 = &lpuart7;
		serial7 = &lpuart8;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A55_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
			#cooling-cells = <2>;
		};

		A55_1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
		};

	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	pmu {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,no-tick-in-suspend;
		interrupt-parent = <&gic>;
	};

	gic: interrupt-controller@48000000 {
		compatible = "arm,gic-v3";
		reg = <0 0x48000000 0 0x10000>,
		      <0 0x48040000 0 0xc0000>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x80000000>,
			 <0x28000000 0x0 0x28000000 0x10000000>;

		aips1: bus@44000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x44000000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			anomix_ns_gpr: syscon@44210000 {
				compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
				reg = <0x44210000 0x1000>;
			};

			mu1: mailbox@44230000 {
				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
				reg = <0x44230000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_MU1_B_GATE>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			system_counter: timer@44290000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x44290000 0x30000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_24m>;
				clock-names = "per";
				nxp,no-divider;
			};

			tpm2: pwm@44320000 {
				compatible = "fsl,imx7ulp-pwm";
				reg = <0x44320000 0x10000>;
				clocks = <&clk IMX93_CLK_TPM2_GATE>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			lpi2c1: i2c@44340000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x44340000 0x10000>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
					 <&clk IMX93_CLK_BUS_AON>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpi2c2: i2c@44350000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x44350000 0x10000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
					 <&clk IMX93_CLK_BUS_AON>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi1: spi@44360000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x44360000 0x10000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
					 <&clk IMX93_CLK_BUS_AON>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi2: spi@44370000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x44370000 0x10000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
					 <&clk IMX93_CLK_BUS_AON>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpuart1: serial@44380000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x44380000 0x1000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART1_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart2: serial@44390000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x44390000 0x1000>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART2_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			flexcan1: can@443a0000 {
				compatible = "fsl,imx93-flexcan";
				reg = <0x443a0000 0x10000>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_BUS_AON>,
					 <&clk IMX93_CLK_CAN1_GATE>;
				clock-names = "ipg", "per";
				assigned-clocks = <&clk IMX93_CLK_CAN1>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
				assigned-clock-rates = <40000000>;
				fsl,clk-source = /bits/ 8 <0>;
				status = "disabled";
			};

			iomuxc: pinctrl@443c0000 {
				compatible = "fsl,imx93-iomuxc";
				reg = <0x443c0000 0x10000>;
				status = "okay";
			};

			clk: clock-controller@44450000 {
				compatible = "fsl,imx93-ccm";
				reg = <0x44450000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1";
				status = "okay";
			};

			src: system-controller@44460000 {
				compatible = "fsl,imx93-src", "syscon";
				reg = <0x44460000 0x10000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				mediamix: power-domain@44462400 {
					compatible = "fsl,imx93-src-slice";
					reg = <0x44462400 0x400>, <0x44465800 0x400>;
					#power-domain-cells = <0>;
					clocks = <&clk IMX93_CLK_MEDIA_AXI>,
						 <&clk IMX93_CLK_MEDIA_APB>;
				};

				mlmix: power-domain@44461800 {
					compatible = "fsl,imx93-src-slice";
					reg = <0x44461800 0x400>, <0x44464800 0x400>;
					#power-domain-cells = <0>;
					clocks = <&clk IMX93_CLK_ML_APB>,
						 <&clk IMX93_CLK_ML>;
				};
			};

			anatop: anatop@44480000 {
				compatible = "fsl,imx93-anatop", "syscon";
				reg = <0x44480000 0x10000>;
			};

			adc1: adc@44530000 {
				compatible = "nxp,imx93-adc";
				reg = <0x44530000 0x10000>;
				interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_ADC1_GATE>;
				clock-names = "ipg";
				#io-channel-cells = <1>;
				status = "disabled";
			};
		};

		aips2: bus@42000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x42000000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			wakeupmix_gpr: syscon@42420000 {
				compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
				reg = <0x42420000 0x1000>;
			};

			mu2: mailbox@42440000 {
				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
				reg = <0x42440000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_MU2_B_GATE>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			tpm4: pwm@424f0000 {
				compatible = "fsl,imx7ulp-pwm";
				reg = <0x424f0000 0x10000>;
				clocks = <&clk IMX93_CLK_TPM4_GATE>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			tpm5: pwm@42500000 {
				compatible = "fsl,imx7ulp-pwm";
				reg = <0x42500000 0x10000>;
				clocks = <&clk IMX93_CLK_TPM5_GATE>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			tpm6: pwm@42510000 {
				compatible = "fsl,imx7ulp-pwm";
				reg = <0x42510000 0x10000>;
				clocks = <&clk IMX93_CLK_TPM6_GATE>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			lpi2c3: i2c@42530000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x42530000 0x10000>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpi2c4: i2c@42540000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x42540000 0x10000>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi3: spi@42550000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x42550000 0x10000>;
				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi4: spi@42560000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x42560000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpuart3: serial@42570000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x42570000 0x1000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart4: serial@42580000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x42580000 0x1000>;
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart5: serial@42590000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x42590000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart6: serial@425a0000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x425a0000 0x1000>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			flexcan2: can@425b0000 {
				compatible = "fsl,imx93-flexcan";
				reg = <0x425b0000 0x10000>;
				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
					 <&clk IMX93_CLK_CAN2_GATE>;
				clock-names = "ipg", "per";
				assigned-clocks = <&clk IMX93_CLK_CAN2>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
				assigned-clock-rates = <40000000>;
				fsl,clk-source = /bits/ 8 <0>;
				status = "disabled";
			};

			lpuart7: serial@42690000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x42690000 0x1000>;
				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART7_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpuart8: serial@426a0000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x426a0000 0x1000>;
				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPUART8_GATE>;
				clock-names = "ipg";
				status = "disabled";
			};

			lpi2c5: i2c@426b0000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x426b0000 0x10000>;
				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpi2c6: i2c@426c0000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x426c0000 0x10000>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpi2c7: i2c@426d0000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x426d0000 0x10000>;
				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpi2c8: i2c@426e0000 {
				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
				reg = <0x426e0000 0x10000>;
				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi5: spi@426f0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x426f0000 0x10000>;
				interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi6: spi@42700000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x42700000 0x10000>;
				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi7: spi@42710000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x42710000 0x10000>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

			lpspi8: spi@42720000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
				reg = <0x42720000 0x10000>;
				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
					 <&clk IMX93_CLK_BUS_WAKEUP>;
				clock-names = "per", "ipg";
				status = "disabled";
			};

		};

		aips3: bus@42800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x42800000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usdhc1: mmc@42850000 {
				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x42850000 0x10000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
					 <&clk IMX93_CLK_WAKEUP_AXI>,
					 <&clk IMX93_CLK_USDHC1_GATE>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <8>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};

			usdhc2: mmc@42860000 {
				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x42860000 0x10000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
					 <&clk IMX93_CLK_WAKEUP_AXI>,
					 <&clk IMX93_CLK_USDHC2_GATE>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};

			eqos: ethernet@428a0000 {
				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
				reg = <0x428a0000 0x10000>;
				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "eth_wake_irq", "macirq";
				clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER2>,
					 <&clk IMX93_CLK_ENET>,
					 <&clk IMX93_CLK_ENET_QOS_GATE>;
				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
						  <&clk IMX93_CLK_ENET>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
				assigned-clock-rates = <100000000>, <250000000>;
				intf_mode = <&wakeupmix_gpr 0x28>;
				clk_csr = <0>;
				status = "disabled";
			};

			fec: ethernet@42890000 {
				compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x42890000 0x10000>;
				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET1_GATE>,
					 <&clk IMX93_CLK_ENET_TIMER1>,
					 <&clk IMX93_CLK_ENET_REF>,
					 <&clk IMX93_CLK_ENET_REF_PHY>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
						  <&clk IMX93_CLK_ENET_REF>,
						  <&clk IMX93_CLK_ENET_REF_PHY>;
				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
				assigned-clock-rates = <100000000>, <250000000>, <50000000>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				status = "disabled";
			};

			usdhc3: mmc@428b0000 {
				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x428b0000 0x10000>;
				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
					 <&clk IMX93_CLK_WAKEUP_AXI>,
					 <&clk IMX93_CLK_USDHC3_GATE>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};
		};

		gpio2: gpio@43810080 {
			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
			reg = <0x43810080 0x1000>, <0x43810040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO2_GATE>,
				 <&clk IMX93_CLK_GPIO2_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 4 30>;
		};

		gpio3: gpio@43820080 {
			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
			reg = <0x43820080 0x1000>, <0x43820040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO3_GATE>,
				 <&clk IMX93_CLK_GPIO3_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
				      <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
		};

		gpio4: gpio@43830080 {
			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
			reg = <0x43830080 0x1000>, <0x43830040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO4_GATE>,
				 <&clk IMX93_CLK_GPIO4_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
		};

		gpio1: gpio@47400080 {
			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
			reg = <0x47400080 0x1000>, <0x47400040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO1_GATE>,
				 <&clk IMX93_CLK_GPIO1_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 92 16>;
		};

		s4muap: mailbox@47520000 {
			compatible = "fsl,imx93-mu-s4";
			reg = <0x47520000 0x10000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";
			#mbox-cells = <2>;
		};

		media_blk_ctrl: system-controller@4ac10000 {
			compatible = "fsl,imx93-media-blk-ctrl", "syscon";
			reg = <0x4ac10000 0x10000>;
			power-domains = <&mediamix>;
			clocks = <&clk IMX93_CLK_MEDIA_APB>,
				 <&clk IMX93_CLK_MEDIA_AXI>,
				 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
				 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
				 <&clk IMX93_CLK_CAM_PIX>,
				 <&clk IMX93_CLK_PXP_GATE>,
				 <&clk IMX93_CLK_LCDIF_GATE>,
				 <&clk IMX93_CLK_ISI_GATE>,
				 <&clk IMX93_CLK_MIPI_CSI_GATE>,
				 <&clk IMX93_CLK_MIPI_DSI_GATE>;
			clock-names = "apb", "axi", "nic", "disp", "cam",
				      "pxp", "lcdif", "isi", "csi", "dsi";
			#power-domain-cells = <1>;
			status = "disabled";
		};
	};
};