// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
 *
 *  Copyright (C) 2014 Atmel,
 *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
 */

#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D4 family SoC";
	compatible = "atmel,sama5d4";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &usart3;
		serial1 = &usart4;
		serial2 = &usart2;
		serial3 = &usart0;
		serial4 = &usart1;
		serial5 = &uart0;
		serial6 = &uart1;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		gpio4 = &pioE;
		pwm0 = &pwm0;
		ssc0 = &ssc0;
		ssc1 = &ssc1;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
	};
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x20000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
		};
	};

	ns_sram: sram@210000 {
		compatible = "mmio-sram";
		reg = <0x00210000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00210000 0x10000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nfc_sram: sram@100000 {
			compatible = "mmio-sram";
			no-memory-wc;
			reg = <0x100000 0x2400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x100000 0x2400>;
		};

		vdec0: vdec@300000 {
			compatible = "microchip,sama5d4-vdec";
			reg = <0x00300000 0x100000>;
			interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
		};

		usb0: gadget@400000 {
			compatible = "atmel,sama5d3-udc";
			reg = <0x00400000 0x100000
			       0xfc02c000 0x4000>;
			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
			clock-names = "pclk", "hclk";
			status = "disabled";
		};

		usb1: ohci@500000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00500000 0x100000>;
			interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@600000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00600000 0x100000>;
			interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		L2: cache-controller@a00000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a00000 0x1000>;
			interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
			cache-unified;
			cache-level = <2>;
		};

		ebi: ebi@10000000 {
			compatible = "atmel,sama5d3-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&hsmc>;
			reg = <0x10000000 0x10000000
			       0x60000000 0x28000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x60000000 0x10000000
				  0x2 0x0 0x70000000 0x10000000
				  0x3 0x0 0x80000000 0x8000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,sama5d3-nand-controller";
				atmel,nfc-sram = <&nfc_sram>;
				atmel,nfc-io = <&nfc_io>;
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		nfc_io: nfc-io@90000000 {
			compatible = "atmel,sama5d3-nfc-io", "syscon";
			reg = <0x90000000 0x8000000>;
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			hlcdc: hlcdc@f0000000 {
				compatible = "atmel,sama5d4-hlcdc";
				reg = <0xf0000000 0x4000>;
				interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
				clock-names = "periph_clk","sys_clk", "slow_clk";
				status = "disabled";

				hlcdc-display-controller {
					compatible = "atmel,hlcdc-display-controller";
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						reg = <0>;
					};
				};

				hlcdc_pwm: hlcdc-pwm {
					compatible = "atmel,hlcdc-pwm";
					pinctrl-names = "default";
					pinctrl-0 = <&pinctrl_lcd_pwm>;
					#pwm-cells = <3>;
				};
			};

			dma1: dma-controller@f0004000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0004000 0x200>;
				interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
				clock-names = "dma_clk";
			};

			isi: isi@f0008000 {
				compatible = "atmel,at91sam9g45-isi";
				reg = <0xf0008000 0x4000>;
				interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isi_data_0_7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
				clock-names = "isi_clk";
				status = "disabled";
				port {
					#address-cells = <1>;
					#size-cells = <0>;
				};
			};

			ramc0: ramc@f0010000 {
				compatible = "atmel,sama5d3-ddramc";
				reg = <0xf0010000 0x200>;
				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
				clock-names = "ddrck", "mpddr";
			};

			dma0: dma-controller@f0014000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0014000 0x200>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
				clock-names = "dma_clk";
			};

			pmc: pmc@f0018000 {
				compatible = "atmel,sama5d4-pmc", "syscon";
				reg = <0xf0018000 0x120>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				#clock-cells = <2>;
				clocks = <&clk32k>, <&main_xtal>;
				clock-names = "slow_clk", "main_xtal";
			};

			mmc0: mmc@f8000000 {
				compatible = "atmel,hsmci";
				reg = <0xf8000000 0x600>;
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(0))>;
				dma-names = "rxtx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
				clock-names = "mci_clk";
			};

			uart0: serial@f8004000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8004000 0x100>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(22))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(23))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
				clock-names = "usart";
				status = "disabled";
			};

			ssc0: ssc@f8008000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf8008000 0x4000>;
				interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(26))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(27))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
				clock-names = "pclk";
				status = "disabled";
			};

			pwm0: pwm@f800c000 {
				compatible = "atmel,sama5d3-pwm";
				reg = <0xf800c000 0x300>;
				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
				#pwm-cells = <3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
				status = "disabled";
			};

			spi0: spi@f8010000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8010000 0x100>;
				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(10))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(11))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			i2c0: i2c@f8014000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8014000 0x4000>;
				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(2))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(3))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c0>;
				pinctrl-1 = <&pinctrl_i2c0_gpio>;
				sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
				status = "disabled";
			};

			i2c1: i2c@f8018000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8018000 0x4000>;
				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(4))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(5))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c1>;
				pinctrl-1 = <&pinctrl_i2c1_gpio>;
				sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
				status = "disabled";
			};

			tcb0: timer@f801c000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf801c000 0x100>;
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			macb0: ethernet@f8020000 {
				compatible = "atmel,sama5d4-gem";
				reg = <0xf8020000 0x100>;
				interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_rmii>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			i2c2: i2c@f8024000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8024000 0x4000>;
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(6))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(7))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c2>;
				pinctrl-1 = <&pinctrl_i2c2_gpio>;
				sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
				status = "disabled";
			};

			sfr: sfr@f8028000 {
				compatible = "atmel,sama5d4-sfr", "syscon";
				reg = <0xf8028000 0x60>;
			};

			usart0: serial@f802c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf802c000 0x100>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(36))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(37))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
				clock-names = "usart";
				status = "disabled";
			};

			usart1: serial@f8030000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8030000 0x100>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(38))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(39))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
				clock-names = "usart";
				status = "disabled";
			};

			mmc1: mmc@fc000000 {
				compatible = "atmel,hsmci";
				reg = <0xfc000000 0x600>;
				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(1))>;
				dma-names = "rxtx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
				clock-names = "mci_clk";
			};

			uart1: serial@fc004000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc004000 0x100>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(24))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(25))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
				clock-names = "usart";
				status = "disabled";
			};

			usart2: serial@fc008000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc008000 0x100>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(16))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(17))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
				clock-names = "usart";
				status = "disabled";
			};

			usart3: serial@fc00c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc00c000 0x100>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(18))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(19))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
				clock-names = "usart";
				status = "disabled";
			};

			usart4: serial@fc010000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc010000 0x100>;
				interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(20))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(21))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart4>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
				clock-names = "usart";
				status = "disabled";
			};

			ssc1: ssc@fc014000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfc014000 0x4000>;
				interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(28))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(29))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
				clock-names = "pclk";
				status = "disabled";
			};

			spi1: spi@fc018000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc018000 0x100>;
				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(12))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(13))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			spi2: spi@fc01c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc01c000 0x100>;
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(14))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(15))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			tcb1: timer@fc020000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xfc020000 0x100>;
				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			tcb2: timer@fc024000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xfc024000 0x100>;
				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			macb1: ethernet@fc028000 {
				compatible = "atmel,sama5d4-gem";
				reg = <0xfc028000 0x100>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb1_rmii>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			trng@fc030000 {
				compatible = "atmel,at91sam9g45-trng";
				reg = <0xfc030000 0x100>;
				interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
			};

			adc0: adc@fc034000 {
				compatible = "atmel,at91sam9x5-adc";
				reg = <0xfc034000 0x100>;
				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
					 <&adc_op_clk>;
				clock-names = "adc_clk", "adc_op_clk";
				atmel,adc-channels-used = <0x01f>;
				atmel,adc-startup-time = <40>;
				atmel,adc-use-external-triggers;
				atmel,adc-vref = <3000>;
				atmel,adc-sample-hold-time = <11>;
				atmel,adc-ts-pressure-threshold = <10000>;
				status = "disabled";
			};

			aes@fc044000 {
				compatible = "atmel,at91sam9g46-aes";
				reg = <0xfc044000 0x100>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(41))>,
				       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(40))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
				clock-names = "aes_clk";
				status = "okay";
			};

			tdes@fc04c000 {
				compatible = "atmel,at91sam9g46-tdes";
				reg = <0xfc04c000 0x100>;
				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(42))>,
				       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(43))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
				clock-names = "tdes_clk";
				status = "okay";
			};

			sha@fc050000 {
				compatible = "atmel,at91sam9g46-sha";
				reg = <0xfc050000 0x100>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(44))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
				clock-names = "sha_clk";
				status = "okay";
			};

			hsmc: smc@fc05c000 {
				compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
				reg = <0xfc05c000 0x1000>;
				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pmecc: ecc-engine@ffffc070 {
					compatible = "atmel,sama5d4-pmecc";
					reg = <0xfc05c070 0x490>,
					      <0xfc05c500 0x100>;
				};
			};

			reset_controller: rstc@fc068600 {
				compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
				reg = <0xfc068600 0x10>;
				clocks = <&clk32k>;
			};

			shutdown_controller: shdwc@fc068610 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfc068610 0x10>;
				clocks = <&clk32k>;
			};

			pit: timer@fc068630 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfc068630 0x10>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
			};

			watchdog: watchdog@fc068640 {
				compatible = "atmel,sama5d4-wdt";
				reg = <0xfc068640 0x10>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			clk32k: sckc@fc068650 {
				compatible = "atmel,sama5d4-sckc";
				reg = <0xfc068650 0x4>;
				#clock-cells = <0>;
				clocks = <&slow_xtal>;
			};

			rtc@fc0686b0 {
				compatible = "atmel,sama5d4-rtc";
				reg = <0xfc0686b0 0x30>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
			};

			dbgu: serial@fc069000 {
				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
				reg = <0xfc069000 0x200>;
				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
				clock-names = "usart";
				status = "disabled";
			};


			pinctrl: pinctrl@fc06a000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
				ranges = <0xfc068000 0xfc068000 0x100
					  0xfc06a000 0xfc06a000 0x4000>;
				/* WARNING: revisit as pin spec has changed */
				atmel,mux-mask = <
					/*   A          B          C  */
					0xffffffff 0x3ffcfe7c 0x1c010101	/* pioA */
					0x7fffffff 0xfffccc3a 0x3f00cc3a	/* pioB */
					0xffffffff 0x3ff83fff 0xff00ffff	/* pioC */
					0xb003ff00 0x8002a800 0x00000000	/* pioD */
					0xffffffff 0x7fffffff 0x76fff1bf	/* pioE */
					>;

				pioA: gpio@fc06a000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06a000 0x100>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
				};

				pioB: gpio@fc06b000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06b000 0x100>;
					interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
				};

				pioC: gpio@fc06c000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06c000 0x100>;
					interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
				};

				pioD: gpio@fc068000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc068000 0x100>;
					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
				};

				pioE: gpio@fc06d000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06d000 0x100>;
					interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
				};

				/* pinctrl pin settings */
				adc0 {
					pinctrl_adc0_adtrg: adc0_adtrg {
						atmel,pins =
							<AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* conflicts with USBA_VBUS */
					};
					pinctrl_adc0_ad0: adc0_ad0 {
						atmel,pins =
							<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad1: adc0_ad1 {
						atmel,pins =
							<AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad2: adc0_ad2 {
						atmel,pins =
							<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad3: adc0_ad3 {
						atmel,pins =
							<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad4: adc0_ad4 {
						atmel,pins =
							<AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* conflicts with D14 and TDI */
							 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;		/* conflicts with D15 and TDO */
					};
				};

				ebi {
					pinctrl_ebi_addr: ebi-addr-0 {
						atmel,pins =
							<AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nand_addr: ebi-addr-1 {
						atmel,pins =
							<AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs0: ebi-cs0-0 {
						atmel,pins =
							<AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs1: ebi-cs1-0 {
						atmel,pins =
							<AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs2: ebi-cs2-0 {
						atmel,pins =
							<AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs3: ebi-cs3-0 {
						atmel,pins =
							<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
						atmel,pins =
							<AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_data_8_15: ebi-data-msb-0 {
						atmel,pins =
							<AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
						atmel,pins =
							<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
						atmel,pins =
							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwait: ebi-nwait-0 {
						atmel,pins =
							<AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
						atmel,pins =
							<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				i2c0 {
					pinctrl_i2c0: i2c0-0 {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_i2c0_gpio: i2c0-gpio {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				i2c1 {
					pinctrl_i2c1: i2c1-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE	/* TWD1, conflicts with UART0 RX and DIBP */
							 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* TWCK1, conflicts with UART0 TX and DIBN */
					};

					pinctrl_i2c1_gpio: i2c1-gpio {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				i2c2 {
					pinctrl_i2c2: i2c2-0 {
						atmel,pins =
							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* TWD2, conflicts with RD0 and PWML1 */
							 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
					};

					pinctrl_i2c2_gpio: i2c2-gpio {
						atmel,pins =
							<AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				isi {
					pinctrl_isi_data_0_7: isi-0-data-0-7 {
						atmel,pins =
							<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D0 */
							 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D1 */
							 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D2 */
							 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D3 */
							 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D4 */
							 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D5 */
							 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D6 */
							 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D7 */
							 AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_PCK, conflict with G0_RXCK */
							 AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_VSYNC */
							 AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_HSYNC */
					};
					pinctrl_isi_data_8_9: isi-0-data-8-9 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
							 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
					};
					pinctrl_isi_data_10_11: isi-0-data-10-11 {
						atmel,pins =
							<AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
							 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
					};
				};

				lcd {
					pinctrl_lcd_base: lcd-base-0 {
						atmel,pins =
							<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDVSYNC */
							 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDHSYNC */
							 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDEN */
							 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPCK */
					};
					pinctrl_lcd_pwm: lcd-pwm-0 {
						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPWM */
					};
					pinctrl_lcd_rgb444: lcd-rgb-0 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD11 pin */
					};
					pinctrl_lcd_rgb565: lcd-rgb-1 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD15 pin */
					};
					pinctrl_lcd_rgb666: lcd-rgb-2 {
						atmel,pins =
							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
					pinctrl_lcd_rgb777: lcd-rgb-3 {
						atmel,pins =
							 /* LCDDAT0 conflicts with TMS */
							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 /* LCDDAT8 conflicts with TCK */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 /* LCDDAT16 conflicts with NTRST */
							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
					pinctrl_lcd_rgb888: lcd-rgb-4 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
				};

				macb0 {
					pinctrl_macb0_rmii: macb0_rmii-0 {
						atmel,pins =
							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TX0 */
							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TX1 */
							 AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RX0 */
							 AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RX1 */
							 AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RXDV */
							 AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RXER */
							 AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TXEN */
							 AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TXCK */
							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_MDC */
							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_MDIO */
							>;
					};
				};

				macb1 {
					pinctrl_macb1_rmii: macb1_rmii-0 {
						atmel,pins =
							<AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TX0 */
							 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TX1 */
							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RX0 */
							 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RX1 */
							 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RXDV */
							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RXER */
							 AT91_PIOA  4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TXEN */
							 AT91_PIOA  2 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TXCK */
							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_MDC */
							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_MDIO */
							>;
					};
				};

				mmc0 {
					pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
						atmel,pins =
							<AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* MCI0_CK, conflict with PCK1(ISI_MCK) */
							 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_CDA, conflict with NAND_D0 */
							 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA0, conflict with NAND_D1 */
							>;
					};
					pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
						atmel,pins =
							<AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA1, conflict with NAND_D2 */
							 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA2, conflict with NAND_D3 */
							 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA3, conflict with NAND_D4 */
							>;
					};
					pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
						atmel,pins =
							<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA4, conflict with NAND_D5 */
							 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA5, conflict with NAND_D6 */
							 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA6, conflict with NAND_D7 */
							 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA7, conflict with NAND_OE */
							>;
					};
				};

				mmc1 {
					pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
						atmel,pins =
							<AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE		/* MCI1_CK */
							 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_CDA */
							 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA0 */
							>;
					};
					pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
						atmel,pins =
							<AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA1 */
							 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA2 */
							 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA3 */
							>;
					};
				};

				nand0 {
					pinctrl_nand: nand-0 {
						atmel,pins =
							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC13 periph A Read Enable */
							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC14 periph A Write Enable */

							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC17 ALE */
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC18 CLE */

							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC15 NCS3/Chip Enable */
							 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC16 NANDRDY */
							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC5 Data bit 0 */
							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC6 Data bit 1 */
							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC7 Data bit 2 */
							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC8 Data bit 3 */
							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC9 Data bit 4 */
							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC10 Data bit 5 */
							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC11 periph A Data bit 6 */
							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC12 periph A Data bit 7 */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_MISO */
							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_MOSI */
							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_SPCK */
							>;
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx {
						atmel,pins =
							<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TK0 */
							 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TF0 */
							 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* TD0 */
					};

					pinctrl_ssc0_rx: ssc0_rx {
						atmel,pins =
							<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RK0 */
							 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RF0 */
							 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* RD0 */
					};
				};

				ssc1 {
					pinctrl_ssc1_tx: ssc1_tx {
						atmel,pins =
							<AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TK1 */
							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TF1 */
							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* TD1 */
					};

					pinctrl_ssc1_rx: ssc1_rx {
						atmel,pins =
							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RK1 */
							 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RF1 */
							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* RD1 */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_MISO */
							 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_MOSI */
							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_SPCK */
							>;
					};
				};

				spi2 {
					pinctrl_spi2: spi2-0 {
						atmel,pins =
							<AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_MISO conflicts with RTS0 */
							 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_MOSI conflicts with TXD0 */
							 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_SPCK conflicts with RTS1 */
							>;
					};
				};

				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart1_rts: usart1_rts-0 {
						atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_usart1_cts: usart1_cts-0 {
						atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP		/* RXD - conflicts with G0_CRS, ISI_HSYNC */
							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD - conflicts with G0_COL, PCK2 */
							>;
					};
					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with G0_RX3, PWMH1 */
					};
					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with G0_TXER, ISI_VSYNC */
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				usart4 {
					pinctrl_usart4: usart4-0 {
						atmel,pins =
							<AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart4_rts: usart4_rts-0 {
						atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with NWAIT, A19 */
					};
					pinctrl_usart4_cts: usart4_cts-0 {
						atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with A0/NBS0, MCI0_CDB */
					};
				};
			};

			aic: interrupt-controller@fc06e000 {
				#interrupt-cells = <3>;
				compatible = "atmel,sama5d4-aic";
				interrupt-controller;
				reg = <0xfc06e000 0x200>;
				atmel,external-irqs = <56>;
			};
		};
	};
};