// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1028A QDS Board.
 *
 * Copyright 2018 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls1028a.dtsi"

/ {
	model = "LS1028A QDS Board";
	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";

	aliases {
		crypto = &crypto;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		serial0 = &duart0;
		serial1 = &duart1;
		mmc0 = &esdhc;
		mmc1 = &esdhc1;
		rtc1 = &ftm_alarm0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x1 0x00000000>;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai1>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			frame-master;
			bitclock-master;
			system-clock-frequency = <25000000>;
		};
	};

	mdio-mux {
		compatible = "mdio-mux-multiplexer";
		mux-controls = <&mux 0>;
		mdio-parent-bus = <&enetc_mdio_pf3>;
		#address-cells=<1>;
		#size-cells = <0>;

		/* on-board RGMII PHY */
		mdio@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			qds_phy1: ethernet-phy@5 {
				/* Atheros 8035 */
				reg = <5>;
			};
		};
	};
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&dspi1 {
	bus-num = <1>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&dspi2 {
	bus-num = <2>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	status = "okay";
};

&esdhc1 {
	status = "okay";
};

&fspi {
	status = "okay";

	mt35xu02g0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
		reg = <0>;
	};
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			current-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			current-monitor@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x5>;

			sgtl5000: audio-codec@a {
				#sound-dai-cells = <0>;
				compatible = "fsl,sgtl5000";
				reg = <0xa>;
				VDDA-supply = <&reg_1p8v>;
				VDDIO-supply = <&reg_1p8v>;
				clocks = <&sys_mclk>;
			};
		};
	};

	fpga@66 {
		compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
			     "simple-mfd";
		reg = <0x66>;

		mux: mux-controller {
			compatible = "reg-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
		};
	};

};

&enetc_port1 {
	phy-handle = <&qds_phy1>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&lpuart0 {
	status = "okay";
};

&sai1 {
	status = "okay";
};

&sata {
	status = "okay";
};