arch/arm64/boot/dts/freescale/imx8qxp.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &lsio_gpio0;
		gpio1 = &lsio_gpio1;
		gpio2 = &lsio_gpio2;
		gpio3 = &lsio_gpio3;
		gpio4 = &lsio_gpio4;
		gpio5 = &lsio_gpio5;
		gpio6 = &lsio_gpio6;
		gpio7 = &lsio_gpio7;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mu0 = &lsio_mu0;
		mu1 = &lsio_mu1;
		mu2 = &lsio_mu2;
		mu3 = &lsio_mu3;
		mu4 = &lsio_mu4;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/* We have 1 clusters with 4 Cortex-A35 cores */
		A35_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	a35_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <150000>;
		};

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_reserved: dsp@92400000 {
			reg = <0 0x92400000 0 0x2000000>;
			no-map;
		};
	};

	pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	scu {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0",
			     "rx0",
			     "gip3";
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 1 0
			  &lsio_mu1 3 3>;

		pd: imx8qx-pd {
			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

		clk: clock-controller {
			compatible = "fsl,imx8qxp-clk";
			#clock-cells = <2>;
			clocks = <&xtal32k &xtal24m>;
			clock-names = "xtal_32KHz", "xtal_24Mhz";
		};

		iomuxc: pinctrl {
			compatible = "fsl,imx8qxp-iomuxc";
		};

		ocotp: imx8qx-ocotp {
			compatible = "fsl,imx8qxp-scu-ocotp";
			#address-cells = <1>;
			#size-cells = <1>;
		};

		scu_key: scu-key {
			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
			linux,keycodes = <KEY_POWER>;
			status = "disabled";
		};

		rtc: rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};

		watchdog {
			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
			timeout-sec = <60>;
		};

		tsens: thermal-sensor {
			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	xtal32k: clock-xtal32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "xtal_32KHz";
	};

	xtal24m: clock-xtal24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xtal_24MHz";
	};

	thermal_zones: thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;

			trips {
				cpu_alert0: trip0 {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <127000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	/* sorted in register address */
	#include "imx8-ss-img.dtsi"
	#include "imx8-ss-adma.dtsi"
	#include "imx8-ss-conn.dtsi"
	#include "imx8-ss-ddr.dtsi"
	#include "imx8-ss-lsio.dtsi"
};

#include "imx8qxp-ss-img.dtsi"
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"