// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8560 ADS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 */

/dts-v1/;

/include/ "e500v2_power_isa.dtsi"

/ {
	model = "MPC8560ADS";
	compatible = "MPC8560ADS", "MPC85xxADS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8560@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <82500000>;
			bus-frequency = <330000000>;
			clock-frequency = <825000000>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x10000000>;
	};

	soc8560@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <330000000>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8560-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8540-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8540-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8560-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <7 1>;
					reg = <0x2>;
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <7 1>;
					reg = <0x3>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x4000 0x9000 0x2000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8560-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
				clock-frequency = <165000000>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <46 2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
			};

			serial0: serial@91a00 {
				device_type = "serial";
				compatible = "fsl,mpc8560-scc-uart",
				             "fsl,cpm2-scc-uart";
				reg = <0x91a00 0x20 0x88000 0x100>;
				fsl,cpm-brg = <1>;
				fsl,cpm-command = <0x800000>;
				current-speed = <115200>;
				interrupts = <40 8>;
				interrupt-parent = <&cpmpic>;
			};

			serial1: serial@91a20 {
				device_type = "serial";
				compatible = "fsl,mpc8560-scc-uart",
				             "fsl,cpm2-scc-uart";
				reg = <0x91a20 0x20 0x88100 0x100>;
				fsl,cpm-brg = <2>;
				fsl,cpm-command = <0x4a00000>;
				current-speed = <115200>;
				interrupts = <41 8>;
				interrupt-parent = <&cpmpic>;
			};

			enet2: ethernet@91320 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x16200300>;
				interrupts = <33 8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy2>;
			};

			enet3: ethernet@91340 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x1a400300>;
				interrupts = <34 8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy3>;
			};
		};
	};

	pci0: pci@e0008000 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
		reg = <0xe0008000 0x1000>;
		clock-frequency = <66666666>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x2 */
				 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
				 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
				 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
				 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1

				/* IDSEL 0x3 */
				 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
				 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
				 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
				 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 0x4 */
				 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
				 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
				 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
				 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1

				/* IDSEL 0x5  */
				 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
				 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
				 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
				 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDSEL 12 */
				 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
				 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
				 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
				 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1

				/* IDSEL 13 */
				 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
				 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
				 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
				 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 14*/
				 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
				 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
				 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
				 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1

				/* IDSEL 15 */
				 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
				 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
				 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
				 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1

				/* IDSEL 18 */
				 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
				 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
				 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
				 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1

				/* IDSEL 19 */
				 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
				 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
				 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
				 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1

				/* IDSEL 20 */
				 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
				 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
				 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
				 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1

				/* IDSEL 21 */
				 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
				 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
				 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
				 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
	};
};