| /* |
| * Copyright (C) 2020 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _dcn_3_1_2_OFFSET_HEADER |
| #define _dcn_3_1_2_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: dce_dc_hda_azcontroller_azdec |
| // base address: 0x1300000 |
| #define regAZCONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000 |
| #define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX 3 |
| #define regAZCONTROLLER0_MINOR_VERSION 0x4b7000 |
| #define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX 3 |
| #define regAZCONTROLLER0_MAJOR_VERSION 0x4b7000 |
| #define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX 3 |
| #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001 |
| #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 |
| #define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001 |
| #define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 |
| #define regAZCONTROLLER0_GLOBAL_CONTROL 0x4b7002 |
| #define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX 3 |
| #define regAZCONTROLLER0_WAKE_ENABLE 0x4b7003 |
| #define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX 3 |
| #define regAZCONTROLLER0_STATE_CHANGE_STATUS 0x4b7003 |
| #define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_GLOBAL_STATUS 0x4b7004 |
| #define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 |
| #define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 |
| #define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 |
| #define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 |
| #define regAZCONTROLLER0_INTERRUPT_CONTROL 0x4b7008 |
| #define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX 3 |
| #define regAZCONTROLLER0_INTERRUPT_STATUS 0x4b7009 |
| #define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_WALL_CLOCK_COUNTER 0x4b700c |
| #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX 3 |
| #define regAZCONTROLLER0_STREAM_SYNCHRONIZATION 0x4b700e |
| #define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS 0x4b7010 |
| #define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS 0x4b7011 |
| #define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 |
| #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 |
| #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 |
| #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_STATUS 0x4b7013 |
| #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_CORB_SIZE 0x4b7013 |
| #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 |
| #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 |
| #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 |
| #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 |
| #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 |
| #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 |
| #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 |
| #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 |
| #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 |
| #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 |
| #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a |
| #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 |
| #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c |
| #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d |
| #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 |
| #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c |
| #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hda_azendpoint_azdec |
| // base address: 0x1300000 |
| #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 |
| #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 |
| #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 |
| #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hda_azinputendpoint_azdec |
| // base address: 0x1300000 |
| #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 |
| #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 |
| #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 |
| #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] |
| // base address: 0x48 |
| #define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 |
| #define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 |
| #define regVGA_MEM_READ_PAGE_ADDR 0x0001 |
| #define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] |
| // base address: 0x3b4 |
| #define regCRTC8_IDX 0x002d |
| #define regCRTC8_IDX_BASE_IDX 1 |
| #define regCRTC8_DATA 0x002d |
| #define regCRTC8_DATA_BASE_IDX 1 |
| #define regGENFC_WT 0x002e |
| #define regGENFC_WT_BASE_IDX 1 |
| #define regGENS1 0x002e |
| #define regGENS1_BASE_IDX 1 |
| #define regATTRDW 0x0030 |
| #define regATTRDW_BASE_IDX 1 |
| #define regATTRX 0x0030 |
| #define regATTRX_BASE_IDX 1 |
| #define regATTRDR 0x0030 |
| #define regATTRDR_BASE_IDX 1 |
| #define regGENMO_WT 0x0030 |
| #define regGENMO_WT_BASE_IDX 1 |
| #define regGENS0 0x0030 |
| #define regGENS0_BASE_IDX 1 |
| #define regGENENB 0x0030 |
| #define regSEQ8_IDX 0x0031 |
| #define regSEQ8_IDX_BASE_IDX 1 |
| #define regSEQ8_DATA 0x0031 |
| #define regSEQ8_DATA_BASE_IDX 1 |
| #define regDAC_MASK 0x0031 |
| #define regDAC_MASK_BASE_IDX 1 |
| #define regDAC_R_INDEX 0x0031 |
| #define regDAC_R_INDEX_BASE_IDX 1 |
| #define regDAC_W_INDEX 0x0032 |
| #define regDAC_W_INDEX_BASE_IDX 1 |
| #define regDAC_DATA 0x0032 |
| #define regDAC_DATA_BASE_IDX 1 |
| #define regGENFC_RD 0x0032 |
| #define regGENFC_RD_BASE_IDX 1 |
| #define regGENMO_RD 0x0033 |
| #define regGENMO_RD_BASE_IDX 1 |
| #define regGRPH8_IDX 0x0033 |
| #define regGRPH8_IDX_BASE_IDX 1 |
| #define regGRPH8_DATA 0x0033 |
| #define regGRPH8_DATA_BASE_IDX 1 |
| #define regCRTC8_IDX_1 0x0035 |
| #define regCRTC8_IDX_1_BASE_IDX 1 |
| #define regCRTC8_DATA_1 0x0035 |
| #define regCRTC8_DATA_1_BASE_IDX 1 |
| #define regGENFC_WT_1 0x0036 |
| #define regGENFC_WT_1_BASE_IDX 1 |
| #define regGENS1_1 0x0036 |
| #define regGENS1_1_BASE_IDX 1 |
| |
| |
| // addressBlock: dce_dc_hda_azcontroller_azdec |
| // base address: 0x0 |
| #define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 |
| #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 |
| #define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 |
| #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 |
| #define regAZCONTROLLER1_CORB_CONTROL 0x0001 |
| #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 |
| #define regAZCONTROLLER1_CORB_STATUS 0x0001 |
| #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 |
| #define regAZCONTROLLER1_CORB_SIZE 0x0001 |
| #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 |
| #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 |
| #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 |
| #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 |
| #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 |
| #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_CONTROL 0x0005 |
| #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_STATUS 0x0005 |
| #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 |
| #define regAZCONTROLLER1_RIRB_SIZE 0x0005 |
| #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 |
| #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 |
| #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 |
| #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 |
| #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a |
| #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 |
| #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b |
| #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 |
| #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c |
| #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 |
| |
| |
| // addressBlock: dce_dc_hda_azendpoint_azdec |
| // base address: 0x0 |
| #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 |
| #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 |
| #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 |
| #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 |
| |
| |
| // addressBlock: dce_dc_hda_azinputendpoint_azdec |
| // base address: 0x0 |
| #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 |
| #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 |
| #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 |
| #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 |
| |
| |
| // addressBlock: dce_dc_dccg_dccg_dfs_dispdec |
| // base address: 0x0 |
| #define regDENTIST_DISPCLK_CNTL 0x0064 |
| #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: dce_dc_dccg_dccg_dispdec |
| // base address: 0x0 |
| #define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 |
| #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
| #define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 |
| #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
| #define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 |
| #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
| #define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 |
| #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
| #define regDP_DTO_DBUF_EN 0x0044 |
| #define regDP_DTO_DBUF_EN_BASE_IDX 1 |
| #define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 |
| #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regDCCG_GATE_DISABLE_CNTL4 0x0049 |
| #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 |
| #define regDPSTREAMCLK_CNTL 0x004a |
| #define regDPSTREAMCLK_CNTL_BASE_IDX 1 |
| #define regREFCLK_CGTT_BLK_CTRL_REG 0x004b |
| #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c |
| #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
| #define regDCCG_PERFMON_CNTL2 0x004e |
| #define regDCCG_PERFMON_CNTL2_BASE_IDX 1 |
| #define regDCCG_DS_DTO_INCR 0x0053 |
| #define regDCCG_DS_DTO_INCR_BASE_IDX 1 |
| #define regDCCG_DS_DTO_MODULO 0x0054 |
| #define regDCCG_DS_DTO_MODULO_BASE_IDX 1 |
| #define regDCCG_DS_CNTL 0x0055 |
| #define regDCCG_DS_CNTL_BASE_IDX 1 |
| #define regDCCG_DS_HW_CAL_INTERVAL 0x0056 |
| #define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 |
| #define regDPREFCLK_CNTL 0x0058 |
| #define regDPREFCLK_CNTL_BASE_IDX 1 |
| #define regDCE_VERSION 0x005e |
| #define regDCE_VERSION_BASE_IDX 1 |
| #define regDCCG_GTC_CNTL 0x0060 |
| #define regDCCG_GTC_CNTL_BASE_IDX 1 |
| #define regDCCG_GTC_DTO_INCR 0x0061 |
| #define regDCCG_GTC_DTO_INCR_BASE_IDX 1 |
| #define regDCCG_GTC_DTO_MODULO 0x0062 |
| #define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 |
| #define regDCCG_GTC_CURRENT 0x0063 |
| #define regDCCG_GTC_CURRENT_BASE_IDX 1 |
| #define regSYMCLK32_SE_CNTL 0x0065 |
| #define regSYMCLK32_SE_CNTL_BASE_IDX 1 |
| #define regSYMCLK32_LE_CNTL 0x0066 |
| #define regSYMCLK32_LE_CNTL_BASE_IDX 1 |
| #define regDSCCLK0_DTO_PARAM 0x006c |
| #define regDSCCLK0_DTO_PARAM_BASE_IDX 1 |
| #define regDSCCLK1_DTO_PARAM 0x006d |
| #define regDSCCLK1_DTO_PARAM_BASE_IDX 1 |
| #define regDSCCLK2_DTO_PARAM 0x006e |
| #define regDSCCLK2_DTO_PARAM_BASE_IDX 1 |
| #define regMILLISECOND_TIME_BASE_DIV 0x0070 |
| #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 |
| #define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 |
| #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 |
| #define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 |
| #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 |
| #define regDCCG_PERFMON_CNTL 0x0073 |
| #define regDCCG_PERFMON_CNTL_BASE_IDX 1 |
| #define regDCCG_GATE_DISABLE_CNTL 0x0074 |
| #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 |
| #define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 |
| #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 |
| #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regDCCG_CAC_STATUS 0x0077 |
| #define regDCCG_CAC_STATUS_BASE_IDX 1 |
| #define regMICROSECOND_TIME_BASE_DIV 0x007b |
| #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 |
| #define regDCCG_GATE_DISABLE_CNTL2 0x007c |
| #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 |
| #define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d |
| #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regDCCG_DISP_CNTL_REG 0x007f |
| #define regDCCG_DISP_CNTL_REG_BASE_IDX 1 |
| #define regOTG0_PIXEL_RATE_CNTL 0x0080 |
| #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regDP_DTO0_PHASE 0x0081 |
| #define regDP_DTO0_PHASE_BASE_IDX 1 |
| #define regDP_DTO0_MODULO 0x0082 |
| #define regDP_DTO0_MODULO_BASE_IDX 1 |
| #define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 |
| #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regOTG1_PIXEL_RATE_CNTL 0x0084 |
| #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regDP_DTO1_PHASE 0x0085 |
| #define regDP_DTO1_PHASE_BASE_IDX 1 |
| #define regDP_DTO1_MODULO 0x0086 |
| #define regDP_DTO1_MODULO_BASE_IDX 1 |
| #define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 |
| #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regOTG2_PIXEL_RATE_CNTL 0x0088 |
| #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regDP_DTO2_PHASE 0x0089 |
| #define regDP_DTO2_PHASE_BASE_IDX 1 |
| #define regDP_DTO2_MODULO 0x008a |
| #define regDP_DTO2_MODULO_BASE_IDX 1 |
| #define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b |
| #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regOTG3_PIXEL_RATE_CNTL 0x008c |
| #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regDP_DTO3_PHASE 0x008d |
| #define regDP_DTO3_PHASE_BASE_IDX 1 |
| #define regDP_DTO3_MODULO 0x008e |
| #define regDP_DTO3_MODULO_BASE_IDX 1 |
| #define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f |
| #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
| #define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 |
| #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
| #define regDPPCLK0_DTO_PARAM 0x0099 |
| #define regDPPCLK0_DTO_PARAM_BASE_IDX 1 |
| #define regDPPCLK1_DTO_PARAM 0x009a |
| #define regDPPCLK1_DTO_PARAM_BASE_IDX 1 |
| #define regDPPCLK2_DTO_PARAM 0x009b |
| #define regDPPCLK2_DTO_PARAM_BASE_IDX 1 |
| #define regDPPCLK3_DTO_PARAM 0x009c |
| #define regDPPCLK3_DTO_PARAM_BASE_IDX 1 |
| #define regDCCG_CAC_STATUS2 0x009f |
| #define regDCCG_CAC_STATUS2_BASE_IDX 1 |
| #define regSYMCLKA_CLOCK_ENABLE 0x00a0 |
| #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 |
| #define regSYMCLKB_CLOCK_ENABLE 0x00a1 |
| #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 |
| #define regSYMCLKC_CLOCK_ENABLE 0x00a2 |
| #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 |
| #define regSYMCLKD_CLOCK_ENABLE 0x00a3 |
| #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 |
| #define regSYMCLKE_CLOCK_ENABLE 0x00a4 |
| #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 |
| #define regDCCG_SOFT_RESET 0x00a6 |
| #define regDCCG_SOFT_RESET_BASE_IDX 1 |
| #define regDSCCLK_DTO_CTRL 0x00a7 |
| #define regDSCCLK_DTO_CTRL_BASE_IDX 1 |
| #define regDCCG_AUDIO_DTO_SOURCE 0x00ab |
| #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 |
| #define regDCCG_AUDIO_DTO0_PHASE 0x00ac |
| #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 |
| #define regDCCG_AUDIO_DTO0_MODULE 0x00ad |
| #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 |
| #define regDCCG_AUDIO_DTO1_PHASE 0x00ae |
| #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 |
| #define regDCCG_AUDIO_DTO1_MODULE 0x00af |
| #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 |
| #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 |
| #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 |
| #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 |
| #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 |
| #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 |
| #define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 |
| #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 |
| #define regDPPCLK_DTO_CTRL 0x00b6 |
| #define regDPPCLK_DTO_CTRL_BASE_IDX 1 |
| #define regDCCG_VSYNC_CNT_CTRL 0x00b8 |
| #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 |
| #define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 |
| #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 |
| #define regFORCE_SYMCLK_DISABLE 0x00ba |
| #define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 |
| #define regDTBCLK_DTO0_PHASE 0x0018 |
| #define regDTBCLK_DTO0_PHASE_BASE_IDX 2 |
| #define regDTBCLK_DTO1_PHASE 0x0019 |
| #define regDTBCLK_DTO1_PHASE_BASE_IDX 2 |
| #define regDTBCLK_DTO2_PHASE 0x001a |
| #define regDTBCLK_DTO2_PHASE_BASE_IDX 2 |
| #define regDTBCLK_DTO3_PHASE 0x001b |
| #define regDTBCLK_DTO3_PHASE_BASE_IDX 2 |
| #define regDTBCLK_DTO0_MODULO 0x001f |
| #define regDTBCLK_DTO0_MODULO_BASE_IDX 2 |
| #define regDTBCLK_DTO1_MODULO 0x0020 |
| #define regDTBCLK_DTO1_MODULO_BASE_IDX 2 |
| #define regDTBCLK_DTO2_MODULO 0x0021 |
| #define regDTBCLK_DTO2_MODULO_BASE_IDX 2 |
| #define regDTBCLK_DTO3_MODULO 0x0022 |
| #define regDTBCLK_DTO3_MODULO_BASE_IDX 2 |
| #define regPHYASYMCLK_CLOCK_CNTL 0x0052 |
| #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 |
| #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 |
| #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
| #define regPHYCSYMCLK_CLOCK_CNTL 0x0054 |
| #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
| #define regPHYDSYMCLK_CLOCK_CNTL 0x0055 |
| #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
| #define regPHYESYMCLK_CLOCK_CNTL 0x0056 |
| #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 |
| #define regDCCG_GATE_DISABLE_CNTL3 0x005a |
| #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 |
| #define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 |
| #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 |
| #define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 |
| #define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 |
| #define regDTBCLK_DTO_DBUF_EN 0x0063 |
| #define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec |
| // base address: 0x0 |
| #define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 |
| #define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 |
| #define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 |
| #define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_CNTL 0x0003 |
| #define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_CNTL2 0x0004 |
| #define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 |
| #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 |
| #define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_HI 0x0007 |
| #define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON0_PERFMON_LOW 0x0008 |
| #define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec |
| // base address: 0x30 |
| #define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c |
| #define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d |
| #define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e |
| #define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_CNTL 0x000f |
| #define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_CNTL2 0x0010 |
| #define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 |
| #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 |
| #define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_HI 0x0013 |
| #define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON1_PERFMON_LOW 0x0014 |
| #define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_dmcu_dispdec |
| // base address: 0x0 |
| #define regDMCU_CTRL 0x00da |
| #define regDMCU_CTRL_BASE_IDX 2 |
| #define regDMCU_STATUS 0x00db |
| #define regDMCU_STATUS_BASE_IDX 2 |
| #define regDMCU_PC_START_ADDR 0x00dc |
| #define regDMCU_PC_START_ADDR_BASE_IDX 2 |
| #define regDMCU_FW_START_ADDR 0x00dd |
| #define regDMCU_FW_START_ADDR_BASE_IDX 2 |
| #define regDMCU_FW_END_ADDR 0x00de |
| #define regDMCU_FW_END_ADDR_BASE_IDX 2 |
| #define regDMCU_FW_ISR_START_ADDR 0x00df |
| #define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 |
| #define regDMCU_FW_CS_HI 0x00e0 |
| #define regDMCU_FW_CS_HI_BASE_IDX 2 |
| #define regDMCU_FW_CS_LO 0x00e1 |
| #define regDMCU_FW_CS_LO_BASE_IDX 2 |
| #define regDMCU_RAM_ACCESS_CTRL 0x00e2 |
| #define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 |
| #define regDMCU_ERAM_WR_CTRL 0x00e3 |
| #define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 |
| #define regDMCU_ERAM_WR_DATA 0x00e4 |
| #define regDMCU_ERAM_WR_DATA_BASE_IDX 2 |
| #define regDMCU_ERAM_RD_CTRL 0x00e5 |
| #define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 |
| #define regDMCU_ERAM_RD_DATA 0x00e6 |
| #define regDMCU_ERAM_RD_DATA_BASE_IDX 2 |
| #define regDMCU_IRAM_WR_CTRL 0x00e7 |
| #define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 |
| #define regDMCU_IRAM_WR_DATA 0x00e8 |
| #define regDMCU_IRAM_WR_DATA_BASE_IDX 2 |
| #define regDMCU_IRAM_RD_CTRL 0x00e9 |
| #define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 |
| #define regDMCU_IRAM_RD_DATA 0x00ea |
| #define regDMCU_IRAM_RD_DATA_BASE_IDX 2 |
| #define regDMCU_EVENT_TRIGGER 0x00eb |
| #define regDMCU_EVENT_TRIGGER_BASE_IDX 2 |
| #define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec |
| #define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 |
| #define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed |
| #define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_STATUS 0x00ee |
| #define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_STATUS_1 0x00ef |
| #define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 |
| #define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 |
| #define regDC_DMCU_SCRATCH 0x00f5 |
| #define regDC_DMCU_SCRATCH_BASE_IDX 2 |
| #define regDMCU_INT_CNT 0x00f6 |
| #define regDMCU_INT_CNT_BASE_IDX 2 |
| #define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 |
| #define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 |
| #define regDMCU_UC_CLK_GATING_CNTL 0x00f8 |
| #define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 |
| #define regMASTER_COMM_DATA_REG1 0x00f9 |
| #define regMASTER_COMM_DATA_REG1_BASE_IDX 2 |
| #define regMASTER_COMM_DATA_REG2 0x00fa |
| #define regMASTER_COMM_DATA_REG2_BASE_IDX 2 |
| #define regMASTER_COMM_DATA_REG3 0x00fb |
| #define regMASTER_COMM_DATA_REG3_BASE_IDX 2 |
| #define regMASTER_COMM_CMD_REG 0x00fc |
| #define regMASTER_COMM_CMD_REG_BASE_IDX 2 |
| #define regMASTER_COMM_CNTL_REG 0x00fd |
| #define regMASTER_COMM_CNTL_REG_BASE_IDX 2 |
| #define regSLAVE_COMM_DATA_REG1 0x00fe |
| #define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 |
| #define regSLAVE_COMM_DATA_REG2 0x00ff |
| #define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 |
| #define regSLAVE_COMM_DATA_REG3 0x0100 |
| #define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 |
| #define regSLAVE_COMM_CMD_REG 0x0101 |
| #define regSLAVE_COMM_CMD_REG_BASE_IDX 2 |
| #define regSLAVE_COMM_CNTL_REG 0x0102 |
| #define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 |
| #define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 |
| #define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 |
| #define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 |
| #define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 |
| #define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 |
| #define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 |
| #define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 |
| #define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 |
| #define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 |
| #define regDMCU_INT_CNT_CONTINUE 0x011c |
| #define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d |
| #define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_STATUS_2 0x011e |
| #define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f |
| #define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 |
| #define regDMCU_INT_CNT_CONT2 0x0120 |
| #define regDMCU_INT_CNT_CONT2_BASE_IDX 2 |
| #define regDMCU_INT_CNT_CONT3 0x0121 |
| #define regDMCU_INT_CNT_CONT3_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_fgsec_dispdec |
| // base address: 0x0 |
| #define regDMCUB_RBBMIF_SEC_CNTL 0x017a |
| #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_rbbmif_dispdec |
| // base address: 0x0 |
| #define regRBBMIF_TIMEOUT 0x017f |
| #define regRBBMIF_TIMEOUT_BASE_IDX 2 |
| #define regRBBMIF_STATUS 0x0180 |
| #define regRBBMIF_STATUS_BASE_IDX 2 |
| #define regRBBMIF_STATUS_2 0x0181 |
| #define regRBBMIF_STATUS_2_BASE_IDX 2 |
| #define regRBBMIF_INT_STATUS 0x0182 |
| #define regRBBMIF_INT_STATUS_BASE_IDX 2 |
| #define regRBBMIF_TIMEOUT_DIS 0x0183 |
| #define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 |
| #define regRBBMIF_TIMEOUT_DIS_2 0x0184 |
| #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 |
| #define regRBBMIF_STATUS_FLAG 0x0185 |
| #define regRBBMIF_STATUS_FLAG_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x2f8 |
| #define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be |
| #define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf |
| #define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 |
| #define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_CNTL 0x00c1 |
| #define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 |
| #define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 |
| #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 |
| #define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_HI 0x00c5 |
| #define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON2_PERFMON_LOW 0x00c6 |
| #define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_ihc_dispdec |
| // base address: 0x0 |
| #define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 |
| #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 |
| #define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 |
| #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 |
| #define regDC_GPU_TIMER_READ 0x0128 |
| #define regDC_GPU_TIMER_READ_BASE_IDX 2 |
| #define regDC_GPU_TIMER_READ_CNTL 0x0129 |
| #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS 0x012a |
| #define regDISP_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b |
| #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c |
| #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d |
| #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e |
| #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f |
| #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a |
| #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b |
| #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c |
| #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d |
| #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e |
| #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f |
| #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 |
| #define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 |
| #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 |
| #define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 |
| #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 |
| #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 |
| #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 |
| #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 |
| #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 |
| #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 |
| #define regDCCG_INTERRUPT_DEST 0x0148 |
| #define regDCCG_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDMU_INTERRUPT_DEST 0x0149 |
| #define regDMU_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDMU_INTERRUPT_DEST2 0x014a |
| #define regDMU_INTERRUPT_DEST2_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_DEST 0x014b |
| #define regDCPG_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_DEST2 0x014c |
| #define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 |
| #define regMMHUBBUB_INTERRUPT_DEST 0x014d |
| #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 |
| #define regWB_INTERRUPT_DEST 0x014e |
| #define regWB_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDCHUB_INTERRUPT_DEST 0x014f |
| #define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 |
| #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDCHUB_INTERRUPT_DEST2 0x0151 |
| #define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 |
| #define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 |
| #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 |
| #define regMPC_INTERRUPT_DEST 0x0153 |
| #define regMPC_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOPP_INTERRUPT_DEST 0x0154 |
| #define regOPP_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOPTC_INTERRUPT_DEST 0x0155 |
| #define regOPTC_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG0_INTERRUPT_DEST 0x0156 |
| #define regOTG0_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG1_INTERRUPT_DEST 0x0157 |
| #define regOTG1_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG2_INTERRUPT_DEST 0x0158 |
| #define regOTG2_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG3_INTERRUPT_DEST 0x0159 |
| #define regOTG3_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG4_INTERRUPT_DEST 0x015a |
| #define regOTG4_INTERRUPT_DEST_BASE_IDX 2 |
| #define regOTG5_INTERRUPT_DEST 0x015b |
| #define regOTG5_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDIG_INTERRUPT_DEST 0x015c |
| #define regDIG_INTERRUPT_DEST_BASE_IDX 2 |
| #define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d |
| #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDIO_INTERRUPT_DEST 0x015f |
| #define regDIO_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDCIO_INTERRUPT_DEST 0x0160 |
| #define regDCIO_INTERRUPT_DEST_BASE_IDX 2 |
| #define regHPD_INTERRUPT_DEST 0x0161 |
| #define regHPD_INTERRUPT_DEST_BASE_IDX 2 |
| #define regAZ_INTERRUPT_DEST 0x0162 |
| #define regAZ_INTERRUPT_DEST_BASE_IDX 2 |
| #define regAUX_INTERRUPT_DEST 0x0163 |
| #define regAUX_INTERRUPT_DEST_BASE_IDX 2 |
| #define regDSC_INTERRUPT_DEST 0x0164 |
| #define regDSC_INTERRUPT_DEST_BASE_IDX 2 |
| #define regHPO_INTERRUPT_DEST 0x0165 |
| #define regHPO_INTERRUPT_DEST_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_dmu_misc_dispdec |
| // base address: 0x0 |
| #define regCC_DC_PIPE_DIS 0x00ca |
| #define regCC_DC_PIPE_DIS_BASE_IDX 2 |
| #define regDMU_CLK_CNTL 0x00cb |
| #define regDMU_CLK_CNTL_BASE_IDX 2 |
| #define regDMU_MEM_PWR_CNTL 0x00cc |
| #define regDMU_MEM_PWR_CNTL_BASE_IDX 2 |
| #define regDMCU_SMU_INTERRUPT_CNTL 0x00cd |
| #define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regSMU_INTERRUPT_CONTROL 0x00ce |
| #define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regZSC_CNTL 0x00cf |
| #define regZSC_CNTL_BASE_IDX 2 |
| #define regZSC_CNTL2 0x00d0 |
| #define regZSC_CNTL2_BASE_IDX 2 |
| #define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 |
| #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 |
| #define regZSC_STATUS 0x00d7 |
| #define regZSC_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_dc_pg_dispdec |
| // base address: 0x0 |
| #define regDOMAIN0_PG_CONFIG 0x0080 |
| #define regDOMAIN0_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN0_PG_STATUS 0x0081 |
| #define regDOMAIN0_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN1_PG_CONFIG 0x0082 |
| #define regDOMAIN1_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN1_PG_STATUS 0x0083 |
| #define regDOMAIN1_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN2_PG_CONFIG 0x0084 |
| #define regDOMAIN2_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN2_PG_STATUS 0x0085 |
| #define regDOMAIN2_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN3_PG_CONFIG 0x0086 |
| #define regDOMAIN3_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN3_PG_STATUS 0x0087 |
| #define regDOMAIN3_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN16_PG_CONFIG 0x0089 |
| #define regDOMAIN16_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN16_PG_STATUS 0x008a |
| #define regDOMAIN16_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN17_PG_CONFIG 0x008b |
| #define regDOMAIN17_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN17_PG_STATUS 0x008c |
| #define regDOMAIN17_PG_STATUS_BASE_IDX 2 |
| #define regDOMAIN18_PG_CONFIG 0x008d |
| #define regDOMAIN18_PG_CONFIG_BASE_IDX 2 |
| #define regDOMAIN18_PG_STATUS 0x008e |
| #define regDOMAIN18_PG_STATUS_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_STATUS 0x008f |
| #define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_STATUS_2 0x0090 |
| #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_CONTROL_1 0x0091 |
| #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 |
| #define regDCPG_INTERRUPT_CONTROL_3 0x0092 |
| #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 |
| #define regDC_IP_REQUEST_CNTL 0x0093 |
| #define regDC_IP_REQUEST_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dmu_dmcub_dispdec |
| // base address: 0x0 |
| #define regDMCUB_REGION0_OFFSET 0x018e |
| #define regDMCUB_REGION0_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION0_OFFSET_HIGH 0x018f |
| #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION1_OFFSET 0x0190 |
| #define regDMCUB_REGION1_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION1_OFFSET_HIGH 0x0191 |
| #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION2_OFFSET 0x0192 |
| #define regDMCUB_REGION2_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION2_OFFSET_HIGH 0x0193 |
| #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION4_OFFSET 0x0196 |
| #define regDMCUB_REGION4_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION4_OFFSET_HIGH 0x0197 |
| #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION5_OFFSET 0x0198 |
| #define regDMCUB_REGION5_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION5_OFFSET_HIGH 0x0199 |
| #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION6_OFFSET 0x019a |
| #define regDMCUB_REGION6_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION6_OFFSET_HIGH 0x019b |
| #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION7_OFFSET 0x019c |
| #define regDMCUB_REGION7_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION7_OFFSET_HIGH 0x019d |
| #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION0_TOP_ADDRESS 0x019e |
| #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION1_TOP_ADDRESS 0x019f |
| #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 |
| #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 |
| #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 |
| #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 |
| #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 |
| #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 |
| #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 |
| #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 |
| #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 |
| #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 |
| #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa |
| #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab |
| #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac |
| #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad |
| #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae |
| #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af |
| #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 |
| #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 |
| #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 |
| #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 |
| #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 |
| #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW0_OFFSET 0x01b5 |
| #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 |
| #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW1_OFFSET 0x01b7 |
| #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 |
| #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW2_OFFSET 0x01b9 |
| #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba |
| #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW3_OFFSET 0x01bb |
| #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc |
| #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW4_OFFSET 0x01bd |
| #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be |
| #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW5_OFFSET 0x01bf |
| #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 |
| #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW6_OFFSET 0x01c1 |
| #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 |
| #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW7_OFFSET 0x01c3 |
| #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 |
| #define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 |
| #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 |
| #define regDMCUB_INTERRUPT_ENABLE 0x01c5 |
| #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 |
| #define regDMCUB_INTERRUPT_ACK 0x01c6 |
| #define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 |
| #define regDMCUB_INTERRUPT_STATUS 0x01c7 |
| #define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regDMCUB_INTERRUPT_TYPE 0x01c8 |
| #define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 |
| #define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 |
| #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca |
| #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 |
| #define regDMCUB_EXT_INTERRUPT_ACK 0x01cb |
| #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 |
| #define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc |
| #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 |
| #define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd |
| #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 |
| #define regDMCUB_SEC_CNTL 0x01ce |
| #define regDMCUB_SEC_CNTL_BASE_IDX 2 |
| #define regDMCUB_MEM_CNTL 0x01cf |
| #define regDMCUB_MEM_CNTL_BASE_IDX 2 |
| #define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 |
| #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_INBOX0_SIZE 0x01d1 |
| #define regDMCUB_INBOX0_SIZE_BASE_IDX 2 |
| #define regDMCUB_INBOX0_WPTR 0x01d2 |
| #define regDMCUB_INBOX0_WPTR_BASE_IDX 2 |
| #define regDMCUB_INBOX0_RPTR 0x01d3 |
| #define regDMCUB_INBOX0_RPTR_BASE_IDX 2 |
| #define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 |
| #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_INBOX1_SIZE 0x01d5 |
| #define regDMCUB_INBOX1_SIZE_BASE_IDX 2 |
| #define regDMCUB_INBOX1_WPTR 0x01d6 |
| #define regDMCUB_INBOX1_WPTR_BASE_IDX 2 |
| #define regDMCUB_INBOX1_RPTR 0x01d7 |
| #define regDMCUB_INBOX1_RPTR_BASE_IDX 2 |
| #define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 |
| #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_OUTBOX0_SIZE 0x01d9 |
| #define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 |
| #define regDMCUB_OUTBOX0_WPTR 0x01da |
| #define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 |
| #define regDMCUB_OUTBOX0_RPTR 0x01db |
| #define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 |
| #define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc |
| #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 |
| #define regDMCUB_OUTBOX1_SIZE 0x01dd |
| #define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 |
| #define regDMCUB_OUTBOX1_WPTR 0x01de |
| #define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 |
| #define regDMCUB_OUTBOX1_RPTR 0x01df |
| #define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 |
| #define regDMCUB_TIMER_TRIGGER0 0x01e0 |
| #define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 |
| #define regDMCUB_TIMER_TRIGGER1 0x01e1 |
| #define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 |
| #define regDMCUB_TIMER_WINDOW 0x01e2 |
| #define regDMCUB_TIMER_WINDOW_BASE_IDX 2 |
| #define regDMCUB_SCRATCH0 0x01e3 |
| #define regDMCUB_SCRATCH0_BASE_IDX 2 |
| #define regDMCUB_SCRATCH1 0x01e4 |
| #define regDMCUB_SCRATCH1_BASE_IDX 2 |
| #define regDMCUB_SCRATCH2 0x01e5 |
| #define regDMCUB_SCRATCH2_BASE_IDX 2 |
| #define regDMCUB_SCRATCH3 0x01e6 |
| #define regDMCUB_SCRATCH3_BASE_IDX 2 |
| #define regDMCUB_SCRATCH4 0x01e7 |
| #define regDMCUB_SCRATCH4_BASE_IDX 2 |
| #define regDMCUB_SCRATCH5 0x01e8 |
| #define regDMCUB_SCRATCH5_BASE_IDX 2 |
| #define regDMCUB_SCRATCH6 0x01e9 |
| #define regDMCUB_SCRATCH6_BASE_IDX 2 |
| #define regDMCUB_SCRATCH7 0x01ea |
| #define regDMCUB_SCRATCH7_BASE_IDX 2 |
| #define regDMCUB_SCRATCH8 0x01eb |
| #define regDMCUB_SCRATCH8_BASE_IDX 2 |
| #define regDMCUB_SCRATCH9 0x01ec |
| #define regDMCUB_SCRATCH9_BASE_IDX 2 |
| #define regDMCUB_SCRATCH10 0x01ed |
| #define regDMCUB_SCRATCH10_BASE_IDX 2 |
| #define regDMCUB_SCRATCH11 0x01ee |
| #define regDMCUB_SCRATCH11_BASE_IDX 2 |
| #define regDMCUB_SCRATCH12 0x01ef |
| #define regDMCUB_SCRATCH12_BASE_IDX 2 |
| #define regDMCUB_SCRATCH13 0x01f0 |
| #define regDMCUB_SCRATCH13_BASE_IDX 2 |
| #define regDMCUB_SCRATCH14 0x01f1 |
| #define regDMCUB_SCRATCH14_BASE_IDX 2 |
| #define regDMCUB_SCRATCH15 0x01f2 |
| #define regDMCUB_SCRATCH15_BASE_IDX 2 |
| #define regDMCUB_CNTL 0x01f6 |
| #define regDMCUB_CNTL_BASE_IDX 2 |
| #define regDMCUB_GPINT_DATAIN0 0x01f7 |
| #define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 |
| #define regDMCUB_GPINT_DATAIN1 0x01f8 |
| #define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 |
| #define regDMCUB_GPINT_DATAOUT 0x01f9 |
| #define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 |
| #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa |
| #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 |
| #define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb |
| #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 |
| #define regDMCUB_MEM_PWR_CNTL 0x01fc |
| #define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 |
| #define regDMCUB_TIMER_CURRENT 0x01fd |
| #define regDMCUB_TIMER_CURRENT_BASE_IDX 2 |
| #define regDMCUB_PROC_ID 0x01ff |
| #define regDMCUB_PROC_ID_BASE_IDX 2 |
| #define regDMCUB_CNTL2 0x0200 |
| #define regDMCUB_CNTL2_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec |
| // base address: 0x0 |
| #define regDWB_ENABLE_CLK_CTRL 0x3228 |
| #define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 |
| #define regDWB_MEM_PWR_CTRL 0x3229 |
| #define regDWB_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regFC_MODE_CTRL 0x322a |
| #define regFC_MODE_CTRL_BASE_IDX 2 |
| #define regFC_FLOW_CTRL 0x322b |
| #define regFC_FLOW_CTRL_BASE_IDX 2 |
| #define regFC_WINDOW_START 0x322c |
| #define regFC_WINDOW_START_BASE_IDX 2 |
| #define regFC_WINDOW_SIZE 0x322d |
| #define regFC_WINDOW_SIZE_BASE_IDX 2 |
| #define regFC_SOURCE_SIZE 0x322e |
| #define regFC_SOURCE_SIZE_BASE_IDX 2 |
| #define regDWB_UPDATE_CTRL 0x322f |
| #define regDWB_UPDATE_CTRL_BASE_IDX 2 |
| #define regDWB_CRC_CTRL 0x3230 |
| #define regDWB_CRC_CTRL_BASE_IDX 2 |
| #define regDWB_CRC_MASK_R_G 0x3231 |
| #define regDWB_CRC_MASK_R_G_BASE_IDX 2 |
| #define regDWB_CRC_MASK_B_A 0x3232 |
| #define regDWB_CRC_MASK_B_A_BASE_IDX 2 |
| #define regDWB_CRC_VAL_R_G 0x3233 |
| #define regDWB_CRC_VAL_R_G_BASE_IDX 2 |
| #define regDWB_CRC_VAL_B_A 0x3234 |
| #define regDWB_CRC_VAL_B_A_BASE_IDX 2 |
| #define regDWB_OUT_CTRL 0x3235 |
| #define regDWB_OUT_CTRL_BASE_IDX 2 |
| #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 |
| #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 |
| #define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 |
| #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 |
| #define regDWB_HOST_READ_CONTROL 0x3238 |
| #define regDWB_HOST_READ_CONTROL_BASE_IDX 2 |
| #define regDWB_OVERFLOW_STATUS 0x3239 |
| #define regDWB_OVERFLOW_STATUS_BASE_IDX 2 |
| #define regDWB_OVERFLOW_COUNTER 0x323a |
| #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 |
| #define regDWB_SOFT_RESET 0x323b |
| #define regDWB_SOFT_RESET_BASE_IDX 2 |
| #define regDWB_DEBUG_CTRL 0x323c |
| #define regDWB_DEBUG_CTRL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec |
| // base address: 0x0 |
| #define regDWB_HDR_MULT_COEF 0x3294 |
| #define regDWB_HDR_MULT_COEF_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAP_MODE 0x3295 |
| #define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 |
| #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C11_C12 0x3297 |
| #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C13_C14 0x3298 |
| #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C21_C22 0x3299 |
| #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C23_C24 0x329a |
| #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C31_C32 0x329b |
| #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPA_C33_C34 0x329c |
| #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C11_C12 0x329d |
| #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C13_C14 0x329e |
| #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C21_C22 0x329f |
| #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 |
| #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 |
| #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 |
| #define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 |
| #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 |
| #define regDWB_OGAM_CONTROL 0x32a3 |
| #define regDWB_OGAM_CONTROL_BASE_IDX 2 |
| #define regDWB_OGAM_LUT_INDEX 0x32a4 |
| #define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 |
| #define regDWB_OGAM_LUT_DATA 0x32a5 |
| #define regDWB_OGAM_LUT_DATA_BASE_IDX 2 |
| #define regDWB_OGAM_LUT_CONTROL 0x32a6 |
| #define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 |
| #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 |
| #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 |
| #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae |
| #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af |
| #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 |
| #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 |
| #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 |
| #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 |
| #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 |
| #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 |
| #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 |
| #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 |
| #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 |
| #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 |
| #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_2_3 0x32ba |
| #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_4_5 0x32bb |
| #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_6_7 0x32bc |
| #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_8_9 0x32bd |
| #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_10_11 0x32be |
| #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_12_13 0x32bf |
| #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 |
| #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 |
| #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 |
| #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 |
| #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 |
| #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 |
| #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 |
| #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 |
| #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 |
| #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 |
| #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca |
| #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb |
| #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc |
| #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 |
| #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 |
| #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 |
| #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 |
| #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 |
| #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 |
| #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 |
| #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 |
| #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 |
| #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_OFFSET_G 0x32da |
| #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_OFFSET_R 0x32db |
| #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_0_1 0x32dc |
| #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_2_3 0x32dd |
| #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_4_5 0x32de |
| #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_6_7 0x32df |
| #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 |
| #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 |
| #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 |
| #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 |
| #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 |
| #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 |
| #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 |
| #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 |
| #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 |
| #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 |
| #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_28_29 0x32ea |
| #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_30_31 0x32eb |
| #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regDWB_OGAM_RAMB_REGION_32_33 0x32ec |
| #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xca20 |
| #define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 |
| #define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 |
| #define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a |
| #define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_CNTL 0x328b |
| #define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_CNTL2 0x328c |
| #define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d |
| #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e |
| #define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_HI 0x328f |
| #define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON3_PERFMON_LOW 0x3290 |
| #define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_vga_dispdec |
| // base address: 0x0 |
| #define regVGA_RENDER_CONTROL 0x0000 |
| #define regVGA_RENDER_CONTROL_BASE_IDX 1 |
| #define regVGA_SEQUENCER_RESET_CONTROL 0x0001 |
| #define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 |
| #define regVGA_MODE_CONTROL 0x0002 |
| #define regVGA_MODE_CONTROL_BASE_IDX 1 |
| #define regVGA_SURFACE_PITCH_SELECT 0x0003 |
| #define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 |
| #define regVGA_MEMORY_BASE_ADDRESS 0x0004 |
| #define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 |
| #define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 |
| #define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 |
| #define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 |
| #define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 |
| #define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 |
| #define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 |
| #define regVGA_HDP_CONTROL 0x000a |
| #define regVGA_HDP_CONTROL_BASE_IDX 1 |
| #define regVGA_CACHE_CONTROL 0x000b |
| #define regVGA_CACHE_CONTROL_BASE_IDX 1 |
| #define regD1VGA_CONTROL 0x000c |
| #define regD1VGA_CONTROL_BASE_IDX 1 |
| #define regD2VGA_CONTROL 0x000e |
| #define regD2VGA_CONTROL_BASE_IDX 1 |
| #define regVGA_STATUS 0x0010 |
| #define regVGA_STATUS_BASE_IDX 1 |
| #define regVGA_INTERRUPT_CONTROL 0x0011 |
| #define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 |
| #define regVGA_STATUS_CLEAR 0x0012 |
| #define regVGA_STATUS_CLEAR_BASE_IDX 1 |
| #define regVGA_INTERRUPT_STATUS 0x0013 |
| #define regVGA_INTERRUPT_STATUS_BASE_IDX 1 |
| #define regVGA_MAIN_CONTROL 0x0014 |
| #define regVGA_MAIN_CONTROL_BASE_IDX 1 |
| #define regVGA_TEST_CONTROL 0x0015 |
| #define regVGA_TEST_CONTROL_BASE_IDX 1 |
| #define regVGA_QOS_CTRL 0x0018 |
| #define regVGA_QOS_CTRL_BASE_IDX 1 |
| #define regD3VGA_CONTROL 0x0038 |
| #define regD3VGA_CONTROL_BASE_IDX 1 |
| #define regD4VGA_CONTROL 0x0039 |
| #define regD4VGA_CONTROL_BASE_IDX 1 |
| #define regD5VGA_CONTROL 0x003a |
| #define regD5VGA_CONTROL_BASE_IDX 1 |
| #define regD6VGA_CONTROL 0x003b |
| #define regD6VGA_CONTROL_BASE_IDX 1 |
| #define regVGA_SOURCE_SELECT 0x003c |
| #define regVGA_SOURCE_SELECT_BASE_IDX 1 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_vgaif_dispdec |
| // base address: 0x0 |
| #define regMCIF_CONTROL 0x034a |
| #define regMCIF_CONTROL_BASE_IDX 2 |
| #define regMCIF_WRITE_COMBINE_CONTROL 0x034b |
| #define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 |
| #define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e |
| #define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 |
| #define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f |
| #define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 |
| #define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 |
| #define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec |
| // base address: 0x0 |
| #define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 |
| #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_BUFMGR_STATUS 0x0274 |
| #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 |
| #define regMCIF_WB_BUF_PITCH 0x0275 |
| #define regMCIF_WB_BUF_PITCH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_STATUS 0x0276 |
| #define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_STATUS2 0x0277 |
| #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_STATUS 0x0278 |
| #define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_STATUS2 0x0279 |
| #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_STATUS 0x027a |
| #define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_STATUS2 0x027b |
| #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_STATUS 0x027c |
| #define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_STATUS2 0x027d |
| #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 |
| #define regMCIF_WB_ARBITRATION_CONTROL 0x027e |
| #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_SCLK_CHANGE 0x027f |
| #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 |
| #define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 |
| #define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regMCIF_WB_TEST_DEBUG_DATA 0x0281 |
| #define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 |
| #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_ADDR_C 0x0284 |
| #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_ADDR_Y 0x0286 |
| #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_ADDR_C 0x0288 |
| #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_ADDR_Y 0x028a |
| #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_ADDR_C 0x028c |
| #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_ADDR_Y 0x028e |
| #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_ADDR_C 0x0290 |
| #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 |
| #define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 |
| #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 |
| #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 |
| #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 |
| #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 |
| #define regMULTI_LEVEL_QOS_CTRL 0x0297 |
| #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 |
| #define regMCIF_WB_BUF_LUMA_SIZE 0x0299 |
| #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 |
| #define regMCIF_WB_BUF_CHROMA_SIZE 0x029a |
| #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b |
| #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c |
| #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d |
| #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e |
| #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f |
| #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 |
| #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 |
| #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 |
| #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 |
| #define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 |
| #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 |
| #define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 |
| #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 |
| #define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 |
| #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 |
| #define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 |
| #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 |
| #define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 |
| #define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 |
| #define regMCIF_WB_VMID_CONTROL 0x02a8 |
| #define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 |
| #define regMCIF_WB_MIN_TTO 0x02a9 |
| #define regMCIF_WB_MIN_TTO_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xd48 |
| #define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 |
| #define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 |
| #define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 |
| #define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_CNTL 0x0355 |
| #define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_CNTL2 0x0356 |
| #define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 |
| #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 |
| #define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_HI 0x0359 |
| #define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON4_PERFMON_LOW 0x035a |
| #define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec |
| // base address: 0x0 |
| #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa |
| #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 |
| #define regMCIF_WB_WATERMARK 0x02ab |
| #define regMCIF_WB_WATERMARK_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_CONFIG 0x02ac |
| #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad |
| #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae |
| #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af |
| #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 |
| #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 |
| #define regMMHUBBUB_MIN_TTO 0x02b1 |
| #define regMMHUBBUB_MIN_TTO_BASE_IDX 2 |
| #define regMMHUBBUB_CTRL 0x0333 |
| #define regMMHUBBUB_CTRL_BASE_IDX 2 |
| #define regWBIF_SMU_WM_CONTROL 0x0334 |
| #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 |
| #define regWBIF0_MISC_CTRL 0x0335 |
| #define regWBIF0_MISC_CTRL_BASE_IDX 2 |
| #define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 |
| #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 |
| #define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 |
| #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 |
| #define regVGA_SRC_SPLIT_CNTL 0x033e |
| #define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 |
| #define regMMHUBBUB_MEM_PWR_STATUS 0x033f |
| #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regMMHUBBUB_MEM_PWR_CNTL 0x0340 |
| #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 |
| #define regMMHUBBUB_CLOCK_CNTL 0x0341 |
| #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 |
| #define regMMHUBBUB_SOFT_RESET 0x0342 |
| #define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 |
| #define regDMU_IF_ERR_STATUS 0x0346 |
| #define regDMU_IF_ERR_STATUS_BASE_IDX 2 |
| #define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 |
| #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 |
| #define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 |
| #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0controller_dispdec |
| // base address: 0x0 |
| #define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 |
| #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 |
| #define regAZALIA_AUDIO_DTO 0x03c3 |
| #define regAZALIA_AUDIO_DTO_BASE_IDX 2 |
| #define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 |
| #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 |
| #define regAZALIA_SOCCLK_CONTROL 0x03c5 |
| #define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 |
| #define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 |
| #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 |
| #define regAZALIA_DATA_DMA_CONTROL 0x03c7 |
| #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 |
| #define regAZALIA_BDL_DMA_CONTROL 0x03c8 |
| #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 |
| #define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 |
| #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 |
| #define regAZALIA_CORB_DMA_CONTROL 0x03ca |
| #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 |
| #define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 |
| #define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 |
| #define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 |
| #define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 |
| #define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 |
| #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 |
| #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 |
| #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 |
| #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 |
| #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 |
| #define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 |
| #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 |
| #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC0_CONTROL1 0x03da |
| #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC0_CONTROL2 0x03db |
| #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc |
| #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC0_RESULT 0x03dd |
| #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC1_CONTROL0 0x03de |
| #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC1_CONTROL1 0x03df |
| #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 |
| #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 |
| #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 |
| #define regAZALIA_INPUT_CRC1_RESULT 0x03e2 |
| #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 |
| #define regAZALIA_CRC0_CONTROL0 0x03e3 |
| #define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 |
| #define regAZALIA_CRC0_CONTROL1 0x03e4 |
| #define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 |
| #define regAZALIA_CRC0_CONTROL2 0x03e5 |
| #define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 |
| #define regAZALIA_CRC0_CONTROL3 0x03e6 |
| #define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 |
| #define regAZALIA_CRC0_RESULT 0x03e7 |
| #define regAZALIA_CRC0_RESULT_BASE_IDX 2 |
| #define regAZALIA_CRC1_CONTROL0 0x03e8 |
| #define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 |
| #define regAZALIA_CRC1_CONTROL1 0x03e9 |
| #define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 |
| #define regAZALIA_CRC1_CONTROL2 0x03ea |
| #define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 |
| #define regAZALIA_CRC1_CONTROL3 0x03eb |
| #define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 |
| #define regAZALIA_CRC1_RESULT 0x03ec |
| #define regAZALIA_CRC1_RESULT_BASE_IDX 2 |
| #define regAZALIA_MEM_PWR_CTRL 0x03ee |
| #define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regAZALIA_MEM_PWR_STATUS 0x03ef |
| #define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0root_dispdec |
| // base address: 0x0 |
| #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 |
| #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 |
| #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 |
| #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 |
| #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d |
| #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 |
| #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 |
| #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 |
| #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 |
| #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 |
| #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a |
| #define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 |
| #define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b |
| #define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 |
| #define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c |
| #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 |
| #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d |
| #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_az_misc_dispdec |
| // base address: 0x0 |
| #define regAZ_CLOCK_CNTL 0x0372 |
| #define regAZ_CLOCK_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xde8 |
| #define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a |
| #define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b |
| #define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c |
| #define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_CNTL 0x037d |
| #define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_CNTL2 0x037e |
| #define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f |
| #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 |
| #define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_HI 0x0381 |
| #define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON5_PERFMON_LOW 0x0382 |
| #define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream0_dispdec |
| // base address: 0x0 |
| #define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e |
| #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f |
| #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream1_dispdec |
| // base address: 0x8 |
| #define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 |
| #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 |
| #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream2_dispdec |
| // base address: 0x10 |
| #define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 |
| #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 |
| #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream3_dispdec |
| // base address: 0x18 |
| #define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 |
| #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 |
| #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream4_dispdec |
| // base address: 0x20 |
| #define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 |
| #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 |
| #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream5_dispdec |
| // base address: 0x28 |
| #define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 |
| #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 |
| #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream6_dispdec |
| // base address: 0x30 |
| #define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a |
| #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b |
| #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream7_dispdec |
| // base address: 0x38 |
| #define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c |
| #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d |
| #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream8_dispdec |
| // base address: 0x320 |
| #define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 |
| #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 |
| #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream9_dispdec |
| // base address: 0x328 |
| #define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 |
| #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 |
| #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream10_dispdec |
| // base address: 0x330 |
| #define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a |
| #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b |
| #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream11_dispdec |
| // base address: 0x338 |
| #define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c |
| #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d |
| #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream12_dispdec |
| // base address: 0x340 |
| #define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e |
| #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f |
| #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream13_dispdec |
| // base address: 0x348 |
| #define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 |
| #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 |
| #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream14_dispdec |
| // base address: 0x350 |
| #define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 |
| #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 |
| #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0stream15_dispdec |
| // base address: 0x358 |
| #define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 |
| #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 |
| #define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 |
| #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint0_dispdec |
| // base address: 0x0 |
| #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 |
| #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 |
| #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint1_dispdec |
| // base address: 0x18 |
| #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c |
| #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d |
| #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint2_dispdec |
| // base address: 0x30 |
| #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 |
| #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 |
| #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint3_dispdec |
| // base address: 0x48 |
| #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 |
| #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 |
| #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint4_dispdec |
| // base address: 0x60 |
| #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e |
| #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f |
| #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint5_dispdec |
| // base address: 0x78 |
| #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 |
| #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 |
| #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint6_dispdec |
| // base address: 0x90 |
| #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa |
| #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab |
| #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0endpoint7_dispdec |
| // base address: 0xa8 |
| #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 |
| #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 |
| #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec |
| // base address: 0x0 |
| #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a |
| #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b |
| #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec |
| // base address: 0x10 |
| #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e |
| #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f |
| #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec |
| // base address: 0x20 |
| #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 |
| #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 |
| #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec |
| // base address: 0x30 |
| #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 |
| #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 |
| #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec |
| // base address: 0x40 |
| #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a |
| #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b |
| #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec |
| // base address: 0x50 |
| #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e |
| #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f |
| #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec |
| // base address: 0x60 |
| #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 |
| #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 |
| #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec |
| // base address: 0x70 |
| #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 |
| #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
| #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 |
| #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchubbubl_hubbub_dispdec |
| // base address: 0x0 |
| #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 |
| #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa |
| #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_QOS_FORCE 0x04fb |
| #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc |
| #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 |
| #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 |
| #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b |
| #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d |
| #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e |
| #define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 |
| #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 |
| #define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 |
| #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 |
| #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 |
| #define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 |
| #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 |
| #define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 |
| #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 |
| #define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 |
| #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 |
| #define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 |
| #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 |
| #define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 |
| #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 |
| #define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 |
| #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 |
| #define regSURFACE_CHECK2_ADDRESS_MSB 0x052a |
| #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 |
| #define regSURFACE_CHECK3_ADDRESS_LSB 0x052b |
| #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 |
| #define regSURFACE_CHECK3_ADDRESS_MSB 0x052c |
| #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 |
| #define regVTG0_CONTROL 0x052d |
| #define regVTG0_CONTROL_BASE_IDX 2 |
| #define regVTG1_CONTROL 0x052e |
| #define regVTG1_CONTROL_BASE_IDX 2 |
| #define regVTG2_CONTROL 0x052f |
| #define regVTG2_CONTROL_BASE_IDX 2 |
| #define regVTG3_CONTROL 0x0530 |
| #define regVTG3_CONTROL_BASE_IDX 2 |
| #define regDCHUBBUB_SOFT_RESET 0x0531 |
| #define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 |
| #define regDCHUBBUB_CLOCK_CNTL 0x0532 |
| #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 |
| #define regDCFCLK_CNTL 0x0533 |
| #define regDCFCLK_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 |
| #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 |
| #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 |
| #define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 |
| #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 |
| #define regDCHUBBUB_CTRL_STATUS 0x0537 |
| #define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 |
| #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d |
| #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 |
| #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e |
| #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 |
| #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f |
| #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regFMON_CTRL 0x0540 |
| #define regFMON_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 |
| #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 |
| #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec |
| // base address: 0x0 |
| #define regDCHUBBUB_SDPIF_CFG0 0x046f |
| #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 |
| #define regDCHUBBUB_SDPIF_CFG1 0x0470 |
| #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 |
| #define regDCHUBBUB_SDPIF_CFG2 0x0471 |
| #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 |
| #define regVM_REQUEST_PHYSICAL 0x0472 |
| #define regVM_REQUEST_PHYSICAL_BASE_IDX 2 |
| #define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 |
| #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 |
| #define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 |
| #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 |
| #define regDCN_VM_FB_LOCATION_BASE 0x0475 |
| #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 |
| #define regDCN_VM_FB_LOCATION_TOP 0x0476 |
| #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 |
| #define regDCN_VM_FB_OFFSET 0x0477 |
| #define regDCN_VM_FB_OFFSET_BASE_IDX 2 |
| #define regDCN_VM_AGP_BOT 0x0478 |
| #define regDCN_VM_AGP_BOT_BASE_IDX 2 |
| #define regDCN_VM_AGP_TOP 0x0479 |
| #define regDCN_VM_AGP_TOP_BASE_IDX 2 |
| #define regDCN_VM_AGP_BASE 0x047a |
| #define regDCN_VM_AGP_BASE_BASE_IDX 2 |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d |
| #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 |
| #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 |
| #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec |
| // base address: 0x0 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af |
| #define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba |
| #define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb |
| #define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc |
| #define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd |
| #define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be |
| #define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf |
| #define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 |
| #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 |
| #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDCHUBBUB_CRC_CTRL 0x04c2 |
| #define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 |
| #define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 |
| #define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 |
| #define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 |
| #define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 |
| #define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 |
| #define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 |
| #define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 |
| #define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 |
| #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 |
| #define regDCHUBBUB_DCC_STAT0 0x04c8 |
| #define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 |
| #define regDCHUBBUB_DCC_STAT1 0x04c9 |
| #define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 |
| #define regDCHUBBUB_DCC_STAT2 0x04ca |
| #define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 |
| #define regDCHUBBUB_COMPBUF_CTRL 0x04cb |
| #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_DET0_CTRL 0x04cc |
| #define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_DET1_CTRL 0x04cd |
| #define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_DET2_CTRL 0x04ce |
| #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_DET3_CTRL 0x04cf |
| #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 |
| #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 |
| #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 |
| #define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 |
| #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 |
| #define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 |
| #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 |
| #define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 |
| #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCOMPBUF_RESERVED_SPACE 0x04d5 |
| #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec |
| // base address: 0x0 |
| #define regDCN_VM_CONTEXT0_CNTL 0x0559 |
| #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f |
| #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_CNTL 0x0560 |
| #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 |
| #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_CNTL 0x0567 |
| #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d |
| #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_CNTL 0x056e |
| #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 |
| #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_CNTL 0x0575 |
| #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b |
| #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_CNTL 0x057c |
| #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 |
| #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_CNTL 0x0583 |
| #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 |
| #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_CNTL 0x058a |
| #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 |
| #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_CNTL 0x0591 |
| #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 |
| #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_CNTL 0x0598 |
| #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e |
| #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_CNTL 0x059f |
| #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 |
| #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_CNTL 0x05a6 |
| #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac |
| #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_CNTL 0x05ad |
| #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 |
| #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_CNTL 0x05b4 |
| #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba |
| #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_CNTL 0x05bb |
| #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 |
| #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_CNTL 0x05c2 |
| #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 |
| #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
| #define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 |
| #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 |
| #define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca |
| #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 |
| #define regDCN_VM_FAULT_CNTL 0x05cb |
| #define regDCN_VM_FAULT_CNTL_BASE_IDX 2 |
| #define regDCN_VM_FAULT_STATUS 0x05cc |
| #define regDCN_VM_FAULT_STATUS_BASE_IDX 2 |
| #define regDCN_VM_FAULT_ADDR_MSB 0x05cd |
| #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 |
| #define regDCN_VM_FAULT_ADDR_LSB 0x05ce |
| #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x1534 |
| #define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d |
| #define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e |
| #define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f |
| #define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_CNTL 0x0550 |
| #define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_CNTL2 0x0551 |
| #define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 |
| #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 |
| #define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_HI 0x0554 |
| #define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON6_PERFMON_LOW 0x0555 |
| #define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec |
| // base address: 0x0 |
| #define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 |
| #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
| #define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 |
| #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
| #define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 |
| #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec |
| #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 |
| #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 |
| #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
| #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 |
| #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
| #define regHUBP0_DCHUBP_CNTL 0x05f3 |
| #define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 |
| #define regHUBP0_HUBP_CLK_CNTL 0x05f4 |
| #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 |
| #define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 |
| #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
| #define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 |
| #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
| #define regHUBP0_HUBPREQ_DEBUG 0x05f7 |
| #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 |
| #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb |
| #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
| #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc |
| #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec |
| // base address: 0x0 |
| #define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 |
| #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 |
| #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
| #define regHUBPREQ0_VMID_SETTINGS_0 0x0609 |
| #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d |
| #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 |
| #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 |
| #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 |
| #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a |
| #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b |
| #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c |
| #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 |
| #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 |
| #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 |
| #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 |
| #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a |
| #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b |
| #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c |
| #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d |
| #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e |
| #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f |
| #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 |
| #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 |
| #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 |
| #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 |
| #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 |
| #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 |
| #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 |
| #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
| #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 |
| #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
| #define regHUBPREQ0_BLANK_OFFSET_0 0x0644 |
| #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 |
| #define regHUBPREQ0_BLANK_OFFSET_1 0x0645 |
| #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 |
| #define regHUBPREQ0_DST_DIMENSIONS 0x0646 |
| #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 |
| #define regHUBPREQ0_DST_AFTER_SCALER 0x0647 |
| #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 |
| #define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 |
| #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 |
| #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a |
| #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b |
| #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c |
| #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d |
| #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e |
| #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f |
| #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 |
| #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 |
| #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 |
| #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 |
| #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 |
| #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 |
| #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 |
| #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 |
| #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 |
| #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 |
| #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 |
| #define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a |
| #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
| #define regHUBPREQ0_PER_LINE_DELIVERY 0x065b |
| #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 |
| #define regHUBPREQ0_CURSOR_SETTINGS 0x065c |
| #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d |
| #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
| #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e |
| #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
| #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f |
| #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 |
| #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 |
| #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 |
| #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 |
| #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 |
| #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 |
| #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec |
| // base address: 0x0 |
| #define regHUBPRET0_HUBPRET_CONTROL 0x066c |
| #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d |
| #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e |
| #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f |
| #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 |
| #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 |
| #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 |
| #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 |
| #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 |
| #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
| #define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 |
| #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec |
| // base address: 0x0 |
| #define regCURSOR0_0_CURSOR_CONTROL 0x0678 |
| #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 |
| #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a |
| #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_SIZE 0x067b |
| #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_POSITION 0x067c |
| #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d |
| #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e |
| #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f |
| #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 |
| #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 |
| #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 |
| #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 |
| #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_CNTL 0x0684 |
| #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 |
| #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_STATUS 0x0686 |
| #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 |
| #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 |
| #define regCURSOR0_0_DMDATA_SW_DATA 0x0688 |
| #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x1a74 |
| #define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d |
| #define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e |
| #define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f |
| #define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_CNTL 0x06a0 |
| #define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 |
| #define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 |
| #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 |
| #define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_HI 0x06a4 |
| #define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON7_PERFMON_LOW 0x06a5 |
| #define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec |
| // base address: 0x370 |
| #define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 |
| #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
| #define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 |
| #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
| #define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 |
| #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 |
| #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc |
| #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd |
| #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
| #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce |
| #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
| #define regHUBP1_DCHUBP_CNTL 0x06cf |
| #define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 |
| #define regHUBP1_HUBP_CLK_CNTL 0x06d0 |
| #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 |
| #define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 |
| #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
| #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 |
| #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
| #define regHUBP1_HUBPREQ_DEBUG 0x06d3 |
| #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 |
| #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 |
| #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
| #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 |
| #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec |
| // base address: 0x370 |
| #define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 |
| #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 |
| #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
| #define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 |
| #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 |
| #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed |
| #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 |
| #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 |
| #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 |
| #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 |
| #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 |
| #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc |
| #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 |
| #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 |
| #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 |
| #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 |
| #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 |
| #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 |
| #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 |
| #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a |
| #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b |
| #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c |
| #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d |
| #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e |
| #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f |
| #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 |
| #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 |
| #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 |
| #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
| #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f |
| #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
| #define regHUBPREQ1_BLANK_OFFSET_0 0x0720 |
| #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 |
| #define regHUBPREQ1_BLANK_OFFSET_1 0x0721 |
| #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 |
| #define regHUBPREQ1_DST_DIMENSIONS 0x0722 |
| #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 |
| #define regHUBPREQ1_DST_AFTER_SCALER 0x0723 |
| #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 |
| #define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 |
| #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 |
| #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a |
| #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b |
| #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c |
| #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d |
| #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_0 0x072e |
| #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_1 0x072f |
| #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 |
| #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 |
| #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 |
| #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 |
| #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 |
| #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 |
| #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 |
| #define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 |
| #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
| #define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 |
| #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 |
| #define regHUBPREQ1_CURSOR_SETTINGS 0x0738 |
| #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 |
| #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
| #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a |
| #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
| #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b |
| #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c |
| #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f |
| #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 |
| #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 |
| #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 |
| #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 |
| #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 |
| #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec |
| // base address: 0x370 |
| #define regHUBPRET1_HUBPRET_CONTROL 0x0748 |
| #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 |
| #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a |
| #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b |
| #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c |
| #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE0 0x074d |
| #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE1 0x074e |
| #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_INTERRUPT 0x074f |
| #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 |
| #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
| #define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 |
| #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec |
| // base address: 0x370 |
| #define regCURSOR0_1_CURSOR_CONTROL 0x0754 |
| #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 |
| #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 |
| #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_SIZE 0x0757 |
| #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_POSITION 0x0758 |
| #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 |
| #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a |
| #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b |
| #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c |
| #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d |
| #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e |
| #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f |
| #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_CNTL 0x0760 |
| #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 |
| #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_STATUS 0x0762 |
| #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 |
| #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 |
| #define regCURSOR0_1_DMDATA_SW_DATA 0x0764 |
| #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x1de4 |
| #define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 |
| #define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a |
| #define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b |
| #define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_CNTL 0x077c |
| #define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_CNTL2 0x077d |
| #define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e |
| #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f |
| #define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_HI 0x0780 |
| #define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON8_PERFMON_LOW 0x0781 |
| #define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec |
| // base address: 0x6e0 |
| #define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d |
| #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
| #define regHUBP2_DCSURF_ADDR_CONFIG 0x079e |
| #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
| #define regHUBP2_DCSURF_TILING_CONFIG 0x079f |
| #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 |
| #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 |
| #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 |
| #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
| #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa |
| #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
| #define regHUBP2_DCHUBP_CNTL 0x07ab |
| #define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 |
| #define regHUBP2_HUBP_CLK_CNTL 0x07ac |
| #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 |
| #define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad |
| #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
| #define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae |
| #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
| #define regHUBP2_HUBPREQ_DEBUG 0x07af |
| #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 |
| #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 |
| #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
| #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 |
| #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec |
| // base address: 0x6e0 |
| #define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf |
| #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 |
| #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
| #define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 |
| #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 |
| #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 |
| #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd |
| #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 |
| #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 |
| #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 |
| #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 |
| #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 |
| #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc |
| #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 |
| #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 |
| #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 |
| #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 |
| #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 |
| #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 |
| #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 |
| #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 |
| #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 |
| #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 |
| #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea |
| #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb |
| #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec |
| #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed |
| #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee |
| #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
| #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb |
| #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
| #define regHUBPREQ2_BLANK_OFFSET_0 0x07fc |
| #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 |
| #define regHUBPREQ2_BLANK_OFFSET_1 0x07fd |
| #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 |
| #define regHUBPREQ2_DST_DIMENSIONS 0x07fe |
| #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 |
| #define regHUBPREQ2_DST_AFTER_SCALER 0x07ff |
| #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 |
| #define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 |
| #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 |
| #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 |
| #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 |
| #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 |
| #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_0 0x080a |
| #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_1 0x080b |
| #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_2 0x080c |
| #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_3 0x080d |
| #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_4 0x080e |
| #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_5 0x080f |
| #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 |
| #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 |
| #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 |
| #define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 |
| #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
| #define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 |
| #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 |
| #define regHUBPREQ2_CURSOR_SETTINGS 0x0814 |
| #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 |
| #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
| #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 |
| #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
| #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 |
| #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 |
| #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b |
| #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c |
| #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d |
| #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e |
| #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f |
| #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 |
| #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec |
| // base address: 0x6e0 |
| #define regHUBPRET2_HUBPRET_CONTROL 0x0824 |
| #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 |
| #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 |
| #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 |
| #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 |
| #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 |
| #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE1 0x082a |
| #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_INTERRUPT 0x082b |
| #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c |
| #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
| #define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d |
| #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec |
| // base address: 0x6e0 |
| #define regCURSOR0_2_CURSOR_CONTROL 0x0830 |
| #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 |
| #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 |
| #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_SIZE 0x0833 |
| #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_POSITION 0x0834 |
| #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 |
| #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 |
| #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 |
| #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 |
| #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 |
| #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a |
| #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b |
| #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_CNTL 0x083c |
| #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d |
| #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_STATUS 0x083e |
| #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_SW_CNTL 0x083f |
| #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 |
| #define regCURSOR0_2_DMDATA_SW_DATA 0x0840 |
| #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x2154 |
| #define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 |
| #define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 |
| #define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 |
| #define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_CNTL 0x0858 |
| #define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_CNTL2 0x0859 |
| #define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a |
| #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b |
| #define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_HI 0x085c |
| #define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON9_PERFMON_LOW 0x085d |
| #define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec |
| // base address: 0xa50 |
| #define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 |
| #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
| #define regHUBP3_DCSURF_ADDR_CONFIG 0x087a |
| #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
| #define regHUBP3_DCSURF_TILING_CONFIG 0x087b |
| #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 |
| #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 |
| #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
| #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 |
| #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
| #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 |
| #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
| #define regHUBP3_DCHUBP_CNTL 0x0887 |
| #define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 |
| #define regHUBP3_HUBP_CLK_CNTL 0x0888 |
| #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 |
| #define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 |
| #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
| #define regHUBP3_HUBPREQ_DEBUG_DB 0x088a |
| #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
| #define regHUBP3_HUBPREQ_DEBUG 0x088b |
| #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 |
| #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f |
| #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
| #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 |
| #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec |
| // base address: 0xa50 |
| #define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b |
| #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c |
| #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
| #define regHUBPREQ3_VMID_SETTINGS_0 0x089d |
| #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 |
| #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 |
| #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 |
| #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad |
| #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae |
| #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af |
| #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 |
| #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 |
| #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 |
| #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc |
| #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd |
| #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be |
| #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf |
| #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 |
| #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 |
| #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 |
| #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 |
| #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 |
| #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 |
| #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 |
| #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 |
| #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 |
| #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 |
| #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca |
| #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
| #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 |
| #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
| #define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 |
| #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 |
| #define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 |
| #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 |
| #define regHUBPREQ3_DST_DIMENSIONS 0x08da |
| #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 |
| #define regHUBPREQ3_DST_AFTER_SCALER 0x08db |
| #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 |
| #define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc |
| #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd |
| #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de |
| #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df |
| #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 |
| #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 |
| #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 |
| #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 |
| #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 |
| #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 |
| #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 |
| #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea |
| #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb |
| #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec |
| #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed |
| #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 |
| #define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee |
| #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
| #define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef |
| #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 |
| #define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 |
| #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 |
| #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 |
| #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
| #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 |
| #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
| #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 |
| #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 |
| #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 |
| #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 |
| #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa |
| #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb |
| #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 |
| #define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc |
| #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec |
| // base address: 0xa50 |
| #define regHUBPRET3_HUBPRET_CONTROL 0x0900 |
| #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 |
| #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 |
| #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 |
| #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 |
| #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 |
| #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 |
| #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 |
| #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 |
| #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
| #define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 |
| #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec |
| // base address: 0xa50 |
| #define regCURSOR0_3_CURSOR_CONTROL 0x090c |
| #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d |
| #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e |
| #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_SIZE 0x090f |
| #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_POSITION 0x0910 |
| #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 |
| #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 |
| #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 |
| #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 |
| #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 |
| #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 |
| #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 |
| #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_CNTL 0x0918 |
| #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 |
| #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_STATUS 0x091a |
| #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_SW_CNTL 0x091b |
| #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 |
| #define regCURSOR0_3_DMDATA_SW_DATA 0x091c |
| #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x24c4 |
| #define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 |
| #define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 |
| #define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 |
| #define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_CNTL 0x0934 |
| #define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_CNTL2 0x0935 |
| #define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 |
| #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 |
| #define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_HI 0x0938 |
| #define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON10_PERFMON_LOW 0x0939 |
| #define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec |
| // base address: 0x0 |
| #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf |
| #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 |
| #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 |
| #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 |
| #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 |
| #define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 |
| #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 |
| #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 |
| #define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 |
| #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 |
| #define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda |
| #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 |
| #define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb |
| #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 |
| #define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd |
| #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_DEALPHA 0x0cde |
| #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf |
| #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 |
| #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 |
| #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 |
| #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 |
| #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 |
| #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 |
| #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 |
| #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 |
| #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 |
| #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 |
| #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea |
| #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb |
| #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec |
| #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_DEGAM 0x0ced |
| #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 |
| #define regCNVC_CFG0_PRE_REALPHA 0x0cee |
| #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec |
| // base address: 0x0 |
| #define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 |
| #define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 |
| #define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 |
| #define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 |
| #define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 |
| #define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 |
| #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 |
| #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec |
| // base address: 0x0 |
| #define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 |
| #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
| #define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa |
| #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
| #define regDSCL0_SCL_MODE 0x0cfb |
| #define regDSCL0_SCL_MODE_BASE_IDX 2 |
| #define regDSCL0_SCL_TAP_CONTROL 0x0cfc |
| #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL0_DSCL_CONTROL 0x0cfd |
| #define regDSCL0_DSCL_CONTROL_BASE_IDX 2 |
| #define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe |
| #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff |
| #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
| #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 |
| #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 |
| #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 |
| #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 |
| #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 |
| #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 |
| #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 |
| #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
| #define regDSCL0_SCL_BLACK_COLOR 0x0d0a |
| #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 |
| #define regDSCL0_DSCL_UPDATE 0x0d0b |
| #define regDSCL0_DSCL_UPDATE_BASE_IDX 2 |
| #define regDSCL0_DSCL_AUTOCAL 0x0d0c |
| #define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 |
| #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d |
| #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
| #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e |
| #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
| #define regDSCL0_OTG_H_BLANK 0x0d0f |
| #define regDSCL0_OTG_H_BLANK_BASE_IDX 2 |
| #define regDSCL0_OTG_V_BLANK 0x0d10 |
| #define regDSCL0_OTG_V_BLANK_BASE_IDX 2 |
| #define regDSCL0_RECOUT_START 0x0d11 |
| #define regDSCL0_RECOUT_START_BASE_IDX 2 |
| #define regDSCL0_RECOUT_SIZE 0x0d12 |
| #define regDSCL0_RECOUT_SIZE_BASE_IDX 2 |
| #define regDSCL0_MPC_SIZE 0x0d13 |
| #define regDSCL0_MPC_SIZE_BASE_IDX 2 |
| #define regDSCL0_LB_DATA_FORMAT 0x0d14 |
| #define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 |
| #define regDSCL0_LB_MEMORY_CTRL 0x0d15 |
| #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 |
| #define regDSCL0_LB_V_COUNTER 0x0d16 |
| #define regDSCL0_LB_V_COUNTER_BASE_IDX 2 |
| #define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 |
| #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 |
| #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDSCL0_OBUF_CONTROL 0x0d19 |
| #define regDSCL0_OBUF_CONTROL_BASE_IDX 2 |
| #define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a |
| #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec |
| // base address: 0x0 |
| #define regCM0_CM_CONTROL 0x0d20 |
| #define regCM0_CM_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_CONTROL 0x0d21 |
| #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C11_C12 0x0d22 |
| #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C13_C14 0x0d23 |
| #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C21_C22 0x0d24 |
| #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C23_C24 0x0d25 |
| #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C31_C32 0x0d26 |
| #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_C33_C34 0x0d27 |
| #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 |
| #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 |
| #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a |
| #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b |
| #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c |
| #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d |
| #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e |
| #define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f |
| #define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 |
| #define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 |
| #define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 |
| #define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 |
| #define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 |
| #define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 |
| #define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 |
| #define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 |
| #define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 |
| #define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 |
| #define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
| #define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a |
| #define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
| #define regCM0_CM_BIAS_CR_R 0x0d3b |
| #define regCM0_CM_BIAS_CR_R_BASE_IDX 2 |
| #define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c |
| #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_CONTROL 0x0d3d |
| #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e |
| #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f |
| #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 |
| #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 |
| #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 |
| #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 |
| #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f |
| #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 |
| #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a |
| #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b |
| #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c |
| #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d |
| #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e |
| #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f |
| #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 |
| #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 |
| #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 |
| #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c |
| #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 |
| #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 |
| #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a |
| #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b |
| #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c |
| #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d |
| #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e |
| #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f |
| #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 |
| #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_CONTROL 0x0d87 |
| #define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 |
| #define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 |
| #define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a |
| #define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d |
| #define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 |
| #define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 |
| #define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 |
| #define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c |
| #define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad |
| #define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 |
| #define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 |
| #define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 |
| #define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc |
| #define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf |
| #define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 |
| #define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_HDR_MULT_COEF 0x0dd1 |
| #define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 |
| #define regCM0_CM_MEM_PWR_CTRL 0x0dd2 |
| #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCM0_CM_MEM_PWR_STATUS 0x0dd3 |
| #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCM0_CM_DEALPHA 0x0dd5 |
| #define regCM0_CM_DEALPHA_BASE_IDX 2 |
| #define regCM0_CM_COEF_FORMAT 0x0dd6 |
| #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_CONTROL 0x0dd7 |
| #define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 |
| #define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 |
| #define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_OFFSET_B 0x0dda |
| #define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_SCALE_R 0x0ddb |
| #define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc |
| #define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd |
| #define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_LUT_DATA 0x0dde |
| #define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf |
| #define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 |
| #define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 |
| #define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 |
| #define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 |
| #define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 |
| #define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 |
| #define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea |
| #define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb |
| #define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec |
| #define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded |
| #define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee |
| #define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def |
| #define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 |
| #define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 |
| #define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 |
| #define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 |
| #define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 |
| #define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 |
| #define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 |
| #define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc |
| #define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd |
| #define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe |
| #define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff |
| #define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 |
| #define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 |
| #define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 |
| #define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 |
| #define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 |
| #define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 |
| #define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 |
| #define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 |
| #define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 |
| #define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 |
| #define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a |
| #define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b |
| #define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c |
| #define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d |
| #define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM0_CM_MEM_PWR_CTRL2 0x0e0e |
| #define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 |
| #define regCM0_CM_MEM_PWR_STATUS2 0x0e0f |
| #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_MODE 0x0e10 |
| #define regCM0_CM_3DLUT_MODE_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_INDEX 0x0e11 |
| #define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_DATA 0x0e12 |
| #define regCM0_CM_3DLUT_DATA_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 |
| #define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 |
| #define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 |
| #define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 |
| #define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 |
| #define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 |
| #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regCM0_CM_TEST_DEBUG_DATA 0x0e1a |
| #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec |
| // base address: 0x0 |
| #define regDPP_TOP0_DPP_CONTROL 0x0cc5 |
| #define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 |
| #define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 |
| #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 |
| #define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 |
| #define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 |
| #define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 |
| #define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 |
| #define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 |
| #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 |
| #define regDPP_TOP0_HOST_READ_CONTROL 0x0cca |
| #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x3890 |
| #define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 |
| #define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 |
| #define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 |
| #define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_CNTL 0x0e27 |
| #define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 |
| #define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 |
| #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a |
| #define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_HI 0x0e2b |
| #define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON11_PERFMON_LOW 0x0e2c |
| #define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec |
| // base address: 0x5ac |
| #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a |
| #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b |
| #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c |
| #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d |
| #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e |
| #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f |
| #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 |
| #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 |
| #define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 |
| #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 |
| #define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 |
| #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 |
| #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 |
| #define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 |
| #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 |
| #define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 |
| #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 |
| #define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 |
| #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 |
| #define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 |
| #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_DEALPHA 0x0e49 |
| #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a |
| #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b |
| #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c |
| #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d |
| #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e |
| #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f |
| #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 |
| #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 |
| #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 |
| #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 |
| #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 |
| #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 |
| #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 |
| #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 |
| #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_DEGAM 0x0e58 |
| #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 |
| #define regCNVC_CFG1_PRE_REALPHA 0x0e59 |
| #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec |
| // base address: 0x5ac |
| #define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c |
| #define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 |
| #define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d |
| #define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 |
| #define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e |
| #define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 |
| #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f |
| #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec |
| // base address: 0x5ac |
| #define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 |
| #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
| #define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 |
| #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
| #define regDSCL1_SCL_MODE 0x0e66 |
| #define regDSCL1_SCL_MODE_BASE_IDX 2 |
| #define regDSCL1_SCL_TAP_CONTROL 0x0e67 |
| #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL1_DSCL_CONTROL 0x0e68 |
| #define regDSCL1_DSCL_CONTROL_BASE_IDX 2 |
| #define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 |
| #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a |
| #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
| #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b |
| #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c |
| #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d |
| #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e |
| #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f |
| #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 |
| #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 |
| #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
| #define regDSCL1_SCL_BLACK_COLOR 0x0e75 |
| #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 |
| #define regDSCL1_DSCL_UPDATE 0x0e76 |
| #define regDSCL1_DSCL_UPDATE_BASE_IDX 2 |
| #define regDSCL1_DSCL_AUTOCAL 0x0e77 |
| #define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 |
| #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 |
| #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
| #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 |
| #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
| #define regDSCL1_OTG_H_BLANK 0x0e7a |
| #define regDSCL1_OTG_H_BLANK_BASE_IDX 2 |
| #define regDSCL1_OTG_V_BLANK 0x0e7b |
| #define regDSCL1_OTG_V_BLANK_BASE_IDX 2 |
| #define regDSCL1_RECOUT_START 0x0e7c |
| #define regDSCL1_RECOUT_START_BASE_IDX 2 |
| #define regDSCL1_RECOUT_SIZE 0x0e7d |
| #define regDSCL1_RECOUT_SIZE_BASE_IDX 2 |
| #define regDSCL1_MPC_SIZE 0x0e7e |
| #define regDSCL1_MPC_SIZE_BASE_IDX 2 |
| #define regDSCL1_LB_DATA_FORMAT 0x0e7f |
| #define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 |
| #define regDSCL1_LB_MEMORY_CTRL 0x0e80 |
| #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 |
| #define regDSCL1_LB_V_COUNTER 0x0e81 |
| #define regDSCL1_LB_V_COUNTER_BASE_IDX 2 |
| #define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 |
| #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 |
| #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDSCL1_OBUF_CONTROL 0x0e84 |
| #define regDSCL1_OBUF_CONTROL_BASE_IDX 2 |
| #define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 |
| #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec |
| // base address: 0x5ac |
| #define regCM1_CM_CONTROL 0x0e8b |
| #define regCM1_CM_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_CONTROL 0x0e8c |
| #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C11_C12 0x0e8d |
| #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C13_C14 0x0e8e |
| #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C21_C22 0x0e8f |
| #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C23_C24 0x0e90 |
| #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C31_C32 0x0e91 |
| #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_C33_C34 0x0e92 |
| #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 |
| #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 |
| #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 |
| #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 |
| #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 |
| #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 |
| #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 |
| #define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a |
| #define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b |
| #define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c |
| #define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d |
| #define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e |
| #define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f |
| #define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 |
| #define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 |
| #define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 |
| #define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 |
| #define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 |
| #define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
| #define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 |
| #define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
| #define regCM1_CM_BIAS_CR_R 0x0ea6 |
| #define regCM1_CM_BIAS_CR_R_BASE_IDX 2 |
| #define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 |
| #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_CONTROL 0x0ea8 |
| #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 |
| #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa |
| #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab |
| #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae |
| #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 |
| #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 |
| #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba |
| #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd |
| #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe |
| #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf |
| #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca |
| #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb |
| #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc |
| #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd |
| #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece |
| #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 |
| #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 |
| #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 |
| #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd |
| #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 |
| #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea |
| #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb |
| #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec |
| #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed |
| #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee |
| #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef |
| #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 |
| #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 |
| #define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 |
| #define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 |
| #define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 |
| #define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 |
| #define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb |
| #define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe |
| #define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 |
| #define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 |
| #define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 |
| #define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b |
| #define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e |
| #define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 |
| #define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 |
| #define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a |
| #define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b |
| #define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_HDR_MULT_COEF 0x0f3c |
| #define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 |
| #define regCM1_CM_MEM_PWR_CTRL 0x0f3d |
| #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCM1_CM_MEM_PWR_STATUS 0x0f3e |
| #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCM1_CM_DEALPHA 0x0f40 |
| #define regCM1_CM_DEALPHA_BASE_IDX 2 |
| #define regCM1_CM_COEF_FORMAT 0x0f41 |
| #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_CONTROL 0x0f42 |
| #define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_OFFSET_R 0x0f43 |
| #define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_OFFSET_G 0x0f44 |
| #define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_OFFSET_B 0x0f45 |
| #define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_SCALE_R 0x0f46 |
| #define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 |
| #define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 |
| #define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_LUT_DATA 0x0f49 |
| #define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a |
| #define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d |
| #define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 |
| #define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 |
| #define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 |
| #define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 |
| #define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 |
| #define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 |
| #define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 |
| #define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 |
| #define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 |
| #define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 |
| #define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a |
| #define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b |
| #define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c |
| #define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d |
| #define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e |
| #define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f |
| #define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 |
| #define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 |
| #define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 |
| #define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 |
| #define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 |
| #define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 |
| #define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a |
| #define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b |
| #define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c |
| #define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d |
| #define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e |
| #define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f |
| #define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 |
| #define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 |
| #define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 |
| #define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 |
| #define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 |
| #define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 |
| #define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 |
| #define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 |
| #define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 |
| #define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM1_CM_MEM_PWR_CTRL2 0x0f79 |
| #define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 |
| #define regCM1_CM_MEM_PWR_STATUS2 0x0f7a |
| #define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_MODE 0x0f7b |
| #define regCM1_CM_3DLUT_MODE_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_INDEX 0x0f7c |
| #define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_DATA 0x0f7d |
| #define regCM1_CM_3DLUT_DATA_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e |
| #define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f |
| #define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 |
| #define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 |
| #define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 |
| #define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 |
| #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regCM1_CM_TEST_DEBUG_DATA 0x0f85 |
| #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec |
| // base address: 0x5ac |
| #define regDPP_TOP1_DPP_CONTROL 0x0e30 |
| #define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 |
| #define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 |
| #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 |
| #define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 |
| #define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 |
| #define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 |
| #define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 |
| #define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 |
| #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 |
| #define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 |
| #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x3e3c |
| #define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f |
| #define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 |
| #define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 |
| #define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_CNTL 0x0f92 |
| #define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 |
| #define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 |
| #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 |
| #define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_HI 0x0f96 |
| #define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON12_PERFMON_LOW 0x0f97 |
| #define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec |
| // base address: 0xb58 |
| #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 |
| #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 |
| #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 |
| #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa |
| #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab |
| #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 |
| #define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac |
| #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 |
| #define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad |
| #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae |
| #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 |
| #define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf |
| #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 |
| #define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 |
| #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 |
| #define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 |
| #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 |
| #define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 |
| #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 |
| #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 |
| #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 |
| #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 |
| #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 |
| #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 |
| #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba |
| #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb |
| #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc |
| #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd |
| #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe |
| #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf |
| #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 |
| #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 |
| #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 |
| #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_DEGAM 0x0fc3 |
| #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 |
| #define regCNVC_CFG2_PRE_REALPHA 0x0fc4 |
| #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec |
| // base address: 0xb58 |
| #define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 |
| #define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 |
| #define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 |
| #define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 |
| #define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 |
| #define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 |
| #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca |
| #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec |
| // base address: 0xb58 |
| #define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf |
| #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
| #define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 |
| #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
| #define regDSCL2_SCL_MODE 0x0fd1 |
| #define regDSCL2_SCL_MODE_BASE_IDX 2 |
| #define regDSCL2_SCL_TAP_CONTROL 0x0fd2 |
| #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL2_DSCL_CONTROL 0x0fd3 |
| #define regDSCL2_DSCL_CONTROL_BASE_IDX 2 |
| #define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 |
| #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 |
| #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
| #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 |
| #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 |
| #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 |
| #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 |
| #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda |
| #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb |
| #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc |
| #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd |
| #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde |
| #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf |
| #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
| #define regDSCL2_SCL_BLACK_COLOR 0x0fe0 |
| #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 |
| #define regDSCL2_DSCL_UPDATE 0x0fe1 |
| #define regDSCL2_DSCL_UPDATE_BASE_IDX 2 |
| #define regDSCL2_DSCL_AUTOCAL 0x0fe2 |
| #define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 |
| #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 |
| #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
| #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 |
| #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
| #define regDSCL2_OTG_H_BLANK 0x0fe5 |
| #define regDSCL2_OTG_H_BLANK_BASE_IDX 2 |
| #define regDSCL2_OTG_V_BLANK 0x0fe6 |
| #define regDSCL2_OTG_V_BLANK_BASE_IDX 2 |
| #define regDSCL2_RECOUT_START 0x0fe7 |
| #define regDSCL2_RECOUT_START_BASE_IDX 2 |
| #define regDSCL2_RECOUT_SIZE 0x0fe8 |
| #define regDSCL2_RECOUT_SIZE_BASE_IDX 2 |
| #define regDSCL2_MPC_SIZE 0x0fe9 |
| #define regDSCL2_MPC_SIZE_BASE_IDX 2 |
| #define regDSCL2_LB_DATA_FORMAT 0x0fea |
| #define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 |
| #define regDSCL2_LB_MEMORY_CTRL 0x0feb |
| #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 |
| #define regDSCL2_LB_V_COUNTER 0x0fec |
| #define regDSCL2_LB_V_COUNTER_BASE_IDX 2 |
| #define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed |
| #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee |
| #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDSCL2_OBUF_CONTROL 0x0fef |
| #define regDSCL2_OBUF_CONTROL_BASE_IDX 2 |
| #define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 |
| #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec |
| // base address: 0xb58 |
| #define regCM2_CM_CONTROL 0x0ff6 |
| #define regCM2_CM_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_CONTROL 0x0ff7 |
| #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C11_C12 0x0ff8 |
| #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C13_C14 0x0ff9 |
| #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C21_C22 0x0ffa |
| #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C23_C24 0x0ffb |
| #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C31_C32 0x0ffc |
| #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_C33_C34 0x0ffd |
| #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe |
| #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C13_C14 0x0fff |
| #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C21_C22 0x1000 |
| #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C23_C24 0x1001 |
| #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C31_C32 0x1002 |
| #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCM2_CM_POST_CSC_B_C33_C34 0x1003 |
| #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 |
| #define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 |
| #define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 |
| #define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 |
| #define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 |
| #define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 |
| #define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a |
| #define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b |
| #define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c |
| #define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d |
| #define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e |
| #define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f |
| #define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
| #define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 |
| #define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
| #define regCM2_CM_BIAS_CR_R 0x1011 |
| #define regCM2_CM_BIAS_CR_R_BASE_IDX 2 |
| #define regCM2_CM_BIAS_Y_G_CB_B 0x1012 |
| #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_CONTROL 0x1013 |
| #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 |
| #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_LUT_DATA 0x1015 |
| #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 |
| #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 |
| #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c |
| #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f |
| #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 |
| #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 |
| #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a |
| #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b |
| #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c |
| #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d |
| #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e |
| #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f |
| #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 |
| #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c |
| #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f |
| #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 |
| #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 |
| #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b |
| #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c |
| #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d |
| #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e |
| #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f |
| #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a |
| #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b |
| #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c |
| #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_CONTROL 0x105d |
| #define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e |
| #define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_LUT_DATA 0x105f |
| #define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 |
| #define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 |
| #define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 |
| #define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 |
| #define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f |
| #define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 |
| #define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 |
| #define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 |
| #define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 |
| #define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c |
| #define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 |
| #define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 |
| #define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 |
| #define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_HDR_MULT_COEF 0x10a7 |
| #define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 |
| #define regCM2_CM_MEM_PWR_CTRL 0x10a8 |
| #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCM2_CM_MEM_PWR_STATUS 0x10a9 |
| #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCM2_CM_DEALPHA 0x10ab |
| #define regCM2_CM_DEALPHA_BASE_IDX 2 |
| #define regCM2_CM_COEF_FORMAT 0x10ac |
| #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_CONTROL 0x10ad |
| #define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_OFFSET_R 0x10ae |
| #define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_OFFSET_G 0x10af |
| #define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_OFFSET_B 0x10b0 |
| #define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_SCALE_R 0x10b1 |
| #define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 |
| #define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 |
| #define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_LUT_DATA 0x10b4 |
| #define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 |
| #define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 |
| #define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb |
| #define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc |
| #define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd |
| #define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be |
| #define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf |
| #define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 |
| #define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 |
| #define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 |
| #define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 |
| #define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 |
| #define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 |
| #define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 |
| #define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 |
| #define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 |
| #define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca |
| #define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb |
| #define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc |
| #define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf |
| #define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 |
| #define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 |
| #define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 |
| #define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 |
| #define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 |
| #define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 |
| #define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 |
| #define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 |
| #define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da |
| #define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db |
| #define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc |
| #define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd |
| #define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de |
| #define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df |
| #define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 |
| #define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 |
| #define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 |
| #define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM2_CM_MEM_PWR_CTRL2 0x10e4 |
| #define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 |
| #define regCM2_CM_MEM_PWR_STATUS2 0x10e5 |
| #define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_MODE 0x10e6 |
| #define regCM2_CM_3DLUT_MODE_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_INDEX 0x10e7 |
| #define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_DATA 0x10e8 |
| #define regCM2_CM_3DLUT_DATA_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 |
| #define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea |
| #define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb |
| #define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec |
| #define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed |
| #define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 |
| #define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee |
| #define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 |
| #define regCM2_CM_TEST_DEBUG_INDEX 0x10ef |
| #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regCM2_CM_TEST_DEBUG_DATA 0x10f0 |
| #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec |
| // base address: 0xb58 |
| #define regDPP_TOP2_DPP_CONTROL 0x0f9b |
| #define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 |
| #define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c |
| #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 |
| #define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d |
| #define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 |
| #define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e |
| #define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 |
| #define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f |
| #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 |
| #define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 |
| #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x43e8 |
| #define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa |
| #define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb |
| #define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc |
| #define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_CNTL 0x10fd |
| #define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_CNTL2 0x10fe |
| #define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff |
| #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 |
| #define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_HI 0x1101 |
| #define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON13_PERFMON_LOW 0x1102 |
| #define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec |
| // base address: 0x1104 |
| #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 |
| #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG3_FORMAT_CONTROL 0x1111 |
| #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 |
| #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 |
| #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 |
| #define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 |
| #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 |
| #define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 |
| #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 |
| #define regCNVC_CFG3_COLOR_KEYER_RED 0x111a |
| #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 |
| #define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b |
| #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 |
| #define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c |
| #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 |
| #define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e |
| #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_DEALPHA 0x111f |
| #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_MODE 0x1120 |
| #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 |
| #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 |
| #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 |
| #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 |
| #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 |
| #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 |
| #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 |
| #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 |
| #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 |
| #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a |
| #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b |
| #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c |
| #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d |
| #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_DEGAM 0x112e |
| #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 |
| #define regCNVC_CFG3_PRE_REALPHA 0x112f |
| #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec |
| // base address: 0x1104 |
| #define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 |
| #define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 |
| #define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 |
| #define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 |
| #define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 |
| #define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 |
| #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 |
| #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec |
| // base address: 0x1104 |
| #define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a |
| #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
| #define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b |
| #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
| #define regDSCL3_SCL_MODE 0x113c |
| #define regDSCL3_SCL_MODE_BASE_IDX 2 |
| #define regDSCL3_SCL_TAP_CONTROL 0x113d |
| #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL3_DSCL_CONTROL 0x113e |
| #define regDSCL3_DSCL_CONTROL_BASE_IDX 2 |
| #define regDSCL3_DSCL_2TAP_CONTROL 0x113f |
| #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 |
| #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 |
| #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
| #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 |
| #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 |
| #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 |
| #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 |
| #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 |
| #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 |
| #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
| #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a |
| #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
| #define regDSCL3_SCL_BLACK_COLOR 0x114b |
| #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 |
| #define regDSCL3_DSCL_UPDATE 0x114c |
| #define regDSCL3_DSCL_UPDATE_BASE_IDX 2 |
| #define regDSCL3_DSCL_AUTOCAL 0x114d |
| #define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 |
| #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e |
| #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
| #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f |
| #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
| #define regDSCL3_OTG_H_BLANK 0x1150 |
| #define regDSCL3_OTG_H_BLANK_BASE_IDX 2 |
| #define regDSCL3_OTG_V_BLANK 0x1151 |
| #define regDSCL3_OTG_V_BLANK_BASE_IDX 2 |
| #define regDSCL3_RECOUT_START 0x1152 |
| #define regDSCL3_RECOUT_START_BASE_IDX 2 |
| #define regDSCL3_RECOUT_SIZE 0x1153 |
| #define regDSCL3_RECOUT_SIZE_BASE_IDX 2 |
| #define regDSCL3_MPC_SIZE 0x1154 |
| #define regDSCL3_MPC_SIZE_BASE_IDX 2 |
| #define regDSCL3_LB_DATA_FORMAT 0x1155 |
| #define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 |
| #define regDSCL3_LB_MEMORY_CTRL 0x1156 |
| #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 |
| #define regDSCL3_LB_V_COUNTER 0x1157 |
| #define regDSCL3_LB_V_COUNTER_BASE_IDX 2 |
| #define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 |
| #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 |
| #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDSCL3_OBUF_CONTROL 0x115a |
| #define regDSCL3_OBUF_CONTROL_BASE_IDX 2 |
| #define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b |
| #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec |
| // base address: 0x1104 |
| #define regCM3_CM_CONTROL 0x1161 |
| #define regCM3_CM_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_CONTROL 0x1162 |
| #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C11_C12 0x1163 |
| #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C13_C14 0x1164 |
| #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C21_C22 0x1165 |
| #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C23_C24 0x1166 |
| #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C31_C32 0x1167 |
| #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_C33_C34 0x1168 |
| #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C11_C12 0x1169 |
| #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C13_C14 0x116a |
| #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C21_C22 0x116b |
| #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C23_C24 0x116c |
| #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C31_C32 0x116d |
| #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
| #define regCM3_CM_POST_CSC_B_C33_C34 0x116e |
| #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f |
| #define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 |
| #define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 |
| #define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 |
| #define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 |
| #define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 |
| #define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 |
| #define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 |
| #define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 |
| #define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 |
| #define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 |
| #define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a |
| #define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
| #define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b |
| #define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
| #define regCM3_CM_BIAS_CR_R 0x117c |
| #define regCM3_CM_BIAS_CR_R_BASE_IDX 2 |
| #define regCM3_CM_BIAS_Y_G_CB_B 0x117d |
| #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_CONTROL 0x117e |
| #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_LUT_INDEX 0x117f |
| #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_LUT_DATA 0x1180 |
| #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 |
| #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 |
| #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 |
| #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a |
| #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 |
| #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 |
| #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a |
| #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b |
| #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c |
| #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d |
| #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e |
| #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f |
| #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 |
| #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 |
| #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa |
| #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad |
| #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 |
| #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 |
| #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba |
| #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb |
| #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc |
| #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd |
| #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be |
| #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf |
| #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 |
| #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_CONTROL 0x11c8 |
| #define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 |
| #define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca |
| #define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb |
| #define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce |
| #define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 |
| #define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 |
| #define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da |
| #define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd |
| #define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee |
| #define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 |
| #define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 |
| #define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 |
| #define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd |
| #define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 |
| #define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 |
| #define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_HDR_MULT_COEF 0x1212 |
| #define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 |
| #define regCM3_CM_MEM_PWR_CTRL 0x1213 |
| #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regCM3_CM_MEM_PWR_STATUS 0x1214 |
| #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regCM3_CM_DEALPHA 0x1216 |
| #define regCM3_CM_DEALPHA_BASE_IDX 2 |
| #define regCM3_CM_COEF_FORMAT 0x1217 |
| #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_CONTROL 0x1218 |
| #define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_OFFSET_R 0x1219 |
| #define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_OFFSET_G 0x121a |
| #define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_OFFSET_B 0x121b |
| #define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_SCALE_R 0x121c |
| #define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_SCALE_G_B 0x121d |
| #define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_LUT_INDEX 0x121e |
| #define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_LUT_DATA 0x121f |
| #define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 |
| #define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 |
| #define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 |
| #define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 |
| #define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 |
| #define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 |
| #define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a |
| #define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b |
| #define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c |
| #define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d |
| #define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e |
| #define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f |
| #define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 |
| #define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 |
| #define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 |
| #define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 |
| #define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 |
| #define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 |
| #define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 |
| #define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 |
| #define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a |
| #define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d |
| #define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e |
| #define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f |
| #define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 |
| #define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 |
| #define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 |
| #define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 |
| #define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 |
| #define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 |
| #define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 |
| #define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 |
| #define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 |
| #define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 |
| #define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a |
| #define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b |
| #define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c |
| #define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d |
| #define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 |
| #define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e |
| #define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 |
| #define regCM3_CM_MEM_PWR_CTRL2 0x124f |
| #define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 |
| #define regCM3_CM_MEM_PWR_STATUS2 0x1250 |
| #define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_MODE 0x1251 |
| #define regCM3_CM_3DLUT_MODE_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_INDEX 0x1252 |
| #define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_DATA 0x1253 |
| #define regCM3_CM_3DLUT_DATA_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_DATA_30BIT 0x1254 |
| #define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 |
| #define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 |
| #define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 |
| #define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 |
| #define regCM3_CM_TEST_DEBUG_INDEX 0x125a |
| #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
| #define regCM3_CM_TEST_DEBUG_DATA 0x125b |
| #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec |
| // base address: 0x1104 |
| #define regDPP_TOP3_DPP_CONTROL 0x1106 |
| #define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 |
| #define regDPP_TOP3_DPP_SOFT_RESET 0x1107 |
| #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 |
| #define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 |
| #define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 |
| #define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 |
| #define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 |
| #define regDPP_TOP3_DPP_CRC_CTRL 0x110a |
| #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 |
| #define regDPP_TOP3_HOST_READ_CONTROL 0x110b |
| #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x4994 |
| #define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 |
| #define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 |
| #define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 |
| #define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_CNTL 0x1268 |
| #define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_CNTL2 0x1269 |
| #define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a |
| #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b |
| #define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_HI 0x126c |
| #define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON14_PERFMON_LOW 0x126d |
| #define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc0_dispdec |
| // base address: 0x0 |
| #define regMPCC0_MPCC_TOP_SEL 0x0000 |
| #define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 |
| #define regMPCC0_MPCC_BOT_SEL 0x0001 |
| #define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 |
| #define regMPCC0_MPCC_OPP_ID 0x0002 |
| #define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 |
| #define regMPCC0_MPCC_CONTROL 0x0003 |
| #define regMPCC0_MPCC_CONTROL_BASE_IDX 3 |
| #define regMPCC0_MPCC_SM_CONTROL 0x0004 |
| #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 |
| #define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 |
| #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
| #define regMPCC0_MPCC_TOP_GAIN 0x0006 |
| #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 |
| #define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 |
| #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
| #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 |
| #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
| #define regMPCC0_MPCC_BG_R_CR 0x0009 |
| #define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 |
| #define regMPCC0_MPCC_BG_G_Y 0x000a |
| #define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 |
| #define regMPCC0_MPCC_BG_B_CB 0x000b |
| #define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 |
| #define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c |
| #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
| #define regMPCC0_MPCC_STATUS 0x000d |
| #define regMPCC0_MPCC_STATUS_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc1_dispdec |
| // base address: 0x80 |
| #define regMPCC1_MPCC_TOP_SEL 0x0020 |
| #define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 |
| #define regMPCC1_MPCC_BOT_SEL 0x0021 |
| #define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 |
| #define regMPCC1_MPCC_OPP_ID 0x0022 |
| #define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 |
| #define regMPCC1_MPCC_CONTROL 0x0023 |
| #define regMPCC1_MPCC_CONTROL_BASE_IDX 3 |
| #define regMPCC1_MPCC_SM_CONTROL 0x0024 |
| #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 |
| #define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 |
| #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
| #define regMPCC1_MPCC_TOP_GAIN 0x0026 |
| #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 |
| #define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 |
| #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
| #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 |
| #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
| #define regMPCC1_MPCC_BG_R_CR 0x0029 |
| #define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 |
| #define regMPCC1_MPCC_BG_G_Y 0x002a |
| #define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 |
| #define regMPCC1_MPCC_BG_B_CB 0x002b |
| #define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 |
| #define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c |
| #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
| #define regMPCC1_MPCC_STATUS 0x002d |
| #define regMPCC1_MPCC_STATUS_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc2_dispdec |
| // base address: 0x100 |
| #define regMPCC2_MPCC_TOP_SEL 0x0040 |
| #define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 |
| #define regMPCC2_MPCC_BOT_SEL 0x0041 |
| #define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 |
| #define regMPCC2_MPCC_OPP_ID 0x0042 |
| #define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 |
| #define regMPCC2_MPCC_CONTROL 0x0043 |
| #define regMPCC2_MPCC_CONTROL_BASE_IDX 3 |
| #define regMPCC2_MPCC_SM_CONTROL 0x0044 |
| #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 |
| #define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 |
| #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
| #define regMPCC2_MPCC_TOP_GAIN 0x0046 |
| #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 |
| #define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 |
| #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
| #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 |
| #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
| #define regMPCC2_MPCC_BG_R_CR 0x0049 |
| #define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 |
| #define regMPCC2_MPCC_BG_G_Y 0x004a |
| #define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 |
| #define regMPCC2_MPCC_BG_B_CB 0x004b |
| #define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 |
| #define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c |
| #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
| #define regMPCC2_MPCC_STATUS 0x004d |
| #define regMPCC2_MPCC_STATUS_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc3_dispdec |
| // base address: 0x180 |
| #define regMPCC3_MPCC_TOP_SEL 0x0060 |
| #define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 |
| #define regMPCC3_MPCC_BOT_SEL 0x0061 |
| #define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 |
| #define regMPCC3_MPCC_OPP_ID 0x0062 |
| #define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 |
| #define regMPCC3_MPCC_CONTROL 0x0063 |
| #define regMPCC3_MPCC_CONTROL_BASE_IDX 3 |
| #define regMPCC3_MPCC_SM_CONTROL 0x0064 |
| #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 |
| #define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 |
| #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
| #define regMPCC3_MPCC_TOP_GAIN 0x0066 |
| #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 |
| #define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 |
| #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
| #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 |
| #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
| #define regMPCC3_MPCC_BG_R_CR 0x0069 |
| #define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 |
| #define regMPCC3_MPCC_BG_G_Y 0x006a |
| #define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 |
| #define regMPCC3_MPCC_BG_B_CB 0x006b |
| #define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 |
| #define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c |
| #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
| #define regMPCC3_MPCC_STATUS 0x006d |
| #define regMPCC3_MPCC_STATUS_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpc_cfg_dispdec |
| // base address: 0x0 |
| #define regMPC_CLOCK_CONTROL 0x0500 |
| #define regMPC_CLOCK_CONTROL_BASE_IDX 3 |
| #define regMPC_SOFT_RESET 0x0501 |
| #define regMPC_SOFT_RESET_BASE_IDX 3 |
| #define regMPC_CRC_CTRL 0x0502 |
| #define regMPC_CRC_CTRL_BASE_IDX 3 |
| #define regMPC_CRC_SEL_CONTROL 0x0503 |
| #define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 |
| #define regMPC_CRC_RESULT_AR 0x0504 |
| #define regMPC_CRC_RESULT_AR_BASE_IDX 3 |
| #define regMPC_CRC_RESULT_GB 0x0505 |
| #define regMPC_CRC_RESULT_GB_BASE_IDX 3 |
| #define regMPC_CRC_RESULT_C 0x0506 |
| #define regMPC_CRC_RESULT_C_BASE_IDX 3 |
| #define regMPC_PERFMON_EVENT_CTRL 0x0509 |
| #define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 |
| #define regMPC_BYPASS_BG_AR 0x050a |
| #define regMPC_BYPASS_BG_AR_BASE_IDX 3 |
| #define regMPC_BYPASS_BG_GB 0x050b |
| #define regMPC_BYPASS_BG_GB_BASE_IDX 3 |
| #define regMPC_HOST_READ_CONTROL 0x050c |
| #define regMPC_HOST_READ_CONTROL_BASE_IDX 3 |
| #define regMPC_DPP_PENDING_STATUS 0x050d |
| #define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 |
| #define regMPC_PENDING_STATUS_MISC 0x050e |
| #define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
| #define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 |
| #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 |
| #define regADR_VUPDATE_LOCK_SET0 0x0511 |
| #define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
| #define regCFG_VUPDATE_LOCK_SET0 0x0512 |
| #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 |
| #define regCUR_VUPDATE_LOCK_SET0 0x0513 |
| #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
| #define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 |
| #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 |
| #define regADR_VUPDATE_LOCK_SET1 0x0516 |
| #define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
| #define regCFG_VUPDATE_LOCK_SET1 0x0517 |
| #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 |
| #define regCUR_VUPDATE_LOCK_SET1 0x0518 |
| #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
| #define regADR_CFG_VUPDATE_LOCK_SET2 0x051a |
| #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 |
| #define regADR_VUPDATE_LOCK_SET2 0x051b |
| #define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
| #define regCFG_VUPDATE_LOCK_SET2 0x051c |
| #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 |
| #define regCUR_VUPDATE_LOCK_SET2 0x051d |
| #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e |
| #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
| #define regADR_CFG_VUPDATE_LOCK_SET3 0x051f |
| #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 |
| #define regADR_VUPDATE_LOCK_SET3 0x0520 |
| #define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
| #define regCFG_VUPDATE_LOCK_SET3 0x0521 |
| #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 |
| #define regCUR_VUPDATE_LOCK_SET3 0x0522 |
| #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
| #define regMPC_DWB0_MUX 0x055c |
| #define regMPC_DWB0_MUX_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x1901c |
| #define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 |
| #define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 |
| #define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 |
| #define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_CNTL 0x08ca |
| #define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_CNTL2 0x08cb |
| #define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc |
| #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd |
| #define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_HI 0x08ce |
| #define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 |
| #define regDC_PERFMON15_PERFMON_LOW 0x08cf |
| #define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec |
| // base address: 0x0 |
| #define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 |
| #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 |
| #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 |
| #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a |
| #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b |
| #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 |
| #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec |
| // base address: 0x200 |
| #define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 |
| #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 |
| #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 |
| #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca |
| #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb |
| #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 |
| #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec |
| // base address: 0x400 |
| #define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 |
| #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 |
| #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 |
| #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a |
| #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b |
| #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 |
| #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec |
| // base address: 0x600 |
| #define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 |
| #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 |
| #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 |
| #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca |
| #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb |
| #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 |
| #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec |
| // base address: 0x0 |
| #define regMPC_OUT0_MUX 0x0580 |
| #define regMPC_OUT0_MUX_BASE_IDX 3 |
| #define regMPC_OUT0_DENORM_CONTROL 0x0581 |
| #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 |
| #define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 |
| #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 |
| #define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 |
| #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 |
| #define regMPC_OUT1_MUX 0x0584 |
| #define regMPC_OUT1_MUX_BASE_IDX 3 |
| #define regMPC_OUT1_DENORM_CONTROL 0x0585 |
| #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 |
| #define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 |
| #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 |
| #define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 |
| #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 |
| #define regMPC_OUT2_MUX 0x0588 |
| #define regMPC_OUT2_MUX_BASE_IDX 3 |
| #define regMPC_OUT2_DENORM_CONTROL 0x0589 |
| #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 |
| #define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a |
| #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 |
| #define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b |
| #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 |
| #define regMPC_OUT3_MUX 0x058c |
| #define regMPC_OUT3_MUX_BASE_IDX 3 |
| #define regMPC_OUT3_DENORM_CONTROL 0x058d |
| #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 |
| #define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e |
| #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 |
| #define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f |
| #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 |
| #define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 |
| #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_MODE 0x05a1 |
| #define regMPC_OUT0_CSC_MODE_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C11_C12_A 0x05a2 |
| #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C13_C14_A 0x05a3 |
| #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C21_C22_A 0x05a4 |
| #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C23_C24_A 0x05a5 |
| #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C31_C32_A 0x05a6 |
| #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C33_C34_A 0x05a7 |
| #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C11_C12_B 0x05a8 |
| #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C13_C14_B 0x05a9 |
| #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C21_C22_B 0x05aa |
| #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C23_C24_B 0x05ab |
| #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C31_C32_B 0x05ac |
| #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 |
| #define regMPC_OUT0_CSC_C33_C34_B 0x05ad |
| #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_MODE 0x05ae |
| #define regMPC_OUT1_CSC_MODE_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C11_C12_A 0x05af |
| #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C13_C14_A 0x05b0 |
| #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C21_C22_A 0x05b1 |
| #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C23_C24_A 0x05b2 |
| #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C31_C32_A 0x05b3 |
| #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C33_C34_A 0x05b4 |
| #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C11_C12_B 0x05b5 |
| #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C13_C14_B 0x05b6 |
| #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C21_C22_B 0x05b7 |
| #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C23_C24_B 0x05b8 |
| #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C31_C32_B 0x05b9 |
| #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 |
| #define regMPC_OUT1_CSC_C33_C34_B 0x05ba |
| #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_MODE 0x05bb |
| #define regMPC_OUT2_CSC_MODE_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C11_C12_A 0x05bc |
| #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C13_C14_A 0x05bd |
| #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C21_C22_A 0x05be |
| #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C23_C24_A 0x05bf |
| #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C31_C32_A 0x05c0 |
| #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C33_C34_A 0x05c1 |
| #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C11_C12_B 0x05c2 |
| #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C13_C14_B 0x05c3 |
| #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C21_C22_B 0x05c4 |
| #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C23_C24_B 0x05c5 |
| #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C31_C32_B 0x05c6 |
| #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 |
| #define regMPC_OUT2_CSC_C33_C34_B 0x05c7 |
| #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_MODE 0x05c8 |
| #define regMPC_OUT3_CSC_MODE_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C11_C12_A 0x05c9 |
| #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C13_C14_A 0x05ca |
| #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C21_C22_A 0x05cb |
| #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C23_C24_A 0x05cc |
| #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C31_C32_A 0x05cd |
| #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C33_C34_A 0x05ce |
| #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C11_C12_B 0x05cf |
| #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C13_C14_B 0x05d0 |
| #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C21_C22_B 0x05d1 |
| #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C23_C24_B 0x05d2 |
| #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C31_C32_B 0x05d3 |
| #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 |
| #define regMPC_OUT3_CSC_C33_C34_B 0x05d4 |
| #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_mpc_mpc_rmu_dispdec |
| // base address: 0x0 |
| #define regMPC_RMU_CONTROL 0x0680 |
| #define regMPC_RMU_CONTROL_BASE_IDX 3 |
| #define regMPC_RMU_MEM_PWR_CTRL 0x0681 |
| #define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_CONTROL 0x0682 |
| #define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 |
| #define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 |
| #define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 |
| #define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_SCALE_R 0x0686 |
| #define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 |
| #define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 |
| #define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 |
| #define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a |
| #define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d |
| #define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 |
| #define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 |
| #define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 |
| #define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 |
| #define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 |
| #define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_MODE 0x06b9 |
| #define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_INDEX 0x06ba |
| #define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_DATA 0x06bb |
| #define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc |
| #define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd |
| #define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be |
| #define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 |
| #define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_CONTROL 0x06c2 |
| #define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 |
| #define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 |
| #define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 |
| #define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 |
| #define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 |
| #define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 |
| #define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 |
| #define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca |
| #define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd |
| #define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 |
| #define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 |
| #define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 |
| #define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 |
| #define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 |
| #define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_MODE 0x06f9 |
| #define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_INDEX 0x06fa |
| #define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_DATA 0x06fb |
| #define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc |
| #define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd |
| #define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe |
| #define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 |
| #define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_opp_abm0_dispdec |
| // base address: 0x0 |
| #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a |
| #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
| #define regABM0_BL1_PWM_USER_LEVEL 0x0e7b |
| #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
| #define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c |
| #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
| #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d |
| #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
| #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e |
| #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f |
| #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM0_BL1_PWM_ABM_CNTL 0x0e80 |
| #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
| #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 |
| #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 |
| #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
| #define regABM0_DC_ABM1_CNTL 0x0e83 |
| #define regABM0_DC_ABM1_CNTL_BASE_IDX 3 |
| #define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 |
| #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 |
| #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a |
| #define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b |
| #define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
| #define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c |
| #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e |
| #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f |
| #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 |
| #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 |
| #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 |
| #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 |
| #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 |
| #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 |
| #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 |
| #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 |
| #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 |
| #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 |
| #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a |
| #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b |
| #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c |
| #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d |
| #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e |
| #define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f |
| #define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 |
| #define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 |
| #define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 |
| #define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 |
| #define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 |
| #define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 |
| #define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 |
| #define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 |
| #define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 |
| #define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 |
| #define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa |
| #define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_14 0x0eab |
| #define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_15 0x0eac |
| #define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_16 0x0ead |
| #define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_17 0x0eae |
| #define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf |
| #define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 |
| #define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 |
| #define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 |
| #define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 |
| #define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 |
| #define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
| #define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 |
| #define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
| #define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 |
| #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_opp_abm1_dispdec |
| // base address: 0x104 |
| #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb |
| #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
| #define regABM1_BL1_PWM_USER_LEVEL 0x0ebc |
| #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
| #define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd |
| #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
| #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe |
| #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
| #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf |
| #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 |
| #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 |
| #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
| #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 |
| #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 |
| #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
| #define regABM1_DC_ABM1_CNTL 0x0ec4 |
| #define regABM1_DC_ABM1_CNTL_BASE_IDX 3 |
| #define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 |
| #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca |
| #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb |
| #define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc |
| #define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
| #define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd |
| #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf |
| #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 |
| #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 |
| #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 |
| #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 |
| #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 |
| #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 |
| #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 |
| #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 |
| #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 |
| #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 |
| #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda |
| #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb |
| #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc |
| #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd |
| #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede |
| #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_1 0x0edf |
| #define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 |
| #define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 |
| #define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 |
| #define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 |
| #define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 |
| #define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 |
| #define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 |
| #define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 |
| #define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 |
| #define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 |
| #define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_12 0x0eea |
| #define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb |
| #define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_14 0x0eec |
| #define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_15 0x0eed |
| #define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_16 0x0eee |
| #define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_17 0x0eef |
| #define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 |
| #define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 |
| #define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 |
| #define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 |
| #define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 |
| #define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 |
| #define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
| #define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 |
| #define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
| #define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 |
| #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_opp_abm2_dispdec |
| // base address: 0x208 |
| #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc |
| #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
| #define regABM2_BL1_PWM_USER_LEVEL 0x0efd |
| #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
| #define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe |
| #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
| #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff |
| #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
| #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 |
| #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 |
| #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM2_BL1_PWM_ABM_CNTL 0x0f02 |
| #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
| #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 |
| #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 |
| #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
| #define regABM2_DC_ABM1_CNTL 0x0f05 |
| #define regABM2_DC_ABM1_CNTL_BASE_IDX 3 |
| #define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 |
| #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b |
| #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c |
| #define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d |
| #define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
| #define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e |
| #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 |
| #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 |
| #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 |
| #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 |
| #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 |
| #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 |
| #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 |
| #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 |
| #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 |
| #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 |
| #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a |
| #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b |
| #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c |
| #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d |
| #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e |
| #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f |
| #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 |
| #define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 |
| #define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 |
| #define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 |
| #define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 |
| #define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 |
| #define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 |
| #define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 |
| #define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 |
| #define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 |
| #define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a |
| #define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b |
| #define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c |
| #define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d |
| #define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e |
| #define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f |
| #define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 |
| #define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 |
| #define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 |
| #define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 |
| #define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 |
| #define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 |
| #define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 |
| #define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
| #define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 |
| #define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
| #define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 |
| #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_opp_abm3_dispdec |
| // base address: 0x30c |
| #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d |
| #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
| #define regABM3_BL1_PWM_USER_LEVEL 0x0f3e |
| #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
| #define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f |
| #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
| #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 |
| #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
| #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 |
| #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 |
| #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
| #define regABM3_BL1_PWM_ABM_CNTL 0x0f43 |
| #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
| #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 |
| #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 |
| #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
| #define regABM3_DC_ABM1_CNTL 0x0f46 |
| #define regABM3_DC_ABM1_CNTL_BASE_IDX 3 |
| #define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 |
| #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c |
| #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d |
| #define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e |
| #define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
| #define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f |
| #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 |
| #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 |
| #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 |
| #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 |
| #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 |
| #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 |
| #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 |
| #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 |
| #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 |
| #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a |
| #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b |
| #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c |
| #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d |
| #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e |
| #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f |
| #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 |
| #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 |
| #define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 |
| #define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 |
| #define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 |
| #define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 |
| #define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 |
| #define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 |
| #define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 |
| #define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 |
| #define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a |
| #define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b |
| #define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c |
| #define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d |
| #define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e |
| #define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f |
| #define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 |
| #define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 |
| #define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 |
| #define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 |
| #define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 |
| #define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 |
| #define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 |
| #define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 |
| #define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
| #define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 |
| #define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
| #define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 |
| #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_opp_dpg0_dispdec |
| // base address: 0x0 |
| #define regDPG0_DPG_CONTROL 0x1854 |
| #define regDPG0_DPG_CONTROL_BASE_IDX 2 |
| #define regDPG0_DPG_RAMP_CONTROL 0x1855 |
| #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 |
| #define regDPG0_DPG_DIMENSIONS 0x1856 |
| #define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 |
| #define regDPG0_DPG_COLOUR_R_CR 0x1857 |
| #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 |
| #define regDPG0_DPG_COLOUR_G_Y 0x1858 |
| #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 |
| #define regDPG0_DPG_COLOUR_B_CB 0x1859 |
| #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 |
| #define regDPG0_DPG_OFFSET_SEGMENT 0x185a |
| #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
| #define regDPG0_DPG_STATUS 0x185b |
| #define regDPG0_DPG_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_fmt0_dispdec |
| // base address: 0x0 |
| #define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c |
| #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
| #define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d |
| #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
| #define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e |
| #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
| #define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f |
| #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
| #define regFMT0_FMT_CONTROL 0x1840 |
| #define regFMT0_FMT_CONTROL_BASE_IDX 2 |
| #define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 |
| #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
| #define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 |
| #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
| #define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 |
| #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
| #define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 |
| #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
| #define regFMT0_FMT_CLAMP_CNTL 0x1845 |
| #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 |
| #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 |
| #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
| #define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 |
| #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
| #define regFMT0_FMT_422_CONTROL 0x1849 |
| #define regFMT0_FMT_422_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_oppbuf0_dispdec |
| // base address: 0x0 |
| #define regOPPBUF0_OPPBUF_CONTROL 0x1884 |
| #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 |
| #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 |
| #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
| #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 |
| #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
| #define regOPPBUF0_OPPBUF_CONTROL1 0x1889 |
| #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe0_dispdec |
| // base address: 0x0 |
| #define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c |
| #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec |
| // base address: 0x0 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 |
| #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dpg1_dispdec |
| // base address: 0x168 |
| #define regDPG1_DPG_CONTROL 0x18ae |
| #define regDPG1_DPG_CONTROL_BASE_IDX 2 |
| #define regDPG1_DPG_RAMP_CONTROL 0x18af |
| #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 |
| #define regDPG1_DPG_DIMENSIONS 0x18b0 |
| #define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 |
| #define regDPG1_DPG_COLOUR_R_CR 0x18b1 |
| #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 |
| #define regDPG1_DPG_COLOUR_G_Y 0x18b2 |
| #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 |
| #define regDPG1_DPG_COLOUR_B_CB 0x18b3 |
| #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 |
| #define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 |
| #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
| #define regDPG1_DPG_STATUS 0x18b5 |
| #define regDPG1_DPG_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_fmt1_dispdec |
| // base address: 0x168 |
| #define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 |
| #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
| #define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 |
| #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
| #define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 |
| #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
| #define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 |
| #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
| #define regFMT1_FMT_CONTROL 0x189a |
| #define regFMT1_FMT_CONTROL_BASE_IDX 2 |
| #define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b |
| #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
| #define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c |
| #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
| #define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d |
| #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
| #define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e |
| #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
| #define regFMT1_FMT_CLAMP_CNTL 0x189f |
| #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 |
| #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 |
| #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
| #define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 |
| #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
| #define regFMT1_FMT_422_CONTROL 0x18a3 |
| #define regFMT1_FMT_422_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_oppbuf1_dispdec |
| // base address: 0x168 |
| #define regOPPBUF1_OPPBUF_CONTROL 0x18de |
| #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 |
| #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df |
| #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
| #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 |
| #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
| #define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 |
| #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe1_dispdec |
| // base address: 0x168 |
| #define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 |
| #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec |
| // base address: 0x168 |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef |
| #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dpg2_dispdec |
| // base address: 0x2d0 |
| #define regDPG2_DPG_CONTROL 0x1908 |
| #define regDPG2_DPG_CONTROL_BASE_IDX 2 |
| #define regDPG2_DPG_RAMP_CONTROL 0x1909 |
| #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 |
| #define regDPG2_DPG_DIMENSIONS 0x190a |
| #define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 |
| #define regDPG2_DPG_COLOUR_R_CR 0x190b |
| #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 |
| #define regDPG2_DPG_COLOUR_G_Y 0x190c |
| #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 |
| #define regDPG2_DPG_COLOUR_B_CB 0x190d |
| #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 |
| #define regDPG2_DPG_OFFSET_SEGMENT 0x190e |
| #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
| #define regDPG2_DPG_STATUS 0x190f |
| #define regDPG2_DPG_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_fmt2_dispdec |
| // base address: 0x2d0 |
| #define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 |
| #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
| #define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 |
| #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
| #define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 |
| #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
| #define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 |
| #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
| #define regFMT2_FMT_CONTROL 0x18f4 |
| #define regFMT2_FMT_CONTROL_BASE_IDX 2 |
| #define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 |
| #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
| #define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 |
| #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
| #define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 |
| #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
| #define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 |
| #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
| #define regFMT2_FMT_CLAMP_CNTL 0x18f9 |
| #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 |
| #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa |
| #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
| #define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb |
| #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
| #define regFMT2_FMT_422_CONTROL 0x18fd |
| #define regFMT2_FMT_422_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_oppbuf2_dispdec |
| // base address: 0x2d0 |
| #define regOPPBUF2_OPPBUF_CONTROL 0x1938 |
| #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 |
| #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 |
| #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
| #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a |
| #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
| #define regOPPBUF2_OPPBUF_CONTROL1 0x193d |
| #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe2_dispdec |
| // base address: 0x2d0 |
| #define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 |
| #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec |
| // base address: 0x2d0 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 |
| #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dpg3_dispdec |
| // base address: 0x438 |
| #define regDPG3_DPG_CONTROL 0x1962 |
| #define regDPG3_DPG_CONTROL_BASE_IDX 2 |
| #define regDPG3_DPG_RAMP_CONTROL 0x1963 |
| #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 |
| #define regDPG3_DPG_DIMENSIONS 0x1964 |
| #define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 |
| #define regDPG3_DPG_COLOUR_R_CR 0x1965 |
| #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 |
| #define regDPG3_DPG_COLOUR_G_Y 0x1966 |
| #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 |
| #define regDPG3_DPG_COLOUR_B_CB 0x1967 |
| #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 |
| #define regDPG3_DPG_OFFSET_SEGMENT 0x1968 |
| #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
| #define regDPG3_DPG_STATUS 0x1969 |
| #define regDPG3_DPG_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_fmt3_dispdec |
| // base address: 0x438 |
| #define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a |
| #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
| #define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b |
| #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
| #define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c |
| #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
| #define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d |
| #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
| #define regFMT3_FMT_CONTROL 0x194e |
| #define regFMT3_FMT_CONTROL_BASE_IDX 2 |
| #define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f |
| #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
| #define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 |
| #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
| #define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 |
| #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
| #define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 |
| #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
| #define regFMT3_FMT_CLAMP_CNTL 0x1953 |
| #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 |
| #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 |
| #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
| #define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 |
| #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
| #define regFMT3_FMT_422_CONTROL 0x1957 |
| #define regFMT3_FMT_422_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_oppbuf3_dispdec |
| // base address: 0x438 |
| #define regOPPBUF3_OPPBUF_CONTROL 0x1992 |
| #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 |
| #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 |
| #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
| #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 |
| #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
| #define regOPPBUF3_OPPBUF_CONTROL1 0x1997 |
| #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe3_dispdec |
| // base address: 0x438 |
| #define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a |
| #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec |
| // base address: 0x438 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 |
| #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dscrm0_dispdec |
| // base address: 0x0 |
| #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 |
| #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dscrm1_dispdec |
| // base address: 0x4 |
| #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 |
| #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_dscrm2_dispdec |
| // base address: 0x8 |
| #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 |
| #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_top_dispdec |
| // base address: 0x0 |
| #define regOPP_TOP_CLK_CONTROL 0x1a5e |
| #define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 |
| #define regOPP_ABM_CONTROL 0x1a60 |
| #define regOPP_ABM_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x6af8 |
| #define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe |
| #define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf |
| #define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 |
| #define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 |
| #define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 |
| #define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 |
| #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 |
| #define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_HI 0x1ac5 |
| #define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON16_PERFMON_LOW 0x1ac6 |
| #define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_odm0_dispdec |
| // base address: 0x0 |
| #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca |
| #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
| #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb |
| #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
| #define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc |
| #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
| #define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd |
| #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regODM0_OPTC_WIDTH_CONTROL 0x1ace |
| #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
| #define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf |
| #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
| #define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 |
| #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
| #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 |
| #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_odm1_dispdec |
| // base address: 0x40 |
| #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada |
| #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
| #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb |
| #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
| #define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc |
| #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
| #define regODM1_OPTC_BYTES_PER_PIXEL 0x1add |
| #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regODM1_OPTC_WIDTH_CONTROL 0x1ade |
| #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
| #define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf |
| #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
| #define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 |
| #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
| #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 |
| #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_odm2_dispdec |
| // base address: 0x80 |
| #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea |
| #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
| #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb |
| #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
| #define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec |
| #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
| #define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed |
| #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regODM2_OPTC_WIDTH_CONTROL 0x1aee |
| #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
| #define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef |
| #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
| #define regODM2_OPTC_MEMORY_CONFIG 0x1af0 |
| #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
| #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 |
| #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_odm3_dispdec |
| // base address: 0xc0 |
| #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa |
| #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
| #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb |
| #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
| #define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc |
| #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
| #define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd |
| #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regODM3_OPTC_WIDTH_CONTROL 0x1afe |
| #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
| #define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff |
| #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
| #define regODM3_OPTC_MEMORY_CONFIG 0x1b00 |
| #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
| #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 |
| #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_otg0_dispdec |
| // base address: 0x0 |
| #define regOTG0_OTG_H_TOTAL 0x1b2a |
| #define regOTG0_OTG_H_TOTAL_BASE_IDX 2 |
| #define regOTG0_OTG_H_BLANK_START_END 0x1b2b |
| #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 |
| #define regOTG0_OTG_H_SYNC_A 0x1b2c |
| #define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 |
| #define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d |
| #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_H_TIMING_CNTL 0x1b2e |
| #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL 0x1b2f |
| #define regOTG0_OTG_V_TOTAL_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL_MIN 0x1b30 |
| #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL_MAX 0x1b31 |
| #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL_MID 0x1b32 |
| #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 |
| #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 |
| #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 |
| #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_V_BLANK_START_END 0x1b36 |
| #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 |
| #define regOTG0_OTG_V_SYNC_A 0x1b37 |
| #define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 |
| #define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 |
| #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_TRIGA_CNTL 0x1b39 |
| #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a |
| #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG0_OTG_TRIGB_CNTL 0x1b3b |
| #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c |
| #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d |
| #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_FLOW_CONTROL 0x1b3e |
| #define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f |
| #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
| #define regOTG0_OTG_CONTROL 0x1b41 |
| #define regOTG0_OTG_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 |
| #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_INTERLACE_STATUS 0x1b45 |
| #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 |
| #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
| #define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 |
| #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
| #define regOTG0_OTG_STATUS 0x1b49 |
| #define regOTG0_OTG_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_STATUS_POSITION 0x1b4a |
| #define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b |
| #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c |
| #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
| #define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d |
| #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
| #define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e |
| #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
| #define regOTG0_OTG_COUNT_CONTROL 0x1b4f |
| #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_COUNT_RESET 0x1b50 |
| #define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 |
| #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 |
| #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
| #define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 |
| #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_STEREO_STATUS 0x1b53 |
| #define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_STEREO_CONTROL 0x1b54 |
| #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 |
| #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 |
| #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 |
| #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 |
| #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
| #define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 |
| #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_UPDATE_LOCK 0x1b5a |
| #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b |
| #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_MASTER_EN 0x1b5c |
| #define regOTG0_OTG_MASTER_EN_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 |
| #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC_CNTL 0x1b68 |
| #define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC_CNTL2 0x1b69 |
| #define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a |
| #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b |
| #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c |
| #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d |
| #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_DATA_RG 0x1b6e |
| #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 |
| #define regOTG0_OTG_CRC0_DATA_B 0x1b6f |
| #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 |
| #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 |
| #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 |
| #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 |
| #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_DATA_RG 0x1b74 |
| #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 |
| #define regOTG0_OTG_CRC1_DATA_B 0x1b75 |
| #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 |
| #define regOTG0_OTG_CRC2_DATA_RG 0x1b76 |
| #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 |
| #define regOTG0_OTG_CRC2_DATA_B 0x1b77 |
| #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 |
| #define regOTG0_OTG_CRC3_DATA_RG 0x1b78 |
| #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 |
| #define regOTG0_OTG_CRC3_DATA_B 0x1b79 |
| #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 |
| #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a |
| #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
| #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b |
| #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
| #define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 |
| #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 |
| #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 |
| #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
| #define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 |
| #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
| #define regOTG0_OTG_CLOCK_CONTROL 0x1b86 |
| #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 |
| #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
| #define regOTG0_OTG_VUPDATE_PARAM 0x1b88 |
| #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 |
| #define regOTG0_OTG_VREADY_PARAM 0x1b89 |
| #define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a |
| #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b |
| #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG0_OTG_GSL_CONTROL 0x1b8c |
| #define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_GSL_WINDOW_X 0x1b8d |
| #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 |
| #define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e |
| #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
| #define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f |
| #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 |
| #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 |
| #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 |
| #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 |
| #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
| #define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 |
| #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
| #define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 |
| #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 |
| #define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 |
| #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 |
| #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
| #define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 |
| #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
| #define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a |
| #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
| #define regOTG0_OTG_DRR_CONTROL 0x1b9b |
| #define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_M_CONST_DTO0 0x1b9c |
| #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 |
| #define regOTG0_OTG_M_CONST_DTO1 0x1b9d |
| #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 |
| #define regOTG0_OTG_REQUEST_CONTROL 0x1b9e |
| #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 |
| #define regOTG0_OTG_DSC_START_POSITION 0x1b9f |
| #define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 |
| #define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 |
| #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
| #define regOTG0_OTG_SPARE_REGISTER 0x1ba2 |
| #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_otg1_dispdec |
| // base address: 0x200 |
| #define regOTG1_OTG_H_TOTAL 0x1baa |
| #define regOTG1_OTG_H_TOTAL_BASE_IDX 2 |
| #define regOTG1_OTG_H_BLANK_START_END 0x1bab |
| #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 |
| #define regOTG1_OTG_H_SYNC_A 0x1bac |
| #define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 |
| #define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad |
| #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_H_TIMING_CNTL 0x1bae |
| #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL 0x1baf |
| #define regOTG1_OTG_V_TOTAL_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 |
| #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 |
| #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL_MID 0x1bb2 |
| #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 |
| #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 |
| #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 |
| #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_V_BLANK_START_END 0x1bb6 |
| #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 |
| #define regOTG1_OTG_V_SYNC_A 0x1bb7 |
| #define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 |
| #define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 |
| #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_TRIGA_CNTL 0x1bb9 |
| #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba |
| #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG1_OTG_TRIGB_CNTL 0x1bbb |
| #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc |
| #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd |
| #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_FLOW_CONTROL 0x1bbe |
| #define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf |
| #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
| #define regOTG1_OTG_CONTROL 0x1bc1 |
| #define regOTG1_OTG_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 |
| #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 |
| #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 |
| #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
| #define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 |
| #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
| #define regOTG1_OTG_STATUS 0x1bc9 |
| #define regOTG1_OTG_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_STATUS_POSITION 0x1bca |
| #define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb |
| #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc |
| #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
| #define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd |
| #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
| #define regOTG1_OTG_STATUS_HV_COUNT 0x1bce |
| #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
| #define regOTG1_OTG_COUNT_CONTROL 0x1bcf |
| #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_COUNT_RESET 0x1bd0 |
| #define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 |
| #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 |
| #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
| #define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 |
| #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_STEREO_STATUS 0x1bd3 |
| #define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_STEREO_CONTROL 0x1bd4 |
| #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 |
| #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 |
| #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 |
| #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 |
| #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
| #define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 |
| #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_UPDATE_LOCK 0x1bda |
| #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb |
| #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_MASTER_EN 0x1bdc |
| #define regOTG1_OTG_MASTER_EN_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 |
| #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC_CNTL 0x1be8 |
| #define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC_CNTL2 0x1be9 |
| #define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea |
| #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb |
| #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec |
| #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed |
| #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_DATA_RG 0x1bee |
| #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 |
| #define regOTG1_OTG_CRC0_DATA_B 0x1bef |
| #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 |
| #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 |
| #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 |
| #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 |
| #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 |
| #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 |
| #define regOTG1_OTG_CRC1_DATA_B 0x1bf5 |
| #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 |
| #define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 |
| #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 |
| #define regOTG1_OTG_CRC2_DATA_B 0x1bf7 |
| #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 |
| #define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 |
| #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 |
| #define regOTG1_OTG_CRC3_DATA_B 0x1bf9 |
| #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 |
| #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa |
| #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
| #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb |
| #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
| #define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 |
| #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 |
| #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 |
| #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
| #define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 |
| #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
| #define regOTG1_OTG_CLOCK_CONTROL 0x1c06 |
| #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 |
| #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
| #define regOTG1_OTG_VUPDATE_PARAM 0x1c08 |
| #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 |
| #define regOTG1_OTG_VREADY_PARAM 0x1c09 |
| #define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a |
| #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b |
| #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG1_OTG_GSL_CONTROL 0x1c0c |
| #define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_GSL_WINDOW_X 0x1c0d |
| #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 |
| #define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e |
| #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
| #define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f |
| #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 |
| #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 |
| #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 |
| #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 |
| #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
| #define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 |
| #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
| #define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 |
| #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 |
| #define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 |
| #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 |
| #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
| #define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 |
| #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
| #define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a |
| #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
| #define regOTG1_OTG_DRR_CONTROL 0x1c1b |
| #define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_M_CONST_DTO0 0x1c1c |
| #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 |
| #define regOTG1_OTG_M_CONST_DTO1 0x1c1d |
| #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 |
| #define regOTG1_OTG_REQUEST_CONTROL 0x1c1e |
| #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 |
| #define regOTG1_OTG_DSC_START_POSITION 0x1c1f |
| #define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 |
| #define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 |
| #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
| #define regOTG1_OTG_SPARE_REGISTER 0x1c22 |
| #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_otg2_dispdec |
| // base address: 0x400 |
| #define regOTG2_OTG_H_TOTAL 0x1c2a |
| #define regOTG2_OTG_H_TOTAL_BASE_IDX 2 |
| #define regOTG2_OTG_H_BLANK_START_END 0x1c2b |
| #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 |
| #define regOTG2_OTG_H_SYNC_A 0x1c2c |
| #define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 |
| #define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d |
| #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_H_TIMING_CNTL 0x1c2e |
| #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL 0x1c2f |
| #define regOTG2_OTG_V_TOTAL_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL_MIN 0x1c30 |
| #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL_MAX 0x1c31 |
| #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL_MID 0x1c32 |
| #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 |
| #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 |
| #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 |
| #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_V_BLANK_START_END 0x1c36 |
| #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 |
| #define regOTG2_OTG_V_SYNC_A 0x1c37 |
| #define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 |
| #define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 |
| #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_TRIGA_CNTL 0x1c39 |
| #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a |
| #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG2_OTG_TRIGB_CNTL 0x1c3b |
| #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c |
| #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d |
| #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_FLOW_CONTROL 0x1c3e |
| #define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f |
| #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
| #define regOTG2_OTG_CONTROL 0x1c41 |
| #define regOTG2_OTG_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 |
| #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_INTERLACE_STATUS 0x1c45 |
| #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 |
| #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
| #define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 |
| #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
| #define regOTG2_OTG_STATUS 0x1c49 |
| #define regOTG2_OTG_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_STATUS_POSITION 0x1c4a |
| #define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b |
| #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c |
| #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
| #define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d |
| #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
| #define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e |
| #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
| #define regOTG2_OTG_COUNT_CONTROL 0x1c4f |
| #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_COUNT_RESET 0x1c50 |
| #define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 |
| #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 |
| #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
| #define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 |
| #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_STEREO_STATUS 0x1c53 |
| #define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_STEREO_CONTROL 0x1c54 |
| #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 |
| #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 |
| #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 |
| #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 |
| #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
| #define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 |
| #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_UPDATE_LOCK 0x1c5a |
| #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b |
| #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_MASTER_EN 0x1c5c |
| #define regOTG2_OTG_MASTER_EN_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 |
| #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC_CNTL 0x1c68 |
| #define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC_CNTL2 0x1c69 |
| #define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a |
| #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b |
| #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c |
| #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d |
| #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_DATA_RG 0x1c6e |
| #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 |
| #define regOTG2_OTG_CRC0_DATA_B 0x1c6f |
| #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 |
| #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 |
| #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 |
| #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 |
| #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_DATA_RG 0x1c74 |
| #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 |
| #define regOTG2_OTG_CRC1_DATA_B 0x1c75 |
| #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 |
| #define regOTG2_OTG_CRC2_DATA_RG 0x1c76 |
| #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 |
| #define regOTG2_OTG_CRC2_DATA_B 0x1c77 |
| #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 |
| #define regOTG2_OTG_CRC3_DATA_RG 0x1c78 |
| #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 |
| #define regOTG2_OTG_CRC3_DATA_B 0x1c79 |
| #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 |
| #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a |
| #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
| #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b |
| #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
| #define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 |
| #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 |
| #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 |
| #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
| #define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 |
| #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
| #define regOTG2_OTG_CLOCK_CONTROL 0x1c86 |
| #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 |
| #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
| #define regOTG2_OTG_VUPDATE_PARAM 0x1c88 |
| #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 |
| #define regOTG2_OTG_VREADY_PARAM 0x1c89 |
| #define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a |
| #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b |
| #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG2_OTG_GSL_CONTROL 0x1c8c |
| #define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_GSL_WINDOW_X 0x1c8d |
| #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 |
| #define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e |
| #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
| #define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f |
| #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 |
| #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 |
| #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 |
| #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 |
| #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
| #define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 |
| #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
| #define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 |
| #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 |
| #define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 |
| #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 |
| #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
| #define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 |
| #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
| #define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a |
| #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
| #define regOTG2_OTG_DRR_CONTROL 0x1c9b |
| #define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_M_CONST_DTO0 0x1c9c |
| #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 |
| #define regOTG2_OTG_M_CONST_DTO1 0x1c9d |
| #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 |
| #define regOTG2_OTG_REQUEST_CONTROL 0x1c9e |
| #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 |
| #define regOTG2_OTG_DSC_START_POSITION 0x1c9f |
| #define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 |
| #define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 |
| #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
| #define regOTG2_OTG_SPARE_REGISTER 0x1ca2 |
| #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_otg3_dispdec |
| // base address: 0x600 |
| #define regOTG3_OTG_H_TOTAL 0x1caa |
| #define regOTG3_OTG_H_TOTAL_BASE_IDX 2 |
| #define regOTG3_OTG_H_BLANK_START_END 0x1cab |
| #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 |
| #define regOTG3_OTG_H_SYNC_A 0x1cac |
| #define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 |
| #define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad |
| #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_H_TIMING_CNTL 0x1cae |
| #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL 0x1caf |
| #define regOTG3_OTG_V_TOTAL_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 |
| #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 |
| #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL_MID 0x1cb2 |
| #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 |
| #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 |
| #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 |
| #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_V_BLANK_START_END 0x1cb6 |
| #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 |
| #define regOTG3_OTG_V_SYNC_A 0x1cb7 |
| #define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 |
| #define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 |
| #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_TRIGA_CNTL 0x1cb9 |
| #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba |
| #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG3_OTG_TRIGB_CNTL 0x1cbb |
| #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc |
| #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
| #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd |
| #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_FLOW_CONTROL 0x1cbe |
| #define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf |
| #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
| #define regOTG3_OTG_CONTROL 0x1cc1 |
| #define regOTG3_OTG_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 |
| #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 |
| #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 |
| #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
| #define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 |
| #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
| #define regOTG3_OTG_STATUS 0x1cc9 |
| #define regOTG3_OTG_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_STATUS_POSITION 0x1cca |
| #define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb |
| #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc |
| #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
| #define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd |
| #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
| #define regOTG3_OTG_STATUS_HV_COUNT 0x1cce |
| #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
| #define regOTG3_OTG_COUNT_CONTROL 0x1ccf |
| #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_COUNT_RESET 0x1cd0 |
| #define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 |
| #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 |
| #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
| #define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 |
| #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_STEREO_STATUS 0x1cd3 |
| #define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_STEREO_CONTROL 0x1cd4 |
| #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 |
| #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 |
| #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 |
| #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 |
| #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
| #define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 |
| #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_UPDATE_LOCK 0x1cda |
| #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb |
| #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_MASTER_EN 0x1cdc |
| #define regOTG3_OTG_MASTER_EN_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 |
| #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC_CNTL 0x1ce8 |
| #define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC_CNTL2 0x1ce9 |
| #define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea |
| #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb |
| #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec |
| #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced |
| #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_DATA_RG 0x1cee |
| #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 |
| #define regOTG3_OTG_CRC0_DATA_B 0x1cef |
| #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 |
| #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 |
| #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 |
| #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 |
| #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 |
| #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 |
| #define regOTG3_OTG_CRC1_DATA_B 0x1cf5 |
| #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 |
| #define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 |
| #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 |
| #define regOTG3_OTG_CRC2_DATA_B 0x1cf7 |
| #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 |
| #define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 |
| #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 |
| #define regOTG3_OTG_CRC3_DATA_B 0x1cf9 |
| #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 |
| #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa |
| #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
| #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb |
| #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
| #define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 |
| #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 |
| #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 |
| #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
| #define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 |
| #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
| #define regOTG3_OTG_CLOCK_CONTROL 0x1d06 |
| #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 |
| #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
| #define regOTG3_OTG_VUPDATE_PARAM 0x1d08 |
| #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 |
| #define regOTG3_OTG_VREADY_PARAM 0x1d09 |
| #define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a |
| #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b |
| #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
| #define regOTG3_OTG_GSL_CONTROL 0x1d0c |
| #define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_GSL_WINDOW_X 0x1d0d |
| #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 |
| #define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e |
| #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
| #define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f |
| #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 |
| #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 |
| #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 |
| #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 |
| #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
| #define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 |
| #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
| #define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 |
| #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 |
| #define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 |
| #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 |
| #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
| #define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 |
| #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
| #define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a |
| #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
| #define regOTG3_OTG_DRR_CONTROL 0x1d1b |
| #define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_M_CONST_DTO0 0x1d1c |
| #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 |
| #define regOTG3_OTG_M_CONST_DTO1 0x1d1d |
| #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 |
| #define regOTG3_OTG_REQUEST_CONTROL 0x1d1e |
| #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 |
| #define regOTG3_OTG_DSC_START_POSITION 0x1d1f |
| #define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 |
| #define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 |
| #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
| #define regOTG3_OTG_SPARE_REGISTER 0x1d22 |
| #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_optc_misc_dispdec |
| // base address: 0x0 |
| #define regDWB_SOURCE_SELECT 0x1e2a |
| #define regDWB_SOURCE_SELECT_BASE_IDX 2 |
| #define regGSL_SOURCE_SELECT 0x1e2b |
| #define regGSL_SOURCE_SELECT_BASE_IDX 2 |
| #define regOPTC_CLOCK_CONTROL 0x1e2c |
| #define regOPTC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regODM_MEM_PWR_CTRL 0x1e2d |
| #define regODM_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regODM_MEM_PWR_CTRL3 0x1e2f |
| #define regODM_MEM_PWR_CTRL3_BASE_IDX 2 |
| #define regODM_MEM_PWR_STATUS 0x1e30 |
| #define regODM_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regOPTC_MISC_SPARE_REGISTER 0x1e31 |
| #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x79a8 |
| #define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a |
| #define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b |
| #define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c |
| #define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_CNTL 0x1e6d |
| #define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e |
| #define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f |
| #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 |
| #define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_HI 0x1e71 |
| #define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON17_PERFMON_LOW 0x1e72 |
| #define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_hpd0_dispdec |
| // base address: 0x0 |
| #define regHPD0_DC_HPD_INT_STATUS 0x1f14 |
| #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 |
| #define regHPD0_DC_HPD_INT_CONTROL 0x1f15 |
| #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 |
| #define regHPD0_DC_HPD_CONTROL 0x1f16 |
| #define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 |
| #define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 |
| #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
| #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 |
| #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_hpd1_dispdec |
| // base address: 0x20 |
| #define regHPD1_DC_HPD_INT_STATUS 0x1f1c |
| #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 |
| #define regHPD1_DC_HPD_INT_CONTROL 0x1f1d |
| #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 |
| #define regHPD1_DC_HPD_CONTROL 0x1f1e |
| #define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 |
| #define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f |
| #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
| #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 |
| #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_hpd2_dispdec |
| // base address: 0x40 |
| #define regHPD2_DC_HPD_INT_STATUS 0x1f24 |
| #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 |
| #define regHPD2_DC_HPD_INT_CONTROL 0x1f25 |
| #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 |
| #define regHPD2_DC_HPD_CONTROL 0x1f26 |
| #define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 |
| #define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 |
| #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
| #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 |
| #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_hpd3_dispdec |
| // base address: 0x60 |
| #define regHPD3_DC_HPD_INT_STATUS 0x1f2c |
| #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 |
| #define regHPD3_DC_HPD_INT_CONTROL 0x1f2d |
| #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 |
| #define regHPD3_DC_HPD_CONTROL 0x1f2e |
| #define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 |
| #define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f |
| #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
| #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 |
| #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_hpd4_dispdec |
| // base address: 0x80 |
| #define regHPD4_DC_HPD_INT_STATUS 0x1f34 |
| #define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 |
| #define regHPD4_DC_HPD_INT_CONTROL 0x1f35 |
| #define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 |
| #define regHPD4_DC_HPD_CONTROL 0x1f36 |
| #define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 |
| #define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 |
| #define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
| #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 |
| #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp0_dispdec |
| // base address: 0x0 |
| #define regDP0_DP_LINK_CNTL 0x2108 |
| #define regDP0_DP_LINK_CNTL_BASE_IDX 2 |
| #define regDP0_DP_PIXEL_FORMAT 0x2109 |
| #define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP0_DP_MSA_COLORIMETRY 0x210a |
| #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 |
| #define regDP0_DP_CONFIG 0x210b |
| #define regDP0_DP_CONFIG_BASE_IDX 2 |
| #define regDP0_DP_VID_STREAM_CNTL 0x210c |
| #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 |
| #define regDP0_DP_STEER_FIFO 0x210d |
| #define regDP0_DP_STEER_FIFO_BASE_IDX 2 |
| #define regDP0_DP_MSA_MISC 0x210e |
| #define regDP0_DP_MSA_MISC_BASE_IDX 2 |
| #define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f |
| #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
| #define regDP0_DP_VID_TIMING 0x2110 |
| #define regDP0_DP_VID_TIMING_BASE_IDX 2 |
| #define regDP0_DP_VID_N 0x2111 |
| #define regDP0_DP_VID_N_BASE_IDX 2 |
| #define regDP0_DP_VID_M 0x2112 |
| #define regDP0_DP_VID_M_BASE_IDX 2 |
| #define regDP0_DP_LINK_FRAMING_CNTL 0x2113 |
| #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
| #define regDP0_DP_HBR2_EYE_PATTERN 0x2114 |
| #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
| #define regDP0_DP_VID_MSA_VBID 0x2115 |
| #define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 |
| #define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 |
| #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CNTL 0x2117 |
| #define regDP0_DP_DPHY_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 |
| #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_SYM0 0x2119 |
| #define regDP0_DP_DPHY_SYM0_BASE_IDX 2 |
| #define regDP0_DP_DPHY_SYM1 0x211a |
| #define regDP0_DP_DPHY_SYM1_BASE_IDX 2 |
| #define regDP0_DP_DPHY_SYM2 0x211b |
| #define regDP0_DP_DPHY_SYM2_BASE_IDX 2 |
| #define regDP0_DP_DPHY_8B10B_CNTL 0x211c |
| #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_PRBS_CNTL 0x211d |
| #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_SCRAM_CNTL 0x211e |
| #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CRC_EN 0x211f |
| #define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CRC_CNTL 0x2120 |
| #define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CRC_RESULT 0x2121 |
| #define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 |
| #define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 |
| #define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
| #define regDP0_DP_DPHY_FAST_TRAINING 0x2124 |
| #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
| #define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 |
| #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL 0x212b |
| #define regDP0_DP_SEC_CNTL_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL1 0x212c |
| #define regDP0_DP_SEC_CNTL1_BASE_IDX 2 |
| #define regDP0_DP_SEC_FRAMING1 0x212d |
| #define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 |
| #define regDP0_DP_SEC_FRAMING2 0x212e |
| #define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 |
| #define regDP0_DP_SEC_FRAMING3 0x212f |
| #define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 |
| #define regDP0_DP_SEC_FRAMING4 0x2130 |
| #define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 |
| #define regDP0_DP_SEC_AUD_N 0x2131 |
| #define regDP0_DP_SEC_AUD_N_BASE_IDX 2 |
| #define regDP0_DP_SEC_AUD_N_READBACK 0x2132 |
| #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
| #define regDP0_DP_SEC_AUD_M 0x2133 |
| #define regDP0_DP_SEC_AUD_M_BASE_IDX 2 |
| #define regDP0_DP_SEC_AUD_M_READBACK 0x2134 |
| #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
| #define regDP0_DP_SEC_TIMESTAMP 0x2135 |
| #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 |
| #define regDP0_DP_SEC_PACKET_CNTL 0x2136 |
| #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
| #define regDP0_DP_MSE_RATE_CNTL 0x2137 |
| #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 |
| #define regDP0_DP_MSE_RATE_UPDATE 0x2139 |
| #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT0 0x213a |
| #define regDP0_DP_MSE_SAT0_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT1 0x213b |
| #define regDP0_DP_MSE_SAT1_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT2 0x213c |
| #define regDP0_DP_MSE_SAT2_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT_UPDATE 0x213d |
| #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
| #define regDP0_DP_MSE_LINK_TIMING 0x213e |
| #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 |
| #define regDP0_DP_MSE_MISC_CNTL 0x213f |
| #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 |
| #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
| #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 |
| #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT0_STATUS 0x2147 |
| #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT1_STATUS 0x2148 |
| #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
| #define regDP0_DP_MSE_SAT2_STATUS 0x2149 |
| #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
| #define regDP0_DP_MSA_TIMING_PARAM1 0x214c |
| #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
| #define regDP0_DP_MSA_TIMING_PARAM2 0x214d |
| #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
| #define regDP0_DP_MSA_TIMING_PARAM3 0x214e |
| #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
| #define regDP0_DP_MSA_TIMING_PARAM4 0x214f |
| #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
| #define regDP0_DP_MSO_CNTL 0x2150 |
| #define regDP0_DP_MSO_CNTL_BASE_IDX 2 |
| #define regDP0_DP_MSO_CNTL1 0x2151 |
| #define regDP0_DP_MSO_CNTL1_BASE_IDX 2 |
| #define regDP0_DP_DSC_CNTL 0x2152 |
| #define regDP0_DP_DSC_CNTL_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL2 0x2153 |
| #define regDP0_DP_SEC_CNTL2_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL3 0x2154 |
| #define regDP0_DP_SEC_CNTL3_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL4 0x2155 |
| #define regDP0_DP_SEC_CNTL4_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL5 0x2156 |
| #define regDP0_DP_SEC_CNTL5_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL6 0x2157 |
| #define regDP0_DP_SEC_CNTL6_BASE_IDX 2 |
| #define regDP0_DP_SEC_CNTL7 0x2158 |
| #define regDP0_DP_SEC_CNTL7_BASE_IDX 2 |
| #define regDP0_DP_DB_CNTL 0x2159 |
| #define regDP0_DP_DB_CNTL_BASE_IDX 2 |
| #define regDP0_DP_MSA_VBID_MISC 0x215a |
| #define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 |
| #define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b |
| #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
| #define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c |
| #define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regDP0_DP_ALPM_CNTL 0x215d |
| #define regDP0_DP_ALPM_CNTL_BASE_IDX 2 |
| #define regDP0_DP_GSP8_CNTL 0x215e |
| #define regDP0_DP_GSP8_CNTL_BASE_IDX 2 |
| #define regDP0_DP_GSP9_CNTL 0x215f |
| #define regDP0_DP_GSP9_CNTL_BASE_IDX 2 |
| #define regDP0_DP_GSP10_CNTL 0x2160 |
| #define regDP0_DP_GSP10_CNTL_BASE_IDX 2 |
| #define regDP0_DP_GSP11_CNTL 0x2161 |
| #define regDP0_DP_GSP11_CNTL_BASE_IDX 2 |
| #define regDP0_DP_GSP_EN_DB_STATUS 0x2162 |
| #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig0_dispdec |
| // base address: 0x0 |
| #define regDIG0_DIG_FE_CNTL 0x208b |
| #define regDIG0_DIG_FE_CNTL_BASE_IDX 2 |
| #define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c |
| #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
| #define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d |
| #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
| #define regDIG0_DIG_CLOCK_PATTERN 0x208e |
| #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 |
| #define regDIG0_DIG_TEST_PATTERN 0x208f |
| #define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 |
| #define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 |
| #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
| #define regDIG0_DIG_FIFO_STATUS 0x2091 |
| #define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 |
| #define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 |
| #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_CONTROL 0x2093 |
| #define regDIG0_HDMI_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_STATUS 0x2094 |
| #define regDIG0_HDMI_STATUS_BASE_IDX 2 |
| #define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 |
| #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 |
| #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 |
| #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 |
| #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 |
| #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
| #define regDIG0_HDMI_GC 0x209d |
| #define regDIG0_HDMI_GC_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 |
| #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
| #define regDIG0_HDMI_DB_CONTROL 0x20a6 |
| #define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_32_0 0x20a7 |
| #define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_32_1 0x20a8 |
| #define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_44_0 0x20a9 |
| #define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_44_1 0x20aa |
| #define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_48_0 0x20ab |
| #define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_48_1 0x20ac |
| #define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_STATUS_0 0x20ad |
| #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 |
| #define regDIG0_HDMI_ACR_STATUS_1 0x20ae |
| #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 |
| #define regDIG0_AFMT_CNTL 0x20af |
| #define regDIG0_AFMT_CNTL_BASE_IDX 2 |
| #define regDIG0_DIG_BE_CNTL 0x20b0 |
| #define regDIG0_DIG_BE_CNTL_BASE_IDX 2 |
| #define regDIG0_DIG_BE_EN_CNTL 0x20b1 |
| #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 |
| #define regDIG0_TMDS_CNTL 0x20d7 |
| #define regDIG0_TMDS_CNTL_BASE_IDX 2 |
| #define regDIG0_TMDS_CONTROL_CHAR 0x20d8 |
| #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 |
| #define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 |
| #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
| #define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da |
| #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
| #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db |
| #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
| #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc |
| #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
| #define regDIG0_TMDS_CTL_BITS 0x20de |
| #define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 |
| #define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df |
| #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
| #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 |
| #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
| #define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 |
| #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
| #define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 |
| #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
| #define regDIG0_DIG_VERSION 0x20e4 |
| #define regDIG0_DIG_VERSION_BASE_IDX 2 |
| #define regDIG0_FORCE_DIG_DISABLE 0x20e5 |
| #define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp1_dispdec |
| // base address: 0x400 |
| #define regDP1_DP_LINK_CNTL 0x2208 |
| #define regDP1_DP_LINK_CNTL_BASE_IDX 2 |
| #define regDP1_DP_PIXEL_FORMAT 0x2209 |
| #define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP1_DP_MSA_COLORIMETRY 0x220a |
| #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 |
| #define regDP1_DP_CONFIG 0x220b |
| #define regDP1_DP_CONFIG_BASE_IDX 2 |
| #define regDP1_DP_VID_STREAM_CNTL 0x220c |
| #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 |
| #define regDP1_DP_STEER_FIFO 0x220d |
| #define regDP1_DP_STEER_FIFO_BASE_IDX 2 |
| #define regDP1_DP_MSA_MISC 0x220e |
| #define regDP1_DP_MSA_MISC_BASE_IDX 2 |
| #define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f |
| #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
| #define regDP1_DP_VID_TIMING 0x2210 |
| #define regDP1_DP_VID_TIMING_BASE_IDX 2 |
| #define regDP1_DP_VID_N 0x2211 |
| #define regDP1_DP_VID_N_BASE_IDX 2 |
| #define regDP1_DP_VID_M 0x2212 |
| #define regDP1_DP_VID_M_BASE_IDX 2 |
| #define regDP1_DP_LINK_FRAMING_CNTL 0x2213 |
| #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
| #define regDP1_DP_HBR2_EYE_PATTERN 0x2214 |
| #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
| #define regDP1_DP_VID_MSA_VBID 0x2215 |
| #define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 |
| #define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 |
| #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CNTL 0x2217 |
| #define regDP1_DP_DPHY_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 |
| #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_SYM0 0x2219 |
| #define regDP1_DP_DPHY_SYM0_BASE_IDX 2 |
| #define regDP1_DP_DPHY_SYM1 0x221a |
| #define regDP1_DP_DPHY_SYM1_BASE_IDX 2 |
| #define regDP1_DP_DPHY_SYM2 0x221b |
| #define regDP1_DP_DPHY_SYM2_BASE_IDX 2 |
| #define regDP1_DP_DPHY_8B10B_CNTL 0x221c |
| #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_PRBS_CNTL 0x221d |
| #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_SCRAM_CNTL 0x221e |
| #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CRC_EN 0x221f |
| #define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CRC_CNTL 0x2220 |
| #define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CRC_RESULT 0x2221 |
| #define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 |
| #define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 |
| #define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
| #define regDP1_DP_DPHY_FAST_TRAINING 0x2224 |
| #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
| #define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 |
| #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL 0x222b |
| #define regDP1_DP_SEC_CNTL_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL1 0x222c |
| #define regDP1_DP_SEC_CNTL1_BASE_IDX 2 |
| #define regDP1_DP_SEC_FRAMING1 0x222d |
| #define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 |
| #define regDP1_DP_SEC_FRAMING2 0x222e |
| #define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 |
| #define regDP1_DP_SEC_FRAMING3 0x222f |
| #define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 |
| #define regDP1_DP_SEC_FRAMING4 0x2230 |
| #define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 |
| #define regDP1_DP_SEC_AUD_N 0x2231 |
| #define regDP1_DP_SEC_AUD_N_BASE_IDX 2 |
| #define regDP1_DP_SEC_AUD_N_READBACK 0x2232 |
| #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
| #define regDP1_DP_SEC_AUD_M 0x2233 |
| #define regDP1_DP_SEC_AUD_M_BASE_IDX 2 |
| #define regDP1_DP_SEC_AUD_M_READBACK 0x2234 |
| #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
| #define regDP1_DP_SEC_TIMESTAMP 0x2235 |
| #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 |
| #define regDP1_DP_SEC_PACKET_CNTL 0x2236 |
| #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
| #define regDP1_DP_MSE_RATE_CNTL 0x2237 |
| #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 |
| #define regDP1_DP_MSE_RATE_UPDATE 0x2239 |
| #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT0 0x223a |
| #define regDP1_DP_MSE_SAT0_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT1 0x223b |
| #define regDP1_DP_MSE_SAT1_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT2 0x223c |
| #define regDP1_DP_MSE_SAT2_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT_UPDATE 0x223d |
| #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
| #define regDP1_DP_MSE_LINK_TIMING 0x223e |
| #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 |
| #define regDP1_DP_MSE_MISC_CNTL 0x223f |
| #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 |
| #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
| #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 |
| #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT0_STATUS 0x2247 |
| #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT1_STATUS 0x2248 |
| #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
| #define regDP1_DP_MSE_SAT2_STATUS 0x2249 |
| #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
| #define regDP1_DP_MSA_TIMING_PARAM1 0x224c |
| #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
| #define regDP1_DP_MSA_TIMING_PARAM2 0x224d |
| #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
| #define regDP1_DP_MSA_TIMING_PARAM3 0x224e |
| #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
| #define regDP1_DP_MSA_TIMING_PARAM4 0x224f |
| #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
| #define regDP1_DP_MSO_CNTL 0x2250 |
| #define regDP1_DP_MSO_CNTL_BASE_IDX 2 |
| #define regDP1_DP_MSO_CNTL1 0x2251 |
| #define regDP1_DP_MSO_CNTL1_BASE_IDX 2 |
| #define regDP1_DP_DSC_CNTL 0x2252 |
| #define regDP1_DP_DSC_CNTL_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL2 0x2253 |
| #define regDP1_DP_SEC_CNTL2_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL3 0x2254 |
| #define regDP1_DP_SEC_CNTL3_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL4 0x2255 |
| #define regDP1_DP_SEC_CNTL4_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL5 0x2256 |
| #define regDP1_DP_SEC_CNTL5_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL6 0x2257 |
| #define regDP1_DP_SEC_CNTL6_BASE_IDX 2 |
| #define regDP1_DP_SEC_CNTL7 0x2258 |
| #define regDP1_DP_SEC_CNTL7_BASE_IDX 2 |
| #define regDP1_DP_DB_CNTL 0x2259 |
| #define regDP1_DP_DB_CNTL_BASE_IDX 2 |
| #define regDP1_DP_MSA_VBID_MISC 0x225a |
| #define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 |
| #define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b |
| #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
| #define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c |
| #define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regDP1_DP_ALPM_CNTL 0x225d |
| #define regDP1_DP_ALPM_CNTL_BASE_IDX 2 |
| #define regDP1_DP_GSP8_CNTL 0x225e |
| #define regDP1_DP_GSP8_CNTL_BASE_IDX 2 |
| #define regDP1_DP_GSP9_CNTL 0x225f |
| #define regDP1_DP_GSP9_CNTL_BASE_IDX 2 |
| #define regDP1_DP_GSP10_CNTL 0x2260 |
| #define regDP1_DP_GSP10_CNTL_BASE_IDX 2 |
| #define regDP1_DP_GSP11_CNTL 0x2261 |
| #define regDP1_DP_GSP11_CNTL_BASE_IDX 2 |
| #define regDP1_DP_GSP_EN_DB_STATUS 0x2262 |
| #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig1_dispdec |
| // base address: 0x400 |
| #define regDIG1_DIG_FE_CNTL 0x218b |
| #define regDIG1_DIG_FE_CNTL_BASE_IDX 2 |
| #define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c |
| #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
| #define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d |
| #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
| #define regDIG1_DIG_CLOCK_PATTERN 0x218e |
| #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 |
| #define regDIG1_DIG_TEST_PATTERN 0x218f |
| #define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 |
| #define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 |
| #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
| #define regDIG1_DIG_FIFO_STATUS 0x2191 |
| #define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 |
| #define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 |
| #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_CONTROL 0x2193 |
| #define regDIG1_HDMI_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_STATUS 0x2194 |
| #define regDIG1_HDMI_STATUS_BASE_IDX 2 |
| #define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 |
| #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 |
| #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 |
| #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 |
| #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 |
| #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
| #define regDIG1_HDMI_GC 0x219d |
| #define regDIG1_HDMI_GC_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 |
| #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
| #define regDIG1_HDMI_DB_CONTROL 0x21a6 |
| #define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_32_0 0x21a7 |
| #define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_32_1 0x21a8 |
| #define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_44_0 0x21a9 |
| #define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_44_1 0x21aa |
| #define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_48_0 0x21ab |
| #define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_48_1 0x21ac |
| #define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_STATUS_0 0x21ad |
| #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 |
| #define regDIG1_HDMI_ACR_STATUS_1 0x21ae |
| #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 |
| #define regDIG1_AFMT_CNTL 0x21af |
| #define regDIG1_AFMT_CNTL_BASE_IDX 2 |
| #define regDIG1_DIG_BE_CNTL 0x21b0 |
| #define regDIG1_DIG_BE_CNTL_BASE_IDX 2 |
| #define regDIG1_DIG_BE_EN_CNTL 0x21b1 |
| #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 |
| #define regDIG1_TMDS_CNTL 0x21d7 |
| #define regDIG1_TMDS_CNTL_BASE_IDX 2 |
| #define regDIG1_TMDS_CONTROL_CHAR 0x21d8 |
| #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 |
| #define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 |
| #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
| #define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da |
| #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
| #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db |
| #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
| #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc |
| #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
| #define regDIG1_TMDS_CTL_BITS 0x21de |
| #define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 |
| #define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df |
| #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
| #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 |
| #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
| #define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 |
| #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
| #define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 |
| #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
| #define regDIG1_DIG_VERSION 0x21e4 |
| #define regDIG1_DIG_VERSION_BASE_IDX 2 |
| #define regDIG1_FORCE_DIG_DISABLE 0x21e5 |
| #define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp2_dispdec |
| // base address: 0x800 |
| #define regDP2_DP_LINK_CNTL 0x2308 |
| #define regDP2_DP_LINK_CNTL_BASE_IDX 2 |
| #define regDP2_DP_PIXEL_FORMAT 0x2309 |
| #define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP2_DP_MSA_COLORIMETRY 0x230a |
| #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 |
| #define regDP2_DP_CONFIG 0x230b |
| #define regDP2_DP_CONFIG_BASE_IDX 2 |
| #define regDP2_DP_VID_STREAM_CNTL 0x230c |
| #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 |
| #define regDP2_DP_STEER_FIFO 0x230d |
| #define regDP2_DP_STEER_FIFO_BASE_IDX 2 |
| #define regDP2_DP_MSA_MISC 0x230e |
| #define regDP2_DP_MSA_MISC_BASE_IDX 2 |
| #define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f |
| #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
| #define regDP2_DP_VID_TIMING 0x2310 |
| #define regDP2_DP_VID_TIMING_BASE_IDX 2 |
| #define regDP2_DP_VID_N 0x2311 |
| #define regDP2_DP_VID_N_BASE_IDX 2 |
| #define regDP2_DP_VID_M 0x2312 |
| #define regDP2_DP_VID_M_BASE_IDX 2 |
| #define regDP2_DP_LINK_FRAMING_CNTL 0x2313 |
| #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
| #define regDP2_DP_HBR2_EYE_PATTERN 0x2314 |
| #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
| #define regDP2_DP_VID_MSA_VBID 0x2315 |
| #define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 |
| #define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 |
| #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CNTL 0x2317 |
| #define regDP2_DP_DPHY_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 |
| #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_SYM0 0x2319 |
| #define regDP2_DP_DPHY_SYM0_BASE_IDX 2 |
| #define regDP2_DP_DPHY_SYM1 0x231a |
| #define regDP2_DP_DPHY_SYM1_BASE_IDX 2 |
| #define regDP2_DP_DPHY_SYM2 0x231b |
| #define regDP2_DP_DPHY_SYM2_BASE_IDX 2 |
| #define regDP2_DP_DPHY_8B10B_CNTL 0x231c |
| #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_PRBS_CNTL 0x231d |
| #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_SCRAM_CNTL 0x231e |
| #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CRC_EN 0x231f |
| #define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CRC_CNTL 0x2320 |
| #define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CRC_RESULT 0x2321 |
| #define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 |
| #define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 |
| #define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
| #define regDP2_DP_DPHY_FAST_TRAINING 0x2324 |
| #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
| #define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 |
| #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL 0x232b |
| #define regDP2_DP_SEC_CNTL_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL1 0x232c |
| #define regDP2_DP_SEC_CNTL1_BASE_IDX 2 |
| #define regDP2_DP_SEC_FRAMING1 0x232d |
| #define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 |
| #define regDP2_DP_SEC_FRAMING2 0x232e |
| #define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 |
| #define regDP2_DP_SEC_FRAMING3 0x232f |
| #define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 |
| #define regDP2_DP_SEC_FRAMING4 0x2330 |
| #define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 |
| #define regDP2_DP_SEC_AUD_N 0x2331 |
| #define regDP2_DP_SEC_AUD_N_BASE_IDX 2 |
| #define regDP2_DP_SEC_AUD_N_READBACK 0x2332 |
| #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
| #define regDP2_DP_SEC_AUD_M 0x2333 |
| #define regDP2_DP_SEC_AUD_M_BASE_IDX 2 |
| #define regDP2_DP_SEC_AUD_M_READBACK 0x2334 |
| #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
| #define regDP2_DP_SEC_TIMESTAMP 0x2335 |
| #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 |
| #define regDP2_DP_SEC_PACKET_CNTL 0x2336 |
| #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
| #define regDP2_DP_MSE_RATE_CNTL 0x2337 |
| #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 |
| #define regDP2_DP_MSE_RATE_UPDATE 0x2339 |
| #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT0 0x233a |
| #define regDP2_DP_MSE_SAT0_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT1 0x233b |
| #define regDP2_DP_MSE_SAT1_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT2 0x233c |
| #define regDP2_DP_MSE_SAT2_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT_UPDATE 0x233d |
| #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
| #define regDP2_DP_MSE_LINK_TIMING 0x233e |
| #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 |
| #define regDP2_DP_MSE_MISC_CNTL 0x233f |
| #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 |
| #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
| #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 |
| #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT0_STATUS 0x2347 |
| #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT1_STATUS 0x2348 |
| #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
| #define regDP2_DP_MSE_SAT2_STATUS 0x2349 |
| #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
| #define regDP2_DP_MSA_TIMING_PARAM1 0x234c |
| #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
| #define regDP2_DP_MSA_TIMING_PARAM2 0x234d |
| #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
| #define regDP2_DP_MSA_TIMING_PARAM3 0x234e |
| #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
| #define regDP2_DP_MSA_TIMING_PARAM4 0x234f |
| #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
| #define regDP2_DP_MSO_CNTL 0x2350 |
| #define regDP2_DP_MSO_CNTL_BASE_IDX 2 |
| #define regDP2_DP_MSO_CNTL1 0x2351 |
| #define regDP2_DP_MSO_CNTL1_BASE_IDX 2 |
| #define regDP2_DP_DSC_CNTL 0x2352 |
| #define regDP2_DP_DSC_CNTL_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL2 0x2353 |
| #define regDP2_DP_SEC_CNTL2_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL3 0x2354 |
| #define regDP2_DP_SEC_CNTL3_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL4 0x2355 |
| #define regDP2_DP_SEC_CNTL4_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL5 0x2356 |
| #define regDP2_DP_SEC_CNTL5_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL6 0x2357 |
| #define regDP2_DP_SEC_CNTL6_BASE_IDX 2 |
| #define regDP2_DP_SEC_CNTL7 0x2358 |
| #define regDP2_DP_SEC_CNTL7_BASE_IDX 2 |
| #define regDP2_DP_DB_CNTL 0x2359 |
| #define regDP2_DP_DB_CNTL_BASE_IDX 2 |
| #define regDP2_DP_MSA_VBID_MISC 0x235a |
| #define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 |
| #define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b |
| #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
| #define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c |
| #define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regDP2_DP_ALPM_CNTL 0x235d |
| #define regDP2_DP_ALPM_CNTL_BASE_IDX 2 |
| #define regDP2_DP_GSP8_CNTL 0x235e |
| #define regDP2_DP_GSP8_CNTL_BASE_IDX 2 |
| #define regDP2_DP_GSP9_CNTL 0x235f |
| #define regDP2_DP_GSP9_CNTL_BASE_IDX 2 |
| #define regDP2_DP_GSP10_CNTL 0x2360 |
| #define regDP2_DP_GSP10_CNTL_BASE_IDX 2 |
| #define regDP2_DP_GSP11_CNTL 0x2361 |
| #define regDP2_DP_GSP11_CNTL_BASE_IDX 2 |
| #define regDP2_DP_GSP_EN_DB_STATUS 0x2362 |
| #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig2_dispdec |
| // base address: 0x800 |
| #define regDIG2_DIG_FE_CNTL 0x228b |
| #define regDIG2_DIG_FE_CNTL_BASE_IDX 2 |
| #define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c |
| #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
| #define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d |
| #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
| #define regDIG2_DIG_CLOCK_PATTERN 0x228e |
| #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 |
| #define regDIG2_DIG_TEST_PATTERN 0x228f |
| #define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 |
| #define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 |
| #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
| #define regDIG2_DIG_FIFO_STATUS 0x2291 |
| #define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 |
| #define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 |
| #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_CONTROL 0x2293 |
| #define regDIG2_HDMI_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_STATUS 0x2294 |
| #define regDIG2_HDMI_STATUS_BASE_IDX 2 |
| #define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 |
| #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 |
| #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 |
| #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 |
| #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 |
| #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
| #define regDIG2_HDMI_GC 0x229d |
| #define regDIG2_HDMI_GC_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 |
| #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
| #define regDIG2_HDMI_DB_CONTROL 0x22a6 |
| #define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_32_0 0x22a7 |
| #define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_32_1 0x22a8 |
| #define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_44_0 0x22a9 |
| #define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_44_1 0x22aa |
| #define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_48_0 0x22ab |
| #define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_48_1 0x22ac |
| #define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_STATUS_0 0x22ad |
| #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 |
| #define regDIG2_HDMI_ACR_STATUS_1 0x22ae |
| #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 |
| #define regDIG2_AFMT_CNTL 0x22af |
| #define regDIG2_AFMT_CNTL_BASE_IDX 2 |
| #define regDIG2_DIG_BE_CNTL 0x22b0 |
| #define regDIG2_DIG_BE_CNTL_BASE_IDX 2 |
| #define regDIG2_DIG_BE_EN_CNTL 0x22b1 |
| #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 |
| #define regDIG2_TMDS_CNTL 0x22d7 |
| #define regDIG2_TMDS_CNTL_BASE_IDX 2 |
| #define regDIG2_TMDS_CONTROL_CHAR 0x22d8 |
| #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 |
| #define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 |
| #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
| #define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da |
| #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
| #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db |
| #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
| #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc |
| #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
| #define regDIG2_TMDS_CTL_BITS 0x22de |
| #define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 |
| #define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df |
| #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
| #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 |
| #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
| #define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 |
| #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
| #define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 |
| #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
| #define regDIG2_DIG_VERSION 0x22e4 |
| #define regDIG2_DIG_VERSION_BASE_IDX 2 |
| #define regDIG2_FORCE_DIG_DISABLE 0x22e5 |
| #define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp3_dispdec |
| // base address: 0xc00 |
| #define regDP3_DP_LINK_CNTL 0x2408 |
| #define regDP3_DP_LINK_CNTL_BASE_IDX 2 |
| #define regDP3_DP_PIXEL_FORMAT 0x2409 |
| #define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP3_DP_MSA_COLORIMETRY 0x240a |
| #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 |
| #define regDP3_DP_CONFIG 0x240b |
| #define regDP3_DP_CONFIG_BASE_IDX 2 |
| #define regDP3_DP_VID_STREAM_CNTL 0x240c |
| #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 |
| #define regDP3_DP_STEER_FIFO 0x240d |
| #define regDP3_DP_STEER_FIFO_BASE_IDX 2 |
| #define regDP3_DP_MSA_MISC 0x240e |
| #define regDP3_DP_MSA_MISC_BASE_IDX 2 |
| #define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f |
| #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
| #define regDP3_DP_VID_TIMING 0x2410 |
| #define regDP3_DP_VID_TIMING_BASE_IDX 2 |
| #define regDP3_DP_VID_N 0x2411 |
| #define regDP3_DP_VID_N_BASE_IDX 2 |
| #define regDP3_DP_VID_M 0x2412 |
| #define regDP3_DP_VID_M_BASE_IDX 2 |
| #define regDP3_DP_LINK_FRAMING_CNTL 0x2413 |
| #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
| #define regDP3_DP_HBR2_EYE_PATTERN 0x2414 |
| #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
| #define regDP3_DP_VID_MSA_VBID 0x2415 |
| #define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 |
| #define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 |
| #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CNTL 0x2417 |
| #define regDP3_DP_DPHY_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 |
| #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_SYM0 0x2419 |
| #define regDP3_DP_DPHY_SYM0_BASE_IDX 2 |
| #define regDP3_DP_DPHY_SYM1 0x241a |
| #define regDP3_DP_DPHY_SYM1_BASE_IDX 2 |
| #define regDP3_DP_DPHY_SYM2 0x241b |
| #define regDP3_DP_DPHY_SYM2_BASE_IDX 2 |
| #define regDP3_DP_DPHY_8B10B_CNTL 0x241c |
| #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_PRBS_CNTL 0x241d |
| #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_SCRAM_CNTL 0x241e |
| #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CRC_EN 0x241f |
| #define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CRC_CNTL 0x2420 |
| #define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CRC_RESULT 0x2421 |
| #define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 |
| #define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 |
| #define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
| #define regDP3_DP_DPHY_FAST_TRAINING 0x2424 |
| #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
| #define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 |
| #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL 0x242b |
| #define regDP3_DP_SEC_CNTL_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL1 0x242c |
| #define regDP3_DP_SEC_CNTL1_BASE_IDX 2 |
| #define regDP3_DP_SEC_FRAMING1 0x242d |
| #define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 |
| #define regDP3_DP_SEC_FRAMING2 0x242e |
| #define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 |
| #define regDP3_DP_SEC_FRAMING3 0x242f |
| #define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 |
| #define regDP3_DP_SEC_FRAMING4 0x2430 |
| #define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 |
| #define regDP3_DP_SEC_AUD_N 0x2431 |
| #define regDP3_DP_SEC_AUD_N_BASE_IDX 2 |
| #define regDP3_DP_SEC_AUD_N_READBACK 0x2432 |
| #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
| #define regDP3_DP_SEC_AUD_M 0x2433 |
| #define regDP3_DP_SEC_AUD_M_BASE_IDX 2 |
| #define regDP3_DP_SEC_AUD_M_READBACK 0x2434 |
| #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
| #define regDP3_DP_SEC_TIMESTAMP 0x2435 |
| #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 |
| #define regDP3_DP_SEC_PACKET_CNTL 0x2436 |
| #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
| #define regDP3_DP_MSE_RATE_CNTL 0x2437 |
| #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 |
| #define regDP3_DP_MSE_RATE_UPDATE 0x2439 |
| #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT0 0x243a |
| #define regDP3_DP_MSE_SAT0_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT1 0x243b |
| #define regDP3_DP_MSE_SAT1_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT2 0x243c |
| #define regDP3_DP_MSE_SAT2_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT_UPDATE 0x243d |
| #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
| #define regDP3_DP_MSE_LINK_TIMING 0x243e |
| #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 |
| #define regDP3_DP_MSE_MISC_CNTL 0x243f |
| #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 |
| #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
| #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 |
| #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT0_STATUS 0x2447 |
| #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT1_STATUS 0x2448 |
| #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
| #define regDP3_DP_MSE_SAT2_STATUS 0x2449 |
| #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
| #define regDP3_DP_MSA_TIMING_PARAM1 0x244c |
| #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
| #define regDP3_DP_MSA_TIMING_PARAM2 0x244d |
| #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
| #define regDP3_DP_MSA_TIMING_PARAM3 0x244e |
| #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
| #define regDP3_DP_MSA_TIMING_PARAM4 0x244f |
| #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
| #define regDP3_DP_MSO_CNTL 0x2450 |
| #define regDP3_DP_MSO_CNTL_BASE_IDX 2 |
| #define regDP3_DP_MSO_CNTL1 0x2451 |
| #define regDP3_DP_MSO_CNTL1_BASE_IDX 2 |
| #define regDP3_DP_DSC_CNTL 0x2452 |
| #define regDP3_DP_DSC_CNTL_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL2 0x2453 |
| #define regDP3_DP_SEC_CNTL2_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL3 0x2454 |
| #define regDP3_DP_SEC_CNTL3_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL4 0x2455 |
| #define regDP3_DP_SEC_CNTL4_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL5 0x2456 |
| #define regDP3_DP_SEC_CNTL5_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL6 0x2457 |
| #define regDP3_DP_SEC_CNTL6_BASE_IDX 2 |
| #define regDP3_DP_SEC_CNTL7 0x2458 |
| #define regDP3_DP_SEC_CNTL7_BASE_IDX 2 |
| #define regDP3_DP_DB_CNTL 0x2459 |
| #define regDP3_DP_DB_CNTL_BASE_IDX 2 |
| #define regDP3_DP_MSA_VBID_MISC 0x245a |
| #define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 |
| #define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b |
| #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
| #define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c |
| #define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regDP3_DP_ALPM_CNTL 0x245d |
| #define regDP3_DP_ALPM_CNTL_BASE_IDX 2 |
| #define regDP3_DP_GSP8_CNTL 0x245e |
| #define regDP3_DP_GSP8_CNTL_BASE_IDX 2 |
| #define regDP3_DP_GSP9_CNTL 0x245f |
| #define regDP3_DP_GSP9_CNTL_BASE_IDX 2 |
| #define regDP3_DP_GSP10_CNTL 0x2460 |
| #define regDP3_DP_GSP10_CNTL_BASE_IDX 2 |
| #define regDP3_DP_GSP11_CNTL 0x2461 |
| #define regDP3_DP_GSP11_CNTL_BASE_IDX 2 |
| #define regDP3_DP_GSP_EN_DB_STATUS 0x2462 |
| #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig3_dispdec |
| // base address: 0xc00 |
| #define regDIG3_DIG_FE_CNTL 0x238b |
| #define regDIG3_DIG_FE_CNTL_BASE_IDX 2 |
| #define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c |
| #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
| #define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d |
| #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
| #define regDIG3_DIG_CLOCK_PATTERN 0x238e |
| #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 |
| #define regDIG3_DIG_TEST_PATTERN 0x238f |
| #define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 |
| #define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 |
| #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
| #define regDIG3_DIG_FIFO_STATUS 0x2391 |
| #define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 |
| #define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 |
| #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_CONTROL 0x2393 |
| #define regDIG3_HDMI_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_STATUS 0x2394 |
| #define regDIG3_HDMI_STATUS_BASE_IDX 2 |
| #define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 |
| #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 |
| #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 |
| #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 |
| #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 |
| #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
| #define regDIG3_HDMI_GC 0x239d |
| #define regDIG3_HDMI_GC_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 |
| #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
| #define regDIG3_HDMI_DB_CONTROL 0x23a6 |
| #define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_32_0 0x23a7 |
| #define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_32_1 0x23a8 |
| #define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_44_0 0x23a9 |
| #define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_44_1 0x23aa |
| #define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_48_0 0x23ab |
| #define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_48_1 0x23ac |
| #define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_STATUS_0 0x23ad |
| #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 |
| #define regDIG3_HDMI_ACR_STATUS_1 0x23ae |
| #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 |
| #define regDIG3_AFMT_CNTL 0x23af |
| #define regDIG3_AFMT_CNTL_BASE_IDX 2 |
| #define regDIG3_DIG_BE_CNTL 0x23b0 |
| #define regDIG3_DIG_BE_CNTL_BASE_IDX 2 |
| #define regDIG3_DIG_BE_EN_CNTL 0x23b1 |
| #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 |
| #define regDIG3_TMDS_CNTL 0x23d7 |
| #define regDIG3_TMDS_CNTL_BASE_IDX 2 |
| #define regDIG3_TMDS_CONTROL_CHAR 0x23d8 |
| #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 |
| #define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 |
| #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
| #define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da |
| #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
| #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db |
| #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
| #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc |
| #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
| #define regDIG3_TMDS_CTL_BITS 0x23de |
| #define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 |
| #define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df |
| #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
| #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 |
| #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
| #define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 |
| #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
| #define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 |
| #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
| #define regDIG3_DIG_VERSION 0x23e4 |
| #define regDIG3_DIG_VERSION_BASE_IDX 2 |
| #define regDIG3_FORCE_DIG_DISABLE 0x23e5 |
| #define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp4_dispdec |
| // base address: 0x1000 |
| #define regDP4_DP_LINK_CNTL 0x2508 |
| #define regDP4_DP_LINK_CNTL_BASE_IDX 2 |
| #define regDP4_DP_PIXEL_FORMAT 0x2509 |
| #define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP4_DP_MSA_COLORIMETRY 0x250a |
| #define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 |
| #define regDP4_DP_CONFIG 0x250b |
| #define regDP4_DP_CONFIG_BASE_IDX 2 |
| #define regDP4_DP_VID_STREAM_CNTL 0x250c |
| #define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 |
| #define regDP4_DP_STEER_FIFO 0x250d |
| #define regDP4_DP_STEER_FIFO_BASE_IDX 2 |
| #define regDP4_DP_MSA_MISC 0x250e |
| #define regDP4_DP_MSA_MISC_BASE_IDX 2 |
| #define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f |
| #define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
| #define regDP4_DP_VID_TIMING 0x2510 |
| #define regDP4_DP_VID_TIMING_BASE_IDX 2 |
| #define regDP4_DP_VID_N 0x2511 |
| #define regDP4_DP_VID_N_BASE_IDX 2 |
| #define regDP4_DP_VID_M 0x2512 |
| #define regDP4_DP_VID_M_BASE_IDX 2 |
| #define regDP4_DP_LINK_FRAMING_CNTL 0x2513 |
| #define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
| #define regDP4_DP_HBR2_EYE_PATTERN 0x2514 |
| #define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
| #define regDP4_DP_VID_MSA_VBID 0x2515 |
| #define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 |
| #define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 |
| #define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CNTL 0x2517 |
| #define regDP4_DP_DPHY_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 |
| #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_SYM0 0x2519 |
| #define regDP4_DP_DPHY_SYM0_BASE_IDX 2 |
| #define regDP4_DP_DPHY_SYM1 0x251a |
| #define regDP4_DP_DPHY_SYM1_BASE_IDX 2 |
| #define regDP4_DP_DPHY_SYM2 0x251b |
| #define regDP4_DP_DPHY_SYM2_BASE_IDX 2 |
| #define regDP4_DP_DPHY_8B10B_CNTL 0x251c |
| #define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_PRBS_CNTL 0x251d |
| #define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_SCRAM_CNTL 0x251e |
| #define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CRC_EN 0x251f |
| #define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CRC_CNTL 0x2520 |
| #define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CRC_RESULT 0x2521 |
| #define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 |
| #define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 |
| #define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
| #define regDP4_DP_DPHY_FAST_TRAINING 0x2524 |
| #define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
| #define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 |
| #define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL 0x252b |
| #define regDP4_DP_SEC_CNTL_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL1 0x252c |
| #define regDP4_DP_SEC_CNTL1_BASE_IDX 2 |
| #define regDP4_DP_SEC_FRAMING1 0x252d |
| #define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 |
| #define regDP4_DP_SEC_FRAMING2 0x252e |
| #define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 |
| #define regDP4_DP_SEC_FRAMING3 0x252f |
| #define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 |
| #define regDP4_DP_SEC_FRAMING4 0x2530 |
| #define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 |
| #define regDP4_DP_SEC_AUD_N 0x2531 |
| #define regDP4_DP_SEC_AUD_N_BASE_IDX 2 |
| #define regDP4_DP_SEC_AUD_N_READBACK 0x2532 |
| #define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
| #define regDP4_DP_SEC_AUD_M 0x2533 |
| #define regDP4_DP_SEC_AUD_M_BASE_IDX 2 |
| #define regDP4_DP_SEC_AUD_M_READBACK 0x2534 |
| #define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
| #define regDP4_DP_SEC_TIMESTAMP 0x2535 |
| #define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 |
| #define regDP4_DP_SEC_PACKET_CNTL 0x2536 |
| #define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
| #define regDP4_DP_MSE_RATE_CNTL 0x2537 |
| #define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 |
| #define regDP4_DP_MSE_RATE_UPDATE 0x2539 |
| #define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT0 0x253a |
| #define regDP4_DP_MSE_SAT0_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT1 0x253b |
| #define regDP4_DP_MSE_SAT1_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT2 0x253c |
| #define regDP4_DP_MSE_SAT2_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT_UPDATE 0x253d |
| #define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
| #define regDP4_DP_MSE_LINK_TIMING 0x253e |
| #define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 |
| #define regDP4_DP_MSE_MISC_CNTL 0x253f |
| #define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 |
| #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
| #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 |
| #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT0_STATUS 0x2547 |
| #define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT1_STATUS 0x2548 |
| #define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
| #define regDP4_DP_MSE_SAT2_STATUS 0x2549 |
| #define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
| #define regDP4_DP_MSA_TIMING_PARAM1 0x254c |
| #define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
| #define regDP4_DP_MSA_TIMING_PARAM2 0x254d |
| #define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
| #define regDP4_DP_MSA_TIMING_PARAM3 0x254e |
| #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
| #define regDP4_DP_MSA_TIMING_PARAM4 0x254f |
| #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
| #define regDP4_DP_MSO_CNTL 0x2550 |
| #define regDP4_DP_MSO_CNTL_BASE_IDX 2 |
| #define regDP4_DP_MSO_CNTL1 0x2551 |
| #define regDP4_DP_MSO_CNTL1_BASE_IDX 2 |
| #define regDP4_DP_DSC_CNTL 0x2552 |
| #define regDP4_DP_DSC_CNTL_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL2 0x2553 |
| #define regDP4_DP_SEC_CNTL2_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL3 0x2554 |
| #define regDP4_DP_SEC_CNTL3_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL4 0x2555 |
| #define regDP4_DP_SEC_CNTL4_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL5 0x2556 |
| #define regDP4_DP_SEC_CNTL5_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL6 0x2557 |
| #define regDP4_DP_SEC_CNTL6_BASE_IDX 2 |
| #define regDP4_DP_SEC_CNTL7 0x2558 |
| #define regDP4_DP_SEC_CNTL7_BASE_IDX 2 |
| #define regDP4_DP_DB_CNTL 0x2559 |
| #define regDP4_DP_DB_CNTL_BASE_IDX 2 |
| #define regDP4_DP_MSA_VBID_MISC 0x255a |
| #define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 |
| #define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b |
| #define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
| #define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c |
| #define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 |
| #define regDP4_DP_ALPM_CNTL 0x255d |
| #define regDP4_DP_ALPM_CNTL_BASE_IDX 2 |
| #define regDP4_DP_GSP8_CNTL 0x255e |
| #define regDP4_DP_GSP8_CNTL_BASE_IDX 2 |
| #define regDP4_DP_GSP9_CNTL 0x255f |
| #define regDP4_DP_GSP9_CNTL_BASE_IDX 2 |
| #define regDP4_DP_GSP10_CNTL 0x2560 |
| #define regDP4_DP_GSP10_CNTL_BASE_IDX 2 |
| #define regDP4_DP_GSP11_CNTL 0x2561 |
| #define regDP4_DP_GSP11_CNTL_BASE_IDX 2 |
| #define regDP4_DP_GSP_EN_DB_STATUS 0x2562 |
| #define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig4_dispdec |
| // base address: 0x1000 |
| #define regDIG4_DIG_FE_CNTL 0x248b |
| #define regDIG4_DIG_FE_CNTL_BASE_IDX 2 |
| #define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c |
| #define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
| #define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d |
| #define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
| #define regDIG4_DIG_CLOCK_PATTERN 0x248e |
| #define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 |
| #define regDIG4_DIG_TEST_PATTERN 0x248f |
| #define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 |
| #define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 |
| #define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
| #define regDIG4_DIG_FIFO_STATUS 0x2491 |
| #define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 |
| #define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 |
| #define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_CONTROL 0x2493 |
| #define regDIG4_HDMI_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_STATUS 0x2494 |
| #define regDIG4_HDMI_STATUS_BASE_IDX 2 |
| #define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 |
| #define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 |
| #define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 |
| #define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 |
| #define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 |
| #define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
| #define regDIG4_HDMI_GC 0x249d |
| #define regDIG4_HDMI_GC_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 |
| #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
| #define regDIG4_HDMI_DB_CONTROL 0x24a6 |
| #define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_32_0 0x24a7 |
| #define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_32_1 0x24a8 |
| #define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_44_0 0x24a9 |
| #define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_44_1 0x24aa |
| #define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_48_0 0x24ab |
| #define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_48_1 0x24ac |
| #define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_STATUS_0 0x24ad |
| #define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 |
| #define regDIG4_HDMI_ACR_STATUS_1 0x24ae |
| #define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 |
| #define regDIG4_AFMT_CNTL 0x24af |
| #define regDIG4_AFMT_CNTL_BASE_IDX 2 |
| #define regDIG4_DIG_BE_CNTL 0x24b0 |
| #define regDIG4_DIG_BE_CNTL_BASE_IDX 2 |
| #define regDIG4_DIG_BE_EN_CNTL 0x24b1 |
| #define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 |
| #define regDIG4_TMDS_CNTL 0x24d7 |
| #define regDIG4_TMDS_CNTL_BASE_IDX 2 |
| #define regDIG4_TMDS_CONTROL_CHAR 0x24d8 |
| #define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 |
| #define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 |
| #define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
| #define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da |
| #define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
| #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db |
| #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
| #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc |
| #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
| #define regDIG4_TMDS_CTL_BITS 0x24de |
| #define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 |
| #define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df |
| #define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
| #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 |
| #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
| #define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 |
| #define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
| #define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 |
| #define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
| #define regDIG4_DIG_VERSION 0x24e4 |
| #define regDIG4_DIG_VERSION_BASE_IDX 2 |
| #define regDIG4_FORCE_DIG_DISABLE 0x24e5 |
| #define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec |
| // base address: 0x154cc |
| #define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 |
| #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 |
| #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_INFO0 0x2076 |
| #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_INFO1 0x2077 |
| #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 |
| #define regAFMT0_AFMT_60958_0 0x2078 |
| #define regAFMT0_AFMT_60958_0_BASE_IDX 2 |
| #define regAFMT0_AFMT_60958_1 0x2079 |
| #define regAFMT0_AFMT_60958_1_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a |
| #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAFMT0_AFMT_RAMP_CONTROL0 0x207b |
| #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
| #define regAFMT0_AFMT_RAMP_CONTROL1 0x207c |
| #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
| #define regAFMT0_AFMT_RAMP_CONTROL2 0x207d |
| #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
| #define regAFMT0_AFMT_RAMP_CONTROL3 0x207e |
| #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
| #define regAFMT0_AFMT_60958_2 0x207f |
| #define regAFMT0_AFMT_60958_2_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 |
| #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAFMT0_AFMT_STATUS 0x2081 |
| #define regAFMT0_AFMT_STATUS_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 |
| #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 |
| #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 |
| #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 |
| #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
| #define regAFMT0_AFMT_MEM_PWR 0x2087 |
| #define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec |
| // base address: 0x158cc |
| #define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 |
| #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 |
| #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_INFO0 0x2176 |
| #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_INFO1 0x2177 |
| #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 |
| #define regAFMT1_AFMT_60958_0 0x2178 |
| #define regAFMT1_AFMT_60958_0_BASE_IDX 2 |
| #define regAFMT1_AFMT_60958_1 0x2179 |
| #define regAFMT1_AFMT_60958_1_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a |
| #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAFMT1_AFMT_RAMP_CONTROL0 0x217b |
| #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
| #define regAFMT1_AFMT_RAMP_CONTROL1 0x217c |
| #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
| #define regAFMT1_AFMT_RAMP_CONTROL2 0x217d |
| #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
| #define regAFMT1_AFMT_RAMP_CONTROL3 0x217e |
| #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
| #define regAFMT1_AFMT_60958_2 0x217f |
| #define regAFMT1_AFMT_60958_2_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 |
| #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAFMT1_AFMT_STATUS 0x2181 |
| #define regAFMT1_AFMT_STATUS_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 |
| #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 |
| #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 |
| #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 |
| #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
| #define regAFMT1_AFMT_MEM_PWR 0x2187 |
| #define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec |
| // base address: 0x15ccc |
| #define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 |
| #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 |
| #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_INFO0 0x2276 |
| #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_INFO1 0x2277 |
| #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 |
| #define regAFMT2_AFMT_60958_0 0x2278 |
| #define regAFMT2_AFMT_60958_0_BASE_IDX 2 |
| #define regAFMT2_AFMT_60958_1 0x2279 |
| #define regAFMT2_AFMT_60958_1_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a |
| #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAFMT2_AFMT_RAMP_CONTROL0 0x227b |
| #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
| #define regAFMT2_AFMT_RAMP_CONTROL1 0x227c |
| #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
| #define regAFMT2_AFMT_RAMP_CONTROL2 0x227d |
| #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
| #define regAFMT2_AFMT_RAMP_CONTROL3 0x227e |
| #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
| #define regAFMT2_AFMT_60958_2 0x227f |
| #define regAFMT2_AFMT_60958_2_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 |
| #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAFMT2_AFMT_STATUS 0x2281 |
| #define regAFMT2_AFMT_STATUS_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 |
| #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 |
| #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 |
| #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 |
| #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
| #define regAFMT2_AFMT_MEM_PWR 0x2287 |
| #define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec |
| // base address: 0x160cc |
| #define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 |
| #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 |
| #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_INFO0 0x2376 |
| #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_INFO1 0x2377 |
| #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 |
| #define regAFMT3_AFMT_60958_0 0x2378 |
| #define regAFMT3_AFMT_60958_0_BASE_IDX 2 |
| #define regAFMT3_AFMT_60958_1 0x2379 |
| #define regAFMT3_AFMT_60958_1_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a |
| #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAFMT3_AFMT_RAMP_CONTROL0 0x237b |
| #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
| #define regAFMT3_AFMT_RAMP_CONTROL1 0x237c |
| #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
| #define regAFMT3_AFMT_RAMP_CONTROL2 0x237d |
| #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
| #define regAFMT3_AFMT_RAMP_CONTROL3 0x237e |
| #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
| #define regAFMT3_AFMT_60958_2 0x237f |
| #define regAFMT3_AFMT_60958_2_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 |
| #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAFMT3_AFMT_STATUS 0x2381 |
| #define regAFMT3_AFMT_STATUS_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 |
| #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 |
| #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 |
| #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 |
| #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
| #define regAFMT3_AFMT_MEM_PWR 0x2387 |
| #define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec |
| // base address: 0x164cc |
| #define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 |
| #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 |
| #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_INFO0 0x2476 |
| #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_INFO1 0x2477 |
| #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 |
| #define regAFMT4_AFMT_60958_0 0x2478 |
| #define regAFMT4_AFMT_60958_0_BASE_IDX 2 |
| #define regAFMT4_AFMT_60958_1 0x2479 |
| #define regAFMT4_AFMT_60958_1_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a |
| #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAFMT4_AFMT_RAMP_CONTROL0 0x247b |
| #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
| #define regAFMT4_AFMT_RAMP_CONTROL1 0x247c |
| #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
| #define regAFMT4_AFMT_RAMP_CONTROL2 0x247d |
| #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
| #define regAFMT4_AFMT_RAMP_CONTROL3 0x247e |
| #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
| #define regAFMT4_AFMT_60958_2 0x247f |
| #define regAFMT4_AFMT_60958_2_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 |
| #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAFMT4_AFMT_STATUS 0x2481 |
| #define regAFMT4_AFMT_STATUS_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 |
| #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
| #define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 |
| #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
| #define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 |
| #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
| #define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 |
| #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
| #define regAFMT4_AFMT_MEM_PWR 0x2487 |
| #define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec |
| // base address: 0x15524 |
| #define regDME0_DME_CONTROL 0x2089 |
| #define regDME0_DME_CONTROL_BASE_IDX 2 |
| #define regDME0_DME_MEMORY_CONTROL 0x208a |
| #define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec |
| // base address: 0x154a0 |
| #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 |
| #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 |
| #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a |
| #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b |
| #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG0_VPG_GENERIC_STATUS 0x206c |
| #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG0_VPG_MEM_PWR 0x206d |
| #define regVPG0_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e |
| #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG0_VPG_ISRC1_2_DATA 0x206f |
| #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG0_VPG_MPEG_INFO0 0x2070 |
| #define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG0_VPG_MPEG_INFO1 0x2071 |
| #define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec |
| // base address: 0x15924 |
| #define regDME1_DME_CONTROL 0x2189 |
| #define regDME1_DME_CONTROL_BASE_IDX 2 |
| #define regDME1_DME_MEMORY_CONTROL 0x218a |
| #define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec |
| // base address: 0x158a0 |
| #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 |
| #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 |
| #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a |
| #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b |
| #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG1_VPG_GENERIC_STATUS 0x216c |
| #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG1_VPG_MEM_PWR 0x216d |
| #define regVPG1_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e |
| #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG1_VPG_ISRC1_2_DATA 0x216f |
| #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG1_VPG_MPEG_INFO0 0x2170 |
| #define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG1_VPG_MPEG_INFO1 0x2171 |
| #define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec |
| // base address: 0x15d24 |
| #define regDME2_DME_CONTROL 0x2289 |
| #define regDME2_DME_CONTROL_BASE_IDX 2 |
| #define regDME2_DME_MEMORY_CONTROL 0x228a |
| #define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec |
| // base address: 0x15ca0 |
| #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 |
| #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 |
| #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a |
| #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b |
| #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG2_VPG_GENERIC_STATUS 0x226c |
| #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG2_VPG_MEM_PWR 0x226d |
| #define regVPG2_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e |
| #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG2_VPG_ISRC1_2_DATA 0x226f |
| #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG2_VPG_MPEG_INFO0 0x2270 |
| #define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG2_VPG_MPEG_INFO1 0x2271 |
| #define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec |
| // base address: 0x16124 |
| #define regDME3_DME_CONTROL 0x2389 |
| #define regDME3_DME_CONTROL_BASE_IDX 2 |
| #define regDME3_DME_MEMORY_CONTROL 0x238a |
| #define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec |
| // base address: 0x160a0 |
| #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 |
| #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 |
| #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a |
| #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b |
| #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG3_VPG_GENERIC_STATUS 0x236c |
| #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG3_VPG_MEM_PWR 0x236d |
| #define regVPG3_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e |
| #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG3_VPG_ISRC1_2_DATA 0x236f |
| #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG3_VPG_MPEG_INFO0 0x2370 |
| #define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG3_VPG_MPEG_INFO1 0x2371 |
| #define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec |
| // base address: 0x16524 |
| #define regDME4_DME_CONTROL 0x2489 |
| #define regDME4_DME_CONTROL_BASE_IDX 2 |
| #define regDME4_DME_MEMORY_CONTROL 0x248a |
| #define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec |
| // base address: 0x164a0 |
| #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 |
| #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 |
| #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a |
| #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b |
| #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG4_VPG_GENERIC_STATUS 0x246c |
| #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG4_VPG_MEM_PWR 0x246d |
| #define regVPG4_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e |
| #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG4_VPG_ISRC1_2_DATA 0x246f |
| #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG4_VPG_MPEG_INFO0 0x2470 |
| #define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG4_VPG_MPEG_INFO1 0x2471 |
| #define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp_aux0_dispdec |
| // base address: 0x0 |
| #define regDP_AUX0_AUX_CONTROL 0x1f50 |
| #define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_SW_CONTROL 0x1f51 |
| #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 |
| #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 |
| #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_SW_STATUS 0x1f54 |
| #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_LS_STATUS 0x1f55 |
| #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_SW_DATA 0x1f56 |
| #define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 |
| #define regDP_AUX0_AUX_LS_DATA 0x1f57 |
| #define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 |
| #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 |
| #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a |
| #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b |
| #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c |
| #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d |
| #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e |
| #define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f |
| #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
| #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 |
| #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 |
| #define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
| #define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 |
| #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp_aux1_dispdec |
| // base address: 0x70 |
| #define regDP_AUX1_AUX_CONTROL 0x1f6c |
| #define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_SW_CONTROL 0x1f6d |
| #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e |
| #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f |
| #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_SW_STATUS 0x1f70 |
| #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_LS_STATUS 0x1f71 |
| #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_SW_DATA 0x1f72 |
| #define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 |
| #define regDP_AUX1_AUX_LS_DATA 0x1f73 |
| #define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 |
| #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 |
| #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 |
| #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 |
| #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 |
| #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 |
| #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a |
| #define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b |
| #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
| #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c |
| #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d |
| #define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
| #define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 |
| #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp_aux2_dispdec |
| // base address: 0xe0 |
| #define regDP_AUX2_AUX_CONTROL 0x1f88 |
| #define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_SW_CONTROL 0x1f89 |
| #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a |
| #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b |
| #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_SW_STATUS 0x1f8c |
| #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_LS_STATUS 0x1f8d |
| #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_SW_DATA 0x1f8e |
| #define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 |
| #define regDP_AUX2_AUX_LS_DATA 0x1f8f |
| #define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 |
| #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 |
| #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 |
| #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 |
| #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 |
| #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 |
| #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 |
| #define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 |
| #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
| #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 |
| #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 |
| #define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
| #define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e |
| #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp_aux3_dispdec |
| // base address: 0x150 |
| #define regDP_AUX3_AUX_CONTROL 0x1fa4 |
| #define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 |
| #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 |
| #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 |
| #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_SW_STATUS 0x1fa8 |
| #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_LS_STATUS 0x1fa9 |
| #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_SW_DATA 0x1faa |
| #define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 |
| #define regDP_AUX3_AUX_LS_DATA 0x1fab |
| #define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac |
| #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad |
| #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae |
| #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf |
| #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 |
| #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 |
| #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 |
| #define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 |
| #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
| #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 |
| #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 |
| #define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
| #define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba |
| #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dp_aux4_dispdec |
| // base address: 0x1c0 |
| #define regDP_AUX4_AUX_CONTROL 0x1fc0 |
| #define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 |
| #define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 |
| #define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 |
| #define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_SW_STATUS 0x1fc4 |
| #define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_LS_STATUS 0x1fc5 |
| #define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_SW_DATA 0x1fc6 |
| #define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 |
| #define regDP_AUX4_AUX_LS_DATA 0x1fc7 |
| #define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 |
| #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 |
| #define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca |
| #define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb |
| #define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc |
| #define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd |
| #define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce |
| #define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf |
| #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
| #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 |
| #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 |
| #define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
| #define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 |
| #define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dout_i2c_dispdec |
| // base address: 0x0 |
| #define regDC_I2C_CONTROL 0x1e98 |
| #define regDC_I2C_CONTROL_BASE_IDX 2 |
| #define regDC_I2C_ARBITRATION 0x1e99 |
| #define regDC_I2C_ARBITRATION_BASE_IDX 2 |
| #define regDC_I2C_INTERRUPT_CONTROL 0x1e9a |
| #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define regDC_I2C_SW_STATUS 0x1e9b |
| #define regDC_I2C_SW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC1_HW_STATUS 0x1e9c |
| #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC2_HW_STATUS 0x1e9d |
| #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC3_HW_STATUS 0x1e9e |
| #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC4_HW_STATUS 0x1e9f |
| #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC5_HW_STATUS 0x1ea0 |
| #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 |
| #define regDC_I2C_DDC1_SPEED 0x1ea2 |
| #define regDC_I2C_DDC1_SPEED_BASE_IDX 2 |
| #define regDC_I2C_DDC1_SETUP 0x1ea3 |
| #define regDC_I2C_DDC1_SETUP_BASE_IDX 2 |
| #define regDC_I2C_DDC2_SPEED 0x1ea4 |
| #define regDC_I2C_DDC2_SPEED_BASE_IDX 2 |
| #define regDC_I2C_DDC2_SETUP 0x1ea5 |
| #define regDC_I2C_DDC2_SETUP_BASE_IDX 2 |
| #define regDC_I2C_DDC3_SPEED 0x1ea6 |
| #define regDC_I2C_DDC3_SPEED_BASE_IDX 2 |
| #define regDC_I2C_DDC3_SETUP 0x1ea7 |
| #define regDC_I2C_DDC3_SETUP_BASE_IDX 2 |
| #define regDC_I2C_DDC4_SPEED 0x1ea8 |
| #define regDC_I2C_DDC4_SPEED_BASE_IDX 2 |
| #define regDC_I2C_DDC4_SETUP 0x1ea9 |
| #define regDC_I2C_DDC4_SETUP_BASE_IDX 2 |
| #define regDC_I2C_DDC5_SPEED 0x1eaa |
| #define regDC_I2C_DDC5_SPEED_BASE_IDX 2 |
| #define regDC_I2C_DDC5_SETUP 0x1eab |
| #define regDC_I2C_DDC5_SETUP_BASE_IDX 2 |
| #define regDC_I2C_TRANSACTION0 0x1eae |
| #define regDC_I2C_TRANSACTION0_BASE_IDX 2 |
| #define regDC_I2C_TRANSACTION1 0x1eaf |
| #define regDC_I2C_TRANSACTION1_BASE_IDX 2 |
| #define regDC_I2C_TRANSACTION2 0x1eb0 |
| #define regDC_I2C_TRANSACTION2_BASE_IDX 2 |
| #define regDC_I2C_TRANSACTION3 0x1eb1 |
| #define regDC_I2C_TRANSACTION3_BASE_IDX 2 |
| #define regDC_I2C_DATA 0x1eb2 |
| #define regDC_I2C_DATA_BASE_IDX 2 |
| #define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 |
| #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 |
| #define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 |
| #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dio_misc_dispdec |
| // base address: 0x0 |
| #define regDIO_SCRATCH0 0x1eca |
| #define regDIO_SCRATCH0_BASE_IDX 2 |
| #define regDIO_SCRATCH1 0x1ecb |
| #define regDIO_SCRATCH1_BASE_IDX 2 |
| #define regDIO_SCRATCH2 0x1ecc |
| #define regDIO_SCRATCH2_BASE_IDX 2 |
| #define regDIO_SCRATCH3 0x1ecd |
| #define regDIO_SCRATCH3_BASE_IDX 2 |
| #define regDIO_SCRATCH4 0x1ece |
| #define regDIO_SCRATCH4_BASE_IDX 2 |
| #define regDIO_SCRATCH5 0x1ecf |
| #define regDIO_SCRATCH5_BASE_IDX 2 |
| #define regDIO_SCRATCH6 0x1ed0 |
| #define regDIO_SCRATCH6_BASE_IDX 2 |
| #define regDIO_SCRATCH7 0x1ed1 |
| #define regDIO_SCRATCH7_BASE_IDX 2 |
| #define regDIO_MEM_PWR_STATUS 0x1edd |
| #define regDIO_MEM_PWR_STATUS_BASE_IDX 2 |
| #define regDIO_MEM_PWR_CTRL 0x1ede |
| #define regDIO_MEM_PWR_CTRL_BASE_IDX 2 |
| #define regDIO_MEM_PWR_CTRL2 0x1edf |
| #define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 |
| #define regDIO_CLK_CNTL 0x1ee0 |
| #define regDIO_CLK_CNTL_BASE_IDX 2 |
| #define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 |
| #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 |
| #define regDIG_SOFT_RESET 0x1eee |
| #define regDIG_SOFT_RESET_BASE_IDX 2 |
| #define regDIO_CLK_CNTL2 0x1ef2 |
| #define regDIO_CLK_CNTL2_BASE_IDX 2 |
| #define regDIO_CLK_CNTL3 0x1ef3 |
| #define regDIO_CLK_CNTL3_BASE_IDX 2 |
| #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff |
| #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 |
| #define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 |
| #define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 |
| #define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 |
| #define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 |
| #define regDIO_LINKA_CNTL 0x1f04 |
| #define regDIO_LINKA_CNTL_BASE_IDX 2 |
| #define regDIO_LINKB_CNTL 0x1f05 |
| #define regDIO_LINKB_CNTL_BASE_IDX 2 |
| #define regDIO_LINKC_CNTL 0x1f06 |
| #define regDIO_LINKC_CNTL_BASE_IDX 2 |
| #define regDIO_LINKD_CNTL 0x1f07 |
| #define regDIO_LINKD_CNTL_BASE_IDX 2 |
| #define regDIO_LINKE_CNTL 0x1f08 |
| #define regDIO_LINKE_CNTL_BASE_IDX 2 |
| #define regDIO_LINKF_CNTL 0x1f09 |
| #define regDIO_LINKF_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x7d10 |
| #define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 |
| #define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 |
| #define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 |
| #define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_CNTL 0x1f47 |
| #define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 |
| #define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 |
| #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a |
| #define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_HI 0x1f4b |
| #define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON18_PERFMON_LOW 0x1f4c |
| #define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_dispdec |
| // base address: 0x0 |
| #define regDC_GENERICA 0x2868 |
| #define regDC_GENERICA_BASE_IDX 2 |
| #define regDC_GENERICB 0x2869 |
| #define regDC_GENERICB_BASE_IDX 2 |
| #define regDCIO_CLOCK_CNTL 0x286a |
| #define regDCIO_CLOCK_CNTL_BASE_IDX 2 |
| #define regDC_REF_CLK_CNTL 0x286b |
| #define regDC_REF_CLK_CNTL_BASE_IDX 2 |
| #define regUNIPHYA_LINK_CNTL 0x286d |
| #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 |
| #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e |
| #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
| #define regUNIPHYB_LINK_CNTL 0x286f |
| #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 |
| #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 |
| #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
| #define regUNIPHYC_LINK_CNTL 0x2871 |
| #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 |
| #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 |
| #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
| #define regUNIPHYD_LINK_CNTL 0x2873 |
| #define regUNIPHYD_LINK_CNTL_BASE_IDX 2 |
| #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 |
| #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
| #define regUNIPHYE_LINK_CNTL 0x2875 |
| #define regUNIPHYE_LINK_CNTL_BASE_IDX 2 |
| #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 |
| #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
| #define regDCIO_WRCMD_DELAY 0x287e |
| #define regDCIO_WRCMD_DELAY_BASE_IDX 2 |
| #define regDC_PINSTRAPS 0x2880 |
| #define regDC_PINSTRAPS_BASE_IDX 2 |
| #define regINTERCEPT_STATE 0x2884 |
| #define regINTERCEPT_STATE_BASE_IDX 2 |
| #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b |
| #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 |
| #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c |
| #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 |
| #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d |
| #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 |
| #define regDCIO_SOFT_RESET 0x289e |
| #define regDCIO_SOFT_RESET_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_chip_dispdec |
| // base address: 0x0 |
| #define regDC_GPIO_GENERIC_MASK 0x28c8 |
| #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 |
| #define regDC_GPIO_GENERIC_A 0x28c9 |
| #define regDC_GPIO_GENERIC_A_BASE_IDX 2 |
| #define regDC_GPIO_GENERIC_EN 0x28ca |
| #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 |
| #define regDC_GPIO_GENERIC_Y 0x28cb |
| #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDC1_MASK 0x28d0 |
| #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDC1_A 0x28d1 |
| #define regDC_GPIO_DDC1_A_BASE_IDX 2 |
| #define regDC_GPIO_DDC1_EN 0x28d2 |
| #define regDC_GPIO_DDC1_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDC1_Y 0x28d3 |
| #define regDC_GPIO_DDC1_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDC2_MASK 0x28d4 |
| #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDC2_A 0x28d5 |
| #define regDC_GPIO_DDC2_A_BASE_IDX 2 |
| #define regDC_GPIO_DDC2_EN 0x28d6 |
| #define regDC_GPIO_DDC2_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDC2_Y 0x28d7 |
| #define regDC_GPIO_DDC2_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDC3_MASK 0x28d8 |
| #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDC3_A 0x28d9 |
| #define regDC_GPIO_DDC3_A_BASE_IDX 2 |
| #define regDC_GPIO_DDC3_EN 0x28da |
| #define regDC_GPIO_DDC3_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDC3_Y 0x28db |
| #define regDC_GPIO_DDC3_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDC4_MASK 0x28dc |
| #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDC4_A 0x28dd |
| #define regDC_GPIO_DDC4_A_BASE_IDX 2 |
| #define regDC_GPIO_DDC4_EN 0x28de |
| #define regDC_GPIO_DDC4_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDC4_Y 0x28df |
| #define regDC_GPIO_DDC4_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDC5_MASK 0x28e0 |
| #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDC5_A 0x28e1 |
| #define regDC_GPIO_DDC5_A_BASE_IDX 2 |
| #define regDC_GPIO_DDC5_EN 0x28e2 |
| #define regDC_GPIO_DDC5_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDC5_Y 0x28e3 |
| #define regDC_GPIO_DDC5_Y_BASE_IDX 2 |
| #define regDC_GPIO_DDCVGA_MASK 0x28e8 |
| #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 |
| #define regDC_GPIO_DDCVGA_A 0x28e9 |
| #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 |
| #define regDC_GPIO_DDCVGA_EN 0x28ea |
| #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 |
| #define regDC_GPIO_DDCVGA_Y 0x28eb |
| #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 |
| #define regDC_GPIO_GENLK_MASK 0x28f0 |
| #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 |
| #define regDC_GPIO_GENLK_A 0x28f1 |
| #define regDC_GPIO_GENLK_A_BASE_IDX 2 |
| #define regDC_GPIO_GENLK_EN 0x28f2 |
| #define regDC_GPIO_GENLK_EN_BASE_IDX 2 |
| #define regDC_GPIO_GENLK_Y 0x28f3 |
| #define regDC_GPIO_GENLK_Y_BASE_IDX 2 |
| #define regDC_GPIO_HPD_MASK 0x28f4 |
| #define regDC_GPIO_HPD_MASK_BASE_IDX 2 |
| #define regDC_GPIO_HPD_A 0x28f5 |
| #define regDC_GPIO_HPD_A_BASE_IDX 2 |
| #define regDC_GPIO_HPD_EN 0x28f6 |
| #define regDC_GPIO_HPD_EN_BASE_IDX 2 |
| #define regDC_GPIO_HPD_Y 0x28f7 |
| #define regDC_GPIO_HPD_Y_BASE_IDX 2 |
| #define regDC_GPIO_PWRSEQ0_EN 0x28fa |
| #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 |
| #define regDC_GPIO_PAD_STRENGTH_1 0x28fc |
| #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 |
| #define regDC_GPIO_PAD_STRENGTH_2 0x28fd |
| #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 |
| #define regPHY_AUX_CNTL 0x28ff |
| #define regPHY_AUX_CNTL_BASE_IDX 2 |
| #define regDC_GPIO_PWRSEQ1_EN 0x2902 |
| #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 |
| #define regDC_GPIO_TX12_EN 0x2915 |
| #define regDC_GPIO_TX12_EN_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_0 0x2916 |
| #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_1 0x2917 |
| #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_2 0x2918 |
| #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 |
| #define regDC_GPIO_RXEN 0x2919 |
| #define regDC_GPIO_RXEN_BASE_IDX 2 |
| #define regDC_GPIO_PULLUPEN 0x291a |
| #define regDC_GPIO_PULLUPEN_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_3 0x291b |
| #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_4 0x291c |
| #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 |
| #define regDC_GPIO_AUX_CTRL_5 0x291d |
| #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 |
| #define regAUXI2C_PAD_ALL_PWR_OK 0x291e |
| #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec |
| // base address: 0x360 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 |
| #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec |
| // base address: 0x6c0 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 |
| #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec |
| // base address: 0xa20 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 |
| #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec |
| // base address: 0xd80 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 |
| #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec |
| // base address: 0x0 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 |
| #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 |
| #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 |
| #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 |
| #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 |
| #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 |
| #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
| #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 |
| #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 |
| #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a |
| #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 |
| #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b |
| #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
| #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c |
| #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
| #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d |
| #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
| #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 |
| #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec |
| // base address: 0x1b0 |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f |
| #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 |
| #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 |
| #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 |
| #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 |
| #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 |
| #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
| #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 |
| #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 |
| #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 |
| #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 |
| #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 |
| #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
| #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 |
| #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
| #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 |
| #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
| #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d |
| #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec |
| // base address: 0x0 |
| #define regDSCC0_DSCC_CONFIG0 0x300a |
| #define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 |
| #define regDSCC0_DSCC_CONFIG1 0x300b |
| #define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 |
| #define regDSCC0_DSCC_STATUS 0x300c |
| #define regDSCC0_DSCC_STATUS_BASE_IDX 2 |
| #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d |
| #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG0 0x300e |
| #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG1 0x300f |
| #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG2 0x3010 |
| #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG3 0x3011 |
| #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG4 0x3012 |
| #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG5 0x3013 |
| #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG6 0x3014 |
| #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG7 0x3015 |
| #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG8 0x3016 |
| #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG9 0x3017 |
| #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG10 0x3018 |
| #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG11 0x3019 |
| #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG12 0x301a |
| #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG13 0x301b |
| #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG14 0x301c |
| #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG15 0x301d |
| #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG16 0x301e |
| #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG17 0x301f |
| #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG18 0x3020 |
| #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG19 0x3021 |
| #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG20 0x3022 |
| #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG21 0x3023 |
| #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 |
| #define regDSCC0_DSCC_PPS_CONFIG22 0x3024 |
| #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 |
| #define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 |
| #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 |
| #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 |
| #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 |
| #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 |
| #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a |
| #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b |
| #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c |
| #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
| #define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d |
| #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e |
| #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f |
| #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 |
| #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 |
| #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 |
| #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a |
| #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec |
| // base address: 0x0 |
| #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 |
| #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 |
| #define regDSCCIF0_DSCCIF_CONFIG1 0x3006 |
| #define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec |
| // base address: 0x0 |
| #define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 |
| #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 |
| #define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 |
| #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xc140 |
| #define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 |
| #define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 |
| #define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 |
| #define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_CNTL 0x3053 |
| #define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_CNTL2 0x3054 |
| #define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 |
| #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 |
| #define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_HI 0x3057 |
| #define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON19_PERFMON_LOW 0x3058 |
| #define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec |
| // base address: 0x170 |
| #define regDSCC1_DSCC_CONFIG0 0x3066 |
| #define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 |
| #define regDSCC1_DSCC_CONFIG1 0x3067 |
| #define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 |
| #define regDSCC1_DSCC_STATUS 0x3068 |
| #define regDSCC1_DSCC_STATUS_BASE_IDX 2 |
| #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 |
| #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG0 0x306a |
| #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG1 0x306b |
| #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG2 0x306c |
| #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG3 0x306d |
| #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG4 0x306e |
| #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG5 0x306f |
| #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG6 0x3070 |
| #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG7 0x3071 |
| #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG8 0x3072 |
| #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG9 0x3073 |
| #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG10 0x3074 |
| #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG11 0x3075 |
| #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG12 0x3076 |
| #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG13 0x3077 |
| #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG14 0x3078 |
| #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG15 0x3079 |
| #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG16 0x307a |
| #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG17 0x307b |
| #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG18 0x307c |
| #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG19 0x307d |
| #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG20 0x307e |
| #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG21 0x307f |
| #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 |
| #define regDSCC1_DSCC_PPS_CONFIG22 0x3080 |
| #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 |
| #define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 |
| #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 |
| #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 |
| #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 |
| #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 |
| #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 |
| #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 |
| #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 |
| #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
| #define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 |
| #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a |
| #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b |
| #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c |
| #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d |
| #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 |
| #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 |
| #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec |
| // base address: 0x170 |
| #define regDSCCIF1_DSCCIF_CONFIG0 0x3061 |
| #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 |
| #define regDSCCIF1_DSCCIF_CONFIG1 0x3062 |
| #define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec |
| // base address: 0x170 |
| #define regDSC_TOP1_DSC_TOP_CONTROL 0x305c |
| #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 |
| #define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d |
| #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xc2b0 |
| #define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac |
| #define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad |
| #define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae |
| #define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_CNTL 0x30af |
| #define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 |
| #define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 |
| #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 |
| #define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_HI 0x30b3 |
| #define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON20_PERFMON_LOW 0x30b4 |
| #define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec |
| // base address: 0x2e0 |
| #define regDSCC2_DSCC_CONFIG0 0x30c2 |
| #define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 |
| #define regDSCC2_DSCC_CONFIG1 0x30c3 |
| #define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 |
| #define regDSCC2_DSCC_STATUS 0x30c4 |
| #define regDSCC2_DSCC_STATUS_BASE_IDX 2 |
| #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 |
| #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 |
| #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 |
| #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 |
| #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 |
| #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG4 0x30ca |
| #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG5 0x30cb |
| #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG6 0x30cc |
| #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG7 0x30cd |
| #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG8 0x30ce |
| #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG9 0x30cf |
| #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 |
| #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 |
| #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 |
| #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 |
| #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 |
| #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 |
| #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 |
| #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 |
| #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 |
| #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 |
| #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG20 0x30da |
| #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG21 0x30db |
| #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 |
| #define regDSCC2_DSCC_PPS_CONFIG22 0x30dc |
| #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 |
| #define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd |
| #define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de |
| #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df |
| #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 |
| #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 |
| #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 |
| #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
| #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 |
| #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
| #define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 |
| #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
| #define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 |
| #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 |
| #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 |
| #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 |
| #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 |
| #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed |
| #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
| #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 |
| #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec |
| // base address: 0x2e0 |
| #define regDSCCIF2_DSCCIF_CONFIG0 0x30bd |
| #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 |
| #define regDSCCIF2_DSCCIF_CONFIG1 0x30be |
| #define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec |
| // base address: 0x2e0 |
| #define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 |
| #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 |
| #define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 |
| #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
| // base address: 0xc420 |
| #define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 |
| #define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 |
| #define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a |
| #define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_CNTL 0x310b |
| #define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_CNTL2 0x310c |
| #define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d |
| #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e |
| #define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_HI 0x310f |
| #define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 |
| #define regDC_PERFMON21_PERFMON_LOW 0x3110 |
| #define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_hpo_top_dispdec |
| // base address: 0x2790c |
| #define regHPO_TOP_CLOCK_CONTROL 0x0e43 |
| #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 |
| #define regHPO_TOP_HW_CONTROL 0x0e4a |
| #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec |
| // base address: 0x27958 |
| #define regDP_STREAM_MAPPER_CONTROL0 0x0e56 |
| #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 |
| #define regDP_STREAM_MAPPER_CONTROL1 0x0e57 |
| #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 |
| #define regDP_STREAM_MAPPER_CONTROL2 0x0e58 |
| #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 |
| #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 |
| #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec |
| // base address: 0x1a698 |
| #define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 |
| #define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 |
| #define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 |
| #define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_CNTL 0x0e69 |
| #define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a |
| #define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b |
| #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c |
| #define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_HI 0x0e6d |
| #define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 |
| #define regDC_PERFMON22_PERFMON_LOW 0x0e6e |
| #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec |
| // base address: 0x2646c |
| #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c |
| #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d |
| #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_INFO0 0x091e |
| #define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_INFO1 0x091f |
| #define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 |
| #define regAFMT5_AFMT_60958_0 0x0920 |
| #define regAFMT5_AFMT_60958_0_BASE_IDX 3 |
| #define regAFMT5_AFMT_60958_1 0x0921 |
| #define regAFMT5_AFMT_60958_1_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 |
| #define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 |
| #define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 |
| #define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 |
| #define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 |
| #define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 |
| #define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 |
| #define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 |
| #define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 |
| #define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 |
| #define regAFMT5_AFMT_60958_2 0x0927 |
| #define regAFMT5_AFMT_60958_2_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 |
| #define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 |
| #define regAFMT5_AFMT_STATUS 0x0929 |
| #define regAFMT5_AFMT_STATUS_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a |
| #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 |
| #define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b |
| #define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 |
| #define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c |
| #define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 |
| #define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d |
| #define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 |
| #define regAFMT5_AFMT_MEM_PWR 0x092f |
| #define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec |
| // base address: 0x264f0 |
| #define regDME5_DME_CONTROL 0x093c |
| #define regDME5_DME_CONTROL_BASE_IDX 3 |
| #define regDME5_DME_MEMORY_CONTROL 0x093d |
| #define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec |
| // base address: 0x264c4 |
| #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 |
| #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 |
| #define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 |
| #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 |
| #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 |
| #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 |
| #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 |
| #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 |
| #define regVPG5_VPG_GENERIC_STATUS 0x0935 |
| #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 |
| #define regVPG5_VPG_MEM_PWR 0x0936 |
| #define regVPG5_VPG_MEM_PWR_BASE_IDX 3 |
| #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 |
| #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 |
| #define regVPG5_VPG_ISRC1_2_DATA 0x0938 |
| #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 |
| #define regVPG5_VPG_MPEG_INFO0 0x0939 |
| #define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 |
| #define regVPG5_VPG_MPEG_INFO1 0x093a |
| #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec |
| // base address: 0x1ab8c |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 |
| #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec |
| // base address: 0x1abc0 |
| #define regAPG0_APG_CONTROL 0x3630 |
| #define regAPG0_APG_CONTROL_BASE_IDX 2 |
| #define regAPG0_APG_CONTROL2 0x3631 |
| #define regAPG0_APG_CONTROL2_BASE_IDX 2 |
| #define regAPG0_APG_DBG_GEN_CONTROL 0x3632 |
| #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
| #define regAPG0_APG_PACKET_CONTROL 0x3633 |
| #define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 |
| #define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a |
| #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b |
| #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
| #define regAPG0_APG_AUDIO_CRC_RESULT 0x363c |
| #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAPG0_APG_STATUS 0x3641 |
| #define regAPG0_APG_STATUS_BASE_IDX 2 |
| #define regAPG0_APG_STATUS2 0x3642 |
| #define regAPG0_APG_STATUS2_BASE_IDX 2 |
| #define regAPG0_APG_MEM_PWR 0x3644 |
| #define regAPG0_APG_MEM_PWR_BASE_IDX 2 |
| #define regAPG0_APG_SPARE 0x3646 |
| #define regAPG0_APG_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec |
| // base address: 0x1ac38 |
| #define regDME6_DME_CONTROL 0x364e |
| #define regDME6_DME_CONTROL_BASE_IDX 2 |
| #define regDME6_DME_MEMORY_CONTROL 0x364f |
| #define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec |
| // base address: 0x1ac44 |
| #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 |
| #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 |
| #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 |
| #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 |
| #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG6_VPG_GENERIC_STATUS 0x3655 |
| #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG6_VPG_MEM_PWR 0x3656 |
| #define regVPG6_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 |
| #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG6_VPG_ISRC1_2_DATA 0x3658 |
| #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG6_VPG_MPEG_INFO0 0x3659 |
| #define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG6_VPG_MPEG_INFO1 0x365a |
| #define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec |
| // base address: 0x1ac74 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c |
| #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec |
| // base address: 0x1aedc |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc |
| #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec |
| // base address: 0x1af10 |
| #define regAPG1_APG_CONTROL 0x3704 |
| #define regAPG1_APG_CONTROL_BASE_IDX 2 |
| #define regAPG1_APG_CONTROL2 0x3705 |
| #define regAPG1_APG_CONTROL2_BASE_IDX 2 |
| #define regAPG1_APG_DBG_GEN_CONTROL 0x3706 |
| #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
| #define regAPG1_APG_PACKET_CONTROL 0x3707 |
| #define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 |
| #define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e |
| #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f |
| #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
| #define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 |
| #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAPG1_APG_STATUS 0x3715 |
| #define regAPG1_APG_STATUS_BASE_IDX 2 |
| #define regAPG1_APG_STATUS2 0x3716 |
| #define regAPG1_APG_STATUS2_BASE_IDX 2 |
| #define regAPG1_APG_MEM_PWR 0x3718 |
| #define regAPG1_APG_MEM_PWR_BASE_IDX 2 |
| #define regAPG1_APG_SPARE 0x371a |
| #define regAPG1_APG_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec |
| // base address: 0x1af88 |
| #define regDME7_DME_CONTROL 0x3722 |
| #define regDME7_DME_CONTROL_BASE_IDX 2 |
| #define regDME7_DME_MEMORY_CONTROL 0x3723 |
| #define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec |
| // base address: 0x1af94 |
| #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 |
| #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 |
| #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 |
| #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 |
| #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG7_VPG_GENERIC_STATUS 0x3729 |
| #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG7_VPG_MEM_PWR 0x372a |
| #define regVPG7_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b |
| #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG7_VPG_ISRC1_2_DATA 0x372c |
| #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG7_VPG_MPEG_INFO0 0x372d |
| #define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG7_VPG_MPEG_INFO1 0x372e |
| #define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec |
| // base address: 0x1afc4 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 |
| #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec |
| // base address: 0x1b22c |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 |
| #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec |
| // base address: 0x1b260 |
| #define regAPG2_APG_CONTROL 0x37d8 |
| #define regAPG2_APG_CONTROL_BASE_IDX 2 |
| #define regAPG2_APG_CONTROL2 0x37d9 |
| #define regAPG2_APG_CONTROL2_BASE_IDX 2 |
| #define regAPG2_APG_DBG_GEN_CONTROL 0x37da |
| #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
| #define regAPG2_APG_PACKET_CONTROL 0x37db |
| #define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 |
| #define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 |
| #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 |
| #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
| #define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 |
| #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAPG2_APG_STATUS 0x37e9 |
| #define regAPG2_APG_STATUS_BASE_IDX 2 |
| #define regAPG2_APG_STATUS2 0x37ea |
| #define regAPG2_APG_STATUS2_BASE_IDX 2 |
| #define regAPG2_APG_MEM_PWR 0x37ec |
| #define regAPG2_APG_MEM_PWR_BASE_IDX 2 |
| #define regAPG2_APG_SPARE 0x37ee |
| #define regAPG2_APG_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec |
| // base address: 0x1b2d8 |
| #define regDME8_DME_CONTROL 0x37f6 |
| #define regDME8_DME_CONTROL_BASE_IDX 2 |
| #define regDME8_DME_MEMORY_CONTROL 0x37f7 |
| #define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec |
| // base address: 0x1b2e4 |
| #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 |
| #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa |
| #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb |
| #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc |
| #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG8_VPG_GENERIC_STATUS 0x37fd |
| #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG8_VPG_MEM_PWR 0x37fe |
| #define regVPG8_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff |
| #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG8_VPG_ISRC1_2_DATA 0x3800 |
| #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG8_VPG_MPEG_INFO0 0x3801 |
| #define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG8_VPG_MPEG_INFO1 0x3802 |
| #define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec |
| // base address: 0x1b314 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 |
| #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec |
| // base address: 0x1b57c |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 |
| #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec |
| // base address: 0x1b5b0 |
| #define regAPG3_APG_CONTROL 0x38ac |
| #define regAPG3_APG_CONTROL_BASE_IDX 2 |
| #define regAPG3_APG_CONTROL2 0x38ad |
| #define regAPG3_APG_CONTROL2_BASE_IDX 2 |
| #define regAPG3_APG_DBG_GEN_CONTROL 0x38ae |
| #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
| #define regAPG3_APG_PACKET_CONTROL 0x38af |
| #define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 |
| #define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 |
| #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
| #define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 |
| #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
| #define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 |
| #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
| #define regAPG3_APG_STATUS 0x38bd |
| #define regAPG3_APG_STATUS_BASE_IDX 2 |
| #define regAPG3_APG_STATUS2 0x38be |
| #define regAPG3_APG_STATUS2_BASE_IDX 2 |
| #define regAPG3_APG_MEM_PWR 0x38c0 |
| #define regAPG3_APG_MEM_PWR_BASE_IDX 2 |
| #define regAPG3_APG_SPARE 0x38c2 |
| #define regAPG3_APG_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec |
| // base address: 0x1b628 |
| #define regDME9_DME_CONTROL 0x38ca |
| #define regDME9_DME_CONTROL_BASE_IDX 2 |
| #define regDME9_DME_MEMORY_CONTROL 0x38cb |
| #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec |
| // base address: 0x1b634 |
| #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd |
| #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce |
| #define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
| #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf |
| #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 |
| #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
| #define regVPG9_VPG_GENERIC_STATUS 0x38d1 |
| #define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 |
| #define regVPG9_VPG_MEM_PWR 0x38d2 |
| #define regVPG9_VPG_MEM_PWR_BASE_IDX 2 |
| #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 |
| #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
| #define regVPG9_VPG_ISRC1_2_DATA 0x38d4 |
| #define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 |
| #define regVPG9_VPG_MPEG_INFO0 0x38d5 |
| #define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 |
| #define regVPG9_VPG_MPEG_INFO1 0x38d6 |
| #define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec |
| // base address: 0x1b664 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 |
| #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_link_enc0_dispdec |
| // base address: 0x1ad5c |
| #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 |
| #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 |
| #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec |
| // base address: 0x1ae00 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee |
| #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_link_enc1_dispdec |
| // base address: 0x1b0ac |
| #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b |
| #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 |
| #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c |
| #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec |
| // base address: 0x1b150 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 |
| #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 |
| |
| |
| // addressBlock: dce_dc_dchvm_hvm_dispdec |
| // base address: 0x0 |
| #define regDCHVM_CTRL0 0x3603 |
| #define regDCHVM_CTRL0_BASE_IDX 2 |
| #define regDCHVM_CTRL1 0x3604 |
| #define regDCHVM_CTRL1_BASE_IDX 2 |
| #define regDCHVM_CLK_CTRL 0x3605 |
| #define regDCHVM_CLK_CTRL_BASE_IDX 2 |
| #define regDCHVM_MEM_CTRL 0x3606 |
| #define regDCHVM_MEM_CTRL_BASE_IDX 2 |
| #define regDCHVM_RIOMMU_CTRL0 0x3607 |
| #define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 |
| #define regDCHVM_RIOMMU_STAT0 0x3608 |
| #define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 |
| |
| // addressBlock: vga_vgaseqind |
| // base address: 0x0 |
| #define ixSEQ00 0x0000 |
| #define ixSEQ01 0x0001 |
| #define ixSEQ02 0x0002 |
| #define ixSEQ03 0x0003 |
| #define ixSEQ04 0x0004 |
| |
| |
| // addressBlock: vga_vgacrtind |
| // base address: 0x0 |
| #define ixCRT00 0x0000 |
| #define ixCRT01 0x0001 |
| #define ixCRT02 0x0002 |
| #define ixCRT03 0x0003 |
| #define ixCRT04 0x0004 |
| #define ixCRT05 0x0005 |
| #define ixCRT06 0x0006 |
| #define ixCRT07 0x0007 |
| #define ixCRT08 0x0008 |
| #define ixCRT09 0x0009 |
| #define ixCRT0A 0x000a |
| #define ixCRT0B 0x000b |
| #define ixCRT0C 0x000c |
| #define ixCRT0D 0x000d |
| #define ixCRT0E 0x000e |
| #define ixCRT0F 0x000f |
| #define ixCRT10 0x0010 |
| #define ixCRT11 0x0011 |
| #define ixCRT12 0x0012 |
| #define ixCRT13 0x0013 |
| #define ixCRT14 0x0014 |
| #define ixCRT15 0x0015 |
| #define ixCRT16 0x0016 |
| #define ixCRT17 0x0017 |
| #define ixCRT18 0x0018 |
| #define ixCRT1E 0x001e |
| #define ixCRT1F 0x001f |
| #define ixCRT22 0x0022 |
| |
| |
| // addressBlock: vga_vgagrphind |
| // base address: 0x0 |
| #define ixGRA00 0x0000 |
| #define ixGRA01 0x0001 |
| #define ixGRA02 0x0002 |
| #define ixGRA03 0x0003 |
| #define ixGRA04 0x0004 |
| #define ixGRA05 0x0005 |
| #define ixGRA06 0x0006 |
| #define ixGRA07 0x0007 |
| #define ixGRA08 0x0008 |
| |
| |
| // addressBlock: vga_vgaattrind |
| // base address: 0x0 |
| #define ixATTR00 0x0000 |
| #define ixATTR01 0x0001 |
| #define ixATTR02 0x0002 |
| #define ixATTR03 0x0003 |
| #define ixATTR04 0x0004 |
| #define ixATTR05 0x0005 |
| #define ixATTR06 0x0006 |
| #define ixATTR07 0x0007 |
| #define ixATTR08 0x0008 |
| #define ixATTR09 0x0009 |
| #define ixATTR0A 0x000a |
| #define ixATTR0B 0x000b |
| #define ixATTR0C 0x000c |
| #define ixATTR0D 0x000d |
| #define ixATTR0E 0x000e |
| #define ixATTR0F 0x000f |
| #define ixATTR10 0x0010 |
| #define ixATTR11 0x0011 |
| #define ixATTR12 0x0012 |
| #define ixATTR13 0x0013 |
| #define ixATTR14 0x0014 |
| |
| |
| // addressBlock: azendpoint_f2codecind |
| // base address: 0x0 |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e |
| #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 |
| #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 |
| #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 |
| #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a |
| #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 |
| #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 |
| #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e |
| #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 |
| #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c |
| #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e |
| |
| |
| // addressBlock: azendpoint_descriptorind |
| // base address: 0x0 |
| #define ixAUDIO_DESCRIPTOR0 0x0001 |
| #define ixAUDIO_DESCRIPTOR1 0x0002 |
| #define ixAUDIO_DESCRIPTOR2 0x0003 |
| #define ixAUDIO_DESCRIPTOR3 0x0004 |
| #define ixAUDIO_DESCRIPTOR4 0x0005 |
| #define ixAUDIO_DESCRIPTOR5 0x0006 |
| #define ixAUDIO_DESCRIPTOR6 0x0007 |
| #define ixAUDIO_DESCRIPTOR7 0x0008 |
| #define ixAUDIO_DESCRIPTOR8 0x0009 |
| #define ixAUDIO_DESCRIPTOR9 0x000a |
| #define ixAUDIO_DESCRIPTOR10 0x000b |
| #define ixAUDIO_DESCRIPTOR11 0x000c |
| #define ixAUDIO_DESCRIPTOR12 0x000d |
| #define ixAUDIO_DESCRIPTOR13 0x000e |
| |
| |
| // addressBlock: azendpoint_sinkinfoind |
| // base address: 0x0 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 |
| #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 |
| #define ixSINK_DESCRIPTION0 0x0005 |
| #define ixSINK_DESCRIPTION1 0x0006 |
| #define ixSINK_DESCRIPTION2 0x0007 |
| #define ixSINK_DESCRIPTION3 0x0008 |
| #define ixSINK_DESCRIPTION4 0x0009 |
| #define ixSINK_DESCRIPTION5 0x000a |
| #define ixSINK_DESCRIPTION6 0x000b |
| #define ixSINK_DESCRIPTION7 0x000c |
| #define ixSINK_DESCRIPTION8 0x000d |
| #define ixSINK_DESCRIPTION9 0x000e |
| #define ixSINK_DESCRIPTION10 0x000f |
| #define ixSINK_DESCRIPTION11 0x0010 |
| #define ixSINK_DESCRIPTION12 0x0011 |
| #define ixSINK_DESCRIPTION13 0x0012 |
| #define ixSINK_DESCRIPTION14 0x0013 |
| #define ixSINK_DESCRIPTION15 0x0014 |
| #define ixSINK_DESCRIPTION16 0x0015 |
| #define ixSINK_DESCRIPTION17 0x0016 |
| |
| |
| // addressBlock: azf0controller_azinputcrc0resultind |
| // base address: 0x0 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 |
| #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 |
| |
| |
| // addressBlock: azf0controller_azinputcrc1resultind |
| // base address: 0x0 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 |
| #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 |
| |
| |
| // addressBlock: azf0controller_azcrc0resultind |
| // base address: 0x0 |
| #define ixAZALIA_CRC0_CHANNEL0 0x0000 |
| #define ixAZALIA_CRC0_CHANNEL1 0x0001 |
| #define ixAZALIA_CRC0_CHANNEL2 0x0002 |
| #define ixAZALIA_CRC0_CHANNEL3 0x0003 |
| #define ixAZALIA_CRC0_CHANNEL4 0x0004 |
| #define ixAZALIA_CRC0_CHANNEL5 0x0005 |
| #define ixAZALIA_CRC0_CHANNEL6 0x0006 |
| #define ixAZALIA_CRC0_CHANNEL7 0x0007 |
| |
| |
| // addressBlock: azf0controller_azcrc1resultind |
| // base address: 0x0 |
| #define ixAZALIA_CRC1_CHANNEL0 0x0000 |
| #define ixAZALIA_CRC1_CHANNEL1 0x0001 |
| #define ixAZALIA_CRC1_CHANNEL2 0x0002 |
| #define ixAZALIA_CRC1_CHANNEL3 0x0003 |
| #define ixAZALIA_CRC1_CHANNEL4 0x0004 |
| #define ixAZALIA_CRC1_CHANNEL5 0x0005 |
| #define ixAZALIA_CRC1_CHANNEL6 0x0006 |
| #define ixAZALIA_CRC1_CHANNEL7 0x0007 |
| |
| |
| // addressBlock: azinputendpoint_f2codecind |
| // base address: 0x0 |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a |
| #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 |
| #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c |
| |
| |
| // addressBlock: azroot_f2codecind |
| // base address: 0x0 |
| #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 |
| #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 |
| #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 |
| #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff |
| #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 |
| #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 |
| #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a |
| #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b |
| #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f |
| |
| |
| // addressBlock: azf0stream0_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream1_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream2_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream3_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream4_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream5_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream6_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream7_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream8_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream9_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream10_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream11_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream12_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream13_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream14_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0stream15_streamind |
| // base address: 0x0 |
| #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
| #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
| #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
| #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
| #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
| |
| |
| // addressBlock: azf0endpoint0_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint1_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint2_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint3_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint4_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint5_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint6_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0endpoint7_endpointind |
| // base address: 0x0 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
| #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
| #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
| #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
| #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
| #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
| |
| |
| // addressBlock: azf0inputendpoint0_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint1_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint2_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint3_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint4_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint5_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint6_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| // addressBlock: azf0inputendpoint7_inputendpointind |
| // base address: 0x0 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
| #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
| |
| |
| #endif |
