blob: b5e634749665e5fc7d2b49d222fd8f15805156e8 [file] [log] [blame]
/*
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GFX_6_0_SH_MASK_H
#define GFX_6_0_SH_MASK_H
#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000
#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b
#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003
#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004
#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010
#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L
#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003
#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L
#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005
#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L
#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004
#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L
#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009
#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L
#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008
#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L
#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007
#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L
#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a
#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L
#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006
#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L
#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001
#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L
#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b
#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L
#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000
#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L
#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002
#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L
#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004
#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L
#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003
#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L
#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008
#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L
#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001
#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L
#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002
#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L
#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005
#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L
#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006
#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L
#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007
#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L
#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000
#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L
#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004
#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L
#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006
#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L
#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008
#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L
#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005
#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L
#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003
#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L
#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002
#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L
#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000
#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L
#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007
#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L
#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014
#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L
#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016
#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L
#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015
#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L
#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006
#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L
#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010
#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL
#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000
#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L
#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a
#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L
#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003
#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L
#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002
#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L
#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000
#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L
#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005
#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L
#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001
#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L
#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004
#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L
#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007
#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L
#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006
#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL
#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b
#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L
#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c
#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L
#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001
#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L
#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010
#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000
#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004
#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008
#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c
#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010
#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014
#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018
#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c
#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L
#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000
#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL
#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000
#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010
#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016
#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000
#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014
#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L
#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011
#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L
#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d
#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL
#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000
#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L
#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL
#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000
#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L
#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL
#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000
#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L
#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL
#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000
#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L
#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL
#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000
#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L
#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L
#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003
#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L
#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L
#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L
#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L
#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L
#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L
#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L
#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L
#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L
#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000
#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L
#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000
#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL
#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000
#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL
#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000
#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL
#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001
#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010
#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL
#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000
#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L
#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008
#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL
#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000
#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018
#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019
#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016
#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015
#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L
#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c
#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017
#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L
#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a
#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014
#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L
#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006
#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL
#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000
#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d
#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018
#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L
#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f
#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000
#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007
#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008
#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006
#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL
#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000
#define COMPUTE_START_X__START_MASK 0xffffffffL
#define COMPUTE_START_X__START__SHIFT 0x00000000
#define COMPUTE_START_Y__START_MASK 0xffffffffL
#define COMPUTE_START_Y__START__SHIFT 0x00000000
#define COMPUTE_START_Z__START_MASK 0xffffffffL
#define COMPUTE_START_Z__START__SHIFT 0x00000000
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010
#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL
#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000
#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL
#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000
#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL
#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000
#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL
#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000
#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L
#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c
#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL
#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000
#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000
#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL
#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000
#define COMPUTE_VMID__DATA_MASK 0x0000000fL
#define COMPUTE_VMID__DATA__SHIFT 0x00000000
#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002
#define CP_APPEND_DATA__DATA_MASK 0xffffffffL
#define CP_APPEND_DATA__DATA__SHIFT 0x00000000
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL
#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000
#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL
#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000
#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008
#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a
#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e
#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000
#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001
#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013
#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f
#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L
#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000
#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL
#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000
#define CP_COHER_STATUS__MEID_MASK 0x03000000L
#define CP_COHER_STATUS__MEID__SHIFT 0x00000018
#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L
#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e
#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004
#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L
#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000
#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d
#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b
#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015
#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L
#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e
#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c
#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a
#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L
#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000
#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d
#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015
#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L
#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e
#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c
#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a
#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L
#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000
#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L
#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004
#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L
#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000
#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L
#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004
#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L
#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a
#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L
#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010
#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L
#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000
#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L
#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004
#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L
#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a
#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L
#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010
#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L
#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000
#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L
#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004
#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L
#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a
#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L
#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010
#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L
#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002
#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L
#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000
#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL
#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000
#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL
#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000
#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004
#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019
#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008
#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d
#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006
#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002
#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L
#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000
#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000
#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000
#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000
#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000
#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L
#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL
#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L
#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL
#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000
#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL
#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L
#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL
#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000
#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000
#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL
#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L
#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL
#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000
#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000
#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL
#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000
#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L
#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L
#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a
#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL
#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL
#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000
#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL
#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000
#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L
#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008
#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L
#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000
#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL
#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000
#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL
#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000
#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000
#define CP_RINGID__RINGID_MASK 0x00000003L
#define CP_RINGID__RINGID__SHIFT 0x00000000
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000
#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L
#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010
#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL
#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000
#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L
#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL