blob: 4509c8237db508c5e85d3a63dd38814c1e05238a [file] [log] [blame]
/*
* GFX_7_2 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GFX_7_2_SH_MASK_H
#define GFX_7_2_SH_MASK_H
#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE_MASK 0x70
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1
#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2
#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4
#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8
#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10
#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20
#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40
#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6
#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80
#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7
#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100
#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8
#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200
#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9
#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400
#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa
#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800
#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb
#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1
#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2
#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4
#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8
#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10
#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20
#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40
#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80
#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100
#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3
#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0
#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4
#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2
#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8
#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10
#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20
#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40
#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80
#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100
#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f
#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0
#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0
#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6
#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00
#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa
#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000
#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10
#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1
#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2
#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4
#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8
#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10
#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20
#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5
#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40
#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6
#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80
#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7
#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff
#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0
#define CP_DFY_CNTL__POLICY_MASK 0x300
#define CP_DFY_CNTL__POLICY__SHIFT 0x8
#define CP_DFY_CNTL__VOL_MASK 0x400
#define CP_DFY_CNTL__VOL__SHIFT 0xa
#define CP_DFY_CNTL__ATC_MASK 0x800
#define CP_DFY_CNTL__ATC__SHIFT 0xb
#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000
#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
#define CP_DFY_STAT__BUSY_MASK 0x80000000
#define CP_DFY_STAT__BUSY__SHIFT 0x1f
#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
#define CP_DFY_DATA_0__DATA__SHIFT 0x0
#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
#define CP_DFY_DATA_1__DATA__SHIFT 0x0
#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
#define CP_DFY_DATA_2__DATA__SHIFT 0x0
#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
#define CP_DFY_DATA_3__DATA__SHIFT 0x0
#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
#define CP_DFY_DATA_4__DATA__SHIFT 0x0
#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
#define CP_DFY_DATA_5__DATA__SHIFT 0x0
#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
#define CP_DFY_DATA_6__DATA__SHIFT 0x0
#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
#define CP_DFY_DATA_7__DATA__SHIFT 0x0
#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
#define CP_DFY_DATA_8__DATA__SHIFT 0x0
#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
#define CP_DFY_DATA_9__DATA__SHIFT 0x0
#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
#define CP_DFY_DATA_10__DATA__SHIFT 0x0
#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
#define CP_DFY_DATA_11__DATA__SHIFT 0x0
#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
#define CP_DFY_DATA_12__DATA__SHIFT 0x0
#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
#define CP_DFY_DATA_13__DATA__SHIFT 0x0
#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
#define CP_DFY_DATA_14__DATA__SHIFT 0x0
#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
#define CP_DFY_DATA_15__DATA__SHIFT 0x0
#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000
#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000
#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000
#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000
#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000
#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc
#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2
#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff
#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
#define CP_RB_VMID__RB0_VMID_MASK 0xf
#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
#define CP_RB_VMID__RB1_VMID_MASK 0xf00
#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1
#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00
#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00
#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00
#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00
#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10
#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1
#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000
#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10
#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100
#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8
#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200
#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1
#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0
#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2
#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4
#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2
#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8
#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10
#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f
#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000
#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000
#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3
#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
#define CP_APPEND_DATA__DATA_MASK 0xffffffff
#define CP_APPEND_DATA__DATA__SHIFT 0x0
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000
#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
#define CP_COHER_STATUS__MEID_MASK 0x3000000
#define CP_COHER_STATUS__MEID__SHIFT 0x18
#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
#define CP_COHER_STATUS__STATUS_MASK 0x80000000
#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000
#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf
#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000
#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b
#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000
#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf
#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000
#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b
#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000
#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000
#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000
#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10
#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000
#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40
#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6
#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80
#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100
#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1