blob: 4070ca3a68eb9b361a45303d3ee5c44571a7f55c [file] [log] [blame]
/*
* GFX_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GFX_8_0_SH_MASK_H
#define GFX_8_0_SH_MASK_H
#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE_MASK 0x70
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
#define CP_DFY_CNTL__POLICY_MASK 0x1
#define CP_DFY_CNTL__POLICY__SHIFT 0x0
#define CP_DFY_CNTL__MTYPE_MASK 0xc
#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
#define CP_DFY_CNTL__MODE_MASK 0x60000000
#define CP_DFY_CNTL__MODE__SHIFT 0x1d
#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
#define CP_DFY_STAT__BUSY_MASK 0x80000000
#define CP_DFY_STAT__BUSY__SHIFT 0x1f
#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
#define CP_DFY_DATA_0__DATA__SHIFT 0x0
#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
#define CP_DFY_DATA_1__DATA__SHIFT 0x0
#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
#define CP_DFY_DATA_2__DATA__SHIFT 0x0
#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
#define CP_DFY_DATA_3__DATA__SHIFT 0x0
#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
#define CP_DFY_DATA_4__DATA__SHIFT 0x0
#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
#define CP_DFY_DATA_5__DATA__SHIFT 0x0
#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
#define CP_DFY_DATA_6__DATA__SHIFT 0x0
#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
#define CP_DFY_DATA_7__DATA__SHIFT 0x0
#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
#define CP_DFY_DATA_8__DATA__SHIFT 0x0
#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
#define CP_DFY_DATA_9__DATA__SHIFT 0x0
#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
#define CP_DFY_DATA_10__DATA__SHIFT 0x0
#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
#define CP_DFY_DATA_11__DATA__SHIFT 0x0
#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
#define CP_DFY_DATA_12__DATA__SHIFT 0x0
#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
#define CP_DFY_DATA_13__DATA__SHIFT 0x0
#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
#define CP_DFY_DATA_14__DATA__SHIFT 0x0
#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
#define CP_DFY_DATA_15__DATA__SHIFT 0x0
#define CP_DFY_CMD__OFFSET_MASK 0x1ff
#define CP_DFY_CMD__OFFSET__SHIFT 0x0
#define CP_DFY_CMD__SIZE_MASK 0xffff0000
#define CP_DFY_CMD__SIZE__SHIFT 0x10
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB0_CNTL__MTYPE_MASK 0x18000
#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB_CNTL__MTYPE_MASK 0x18000
#define CP_RB_CNTL__MTYPE__SHIFT 0xf
#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB1_CNTL__MTYPE_MASK 0x18000
#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB2_CNTL__MTYPE_MASK 0x18000
#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
#define CP_RB_VMID__RB0_VMID_MASK 0xf
#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
#define CP_RB_VMID__RB1_VMID_MASK 0xf00
#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT