| /* |
| * GMC_8_1 Register documentation |
| * |
| * Copyright (C) 2014 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #ifndef GMC_8_1_SH_MASK_H |
| #define GMC_8_1_SH_MASK_H |
| |
| #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 |
| #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 |
| #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 |
| #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 |
| #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 |
| #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 |
| #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 |
| #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 |
| #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 |
| #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 |
| #define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 |
| #define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 |
| #define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 |
| #define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 |
| #define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 |
| #define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 |
| #define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 |
| #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 |
| #define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 |
| #define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f |
| #define MC_ARB_ATOMIC__TC_GRP_MASK 0x7 |
| #define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0 |
| #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8 |
| #define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3 |
| #define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70 |
| #define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4 |
| #define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80 |
| #define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7 |
| #define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00 |
| #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8 |
| #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000 |
| #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 |
| #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 |
| #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf |
| #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 |
| #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 |
| #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 |
| #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 |
| #define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 |
| #define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 |
| #define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 |
| #define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 |
| #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 |
| #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 |
| #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 |
| #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 |
| #define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff |
| #define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 |
| #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 |
| #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa |
| #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 |
| #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 |
| #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd |
| #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000 |
| #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe |
| #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000 |
| #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf |
| #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000 |
| #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10 |
| #define MC_ARB_FED_CNTL__MODE_MASK 0x3 |
| #define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 |
| #define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc |
| #define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 |
| #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 |
| #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 |
| #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 |
| #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 |
| #define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 |
| #define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 |
| #define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 |
| #define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 |
| #define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 |
| #define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 |
| #define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 |
| #define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 |
| #define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 |
| #define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 |
| #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 |
| #define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 |
| #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 |
| #define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 |
| #define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 |
| #define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 |
| #define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 |
| #define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 |
| #define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 |
| #define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 |
| #define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 |
| #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 |
| #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 |
| #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 |
| #define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 |
| #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa |
| #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 |
| #define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb |
| #define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 |
| #define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc |
| #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 |
| #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd |
| #define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 |
| #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe |
| #define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 |
| #define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 |
| #define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 |
| #define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 |
| #define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 |
| #define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 |
| #define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 |
| #define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 |
| #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d |
| #define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf |
| #define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 |
| #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 |
| #define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 |
| #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 |
| #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 |
| #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 |
| #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 |
| #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 |
| #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 |
| #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 |
| #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 |
| #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 |
| #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 |
| #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 |
| #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa |
| #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 |
| #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb |
| #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 |
| #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc |
| #define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 |
| #define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd |
| #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 |
| #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 |
| #define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 |
| #define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 |
| #define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 |
| #define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 |
| #define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 |
| #define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 |
| #define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff |
| #define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 |
| #define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 |
| #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 |
| #define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 |
| #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 |
| #define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 |
| #define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 |
| #define MC_ARB_PERF_CID__CH0_MASK 0xff |
| #define MC_ARB_PERF_CID__CH0__SHIFT 0x0 |
| #define MC_ARB_PERF_CID__CH1_MASK 0xff00 |
| #define MC_ARB_PERF_CID__CH1__SHIFT 0x8 |
| #define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 |
| #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 |
| #define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 |
| #define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 |
| #define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7 |
| #define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0 |
| #define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8 |
| #define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3 |
| #define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70 |
| #define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4 |
| #define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80 |
| #define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7 |
| #define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700 |
| #define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8 |
| #define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800 |
| #define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb |
| #define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000 |
| #define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc |
| #define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000 |
| #define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf |
| #define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000 |
| #define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10 |
| #define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000 |
| #define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18 |
| #define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff |
| #define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0 |
| #define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00 |
| #define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8 |
| #define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000 |
| #define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10 |
| #define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000 |
| #define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18 |
| #define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000 |
| #define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a |
| #define MC_ARB_GECC2__ENABLE_MASK 0x1 |
| #define MC_ARB_GECC2__ENABLE__SHIFT 0x0 |
| #define MC_ARB_GECC2__ECC_MODE_MASK 0x6 |
| #define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 |
| #define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 |
| #define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 |
| #define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 |
| #define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 |
| #define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 |
| #define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 |
| #define MC_ARB_GECC2__READ_ERR_MASK 0x3800 |
| #define MC_ARB_GECC2__READ_ERR__SHIFT 0xb |
| #define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 |
| #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe |
| #define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 |
| #define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf |
| #define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 |
| #define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 |
| #define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 |
| #define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 |
| #define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 |
| #define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf |
| #define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 |
| #define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 |
| #define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 |
| #define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 |
| #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 |
| #define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 |
| #define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc |
| #define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 |
| #define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 |
| #define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 |
| #define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 |
| #define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 |
| #define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 |
| #define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 |
| #define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c |
| #define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf |
| #define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 |
| #define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 |
| #define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 |
| #define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 |
| #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 |
| #define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 |
| #define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc |
| #define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 |
| #define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 |
| #define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 |
| #define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 |
| #define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 |
| #define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 |
| #define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8 |
| #define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3 |
| #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10 |
| #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4 |
| #define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0 |
| #define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5 |
| #define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff |
| #define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0 |
| #define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00 |
| #define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8 |
| #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000 |
| #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10 |
| #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000 |
| #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18 |
| #define MC_ARB_RTT_DATA__PATTERN_MASK 0xff |
| #define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 |
| #define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 |
| #define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 |
| #define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 |
| #define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 |
| #define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc |
| #define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 |
| #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 |
| #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 |
| #define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 |
| #define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 |
| #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 |
| #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 |
| #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 |
| #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 |
| #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa |
| #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 |
| #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb |
| #define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 |
| #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 |
| #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 |
| #define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 |
| #define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 |
| #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 |
| #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 |
| #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 |
| #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 |
| #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 |
| #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 |
| #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 |
| #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 |
| #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 |
| #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 |
| #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e |
| #define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f |
| #define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 |
| #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 |
| #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 |
| #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 |
| #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc |
| #define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 |
| #define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd |
| #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 |
| #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 |
| #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc |
| #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 |
| #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 |
| #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 |
| #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 |
| #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc |
| #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 |
| #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 |
| #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 |
| #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 |
| #define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 |
| #define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 |
| #define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e |
| #define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 |
| #define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 |
| #define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 |
| #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 |
| #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 |
| #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa |
| #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 |
| #define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb |
| #define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 |
| #define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc |
| #define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 |
| #define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd |
| #define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 |
| #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe |
| #define MC_ARB_MISC2__GECC_MASK 0x40000 |
| #define MC_ARB_MISC2__GECC__SHIFT 0x12 |
| #define MC_ARB_MISC2__GECC_RST_MASK 0x80000 |
| #define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 |
| #define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 |
| #define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 |
| #define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 |
| #define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 |
| #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 |
| #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 |
| #define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 |
| #define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c |
| #define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 |
| #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d |
| #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 |
| #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e |
| #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 |
| #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f |
| #define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 |
| #define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 |
| #define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 |
| #define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 |
| #define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 |
| #define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 |
| #define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 |
| #define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 |
| #define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 |
| #define MC_ARB_MISC__HARSHNESS__SHIFT 0xb |
| #define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 |
| #define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 |
| #define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 |
| #define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 |
| #define MC_ARB_MISC__CALI_RATES_MASK 0x600000 |
| #define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 |
| #define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 |
| #define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 |
| #define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 |
| #define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 |
| #define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 |
| #define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 |
| #define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 |
| #define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a |
| #define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 |
| #define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e |
| #define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 |
| #define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f |
| #define MC_ARB_BANKMAP__BANK0_MASK 0xf |
| #define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 |
| #define MC_ARB_BANKMAP__BANK1_MASK 0xf0 |
| #define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 |
| #define MC_ARB_BANKMAP__BANK2_MASK 0xf00 |
| #define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 |
| #define MC_ARB_BANKMAP__BANK3_MASK 0xf000 |
| #define MC_ARB_BANKMAP__BANK3__SHIFT 0xc |
| #define MC_ARB_BANKMAP__RANK_MASK 0xf0000 |
| #define MC_ARB_BANKMAP__RANK__SHIFT 0x10 |
| #define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 |
| #define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 |
| #define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 |
| #define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 |
| #define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 |
| #define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 |
| #define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 |
| #define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 |
| #define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 |
| #define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 |
| #define MC_ARB_RAMCFG__RSV_1_MASK 0x200 |
| #define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 |
| #define MC_ARB_RAMCFG__RSV_2_MASK 0x400 |
| #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa |
| #define MC_ARB_RAMCFG__RSV_3_MASK 0x800 |
| #define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb |
| #define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 |
| #define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc |
| #define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 |
| #define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd |
| #define MC_ARB_POP__ENABLE_ARB_MASK 0x1 |
| #define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 |
| #define MC_ARB_POP__SPEC_OPEN_MASK 0x2 |
| #define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 |
| #define MC_ARB_POP__POP_DEPTH_MASK 0x3c |
| #define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 |
| #define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 |
| #define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 |
| #define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 |
| #define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc |
| #define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 |
| #define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf |
| #define MC_ARB_POP__QUICK_STOP_MASK 0x20000 |
| #define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 |
| #define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 |
| #define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 |
| #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 |
| #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 |
| #define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff |
| #define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 |
| #define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 |
| #define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 |
| #define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 |
| #define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 |
| #define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 |
| #define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 |
| #define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff |
| #define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 |
| #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 |
| #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 |
| #define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 |
| #define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 |
| #define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 |
| #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa |
| #define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 |
| #define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 |
| #define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 |
| #define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 |
| #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf |
| #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 |
| #define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 |
| #define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 |
| #define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 |
| #define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc |
| #define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff |
| #define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 |
| #define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 |
| #define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 |
| #define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 |
| #define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 |
| #define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 |
| #define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 |
| #define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff |
| #define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 |
| #define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 |
| #define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 |
| #define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 |
| #define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 |
| #define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 |
| #define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 |
| #define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 |
| #define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 |
| #define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 |
| #define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 |
| #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa |
| #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 |
| #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb |
| #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 |
| #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc |
| #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 |
| #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd |
| #define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 |
| #define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 |
| #define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 |
| #define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 |
| #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa |
| #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 |
| #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb |
| #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 |
| #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc |
| #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 |
| #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd |
| #define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 |
| #define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 |
| #define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc |
| #define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 |
| #define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 |
| #define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 |
| #define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 |
| #define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 |
| #define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 |
| #define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 |
| #define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 |
| #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa |
| #define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 |
| #define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc |
| #define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 |
| #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe |
| #define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 |
| #define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 |
| #define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 |
| #define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 |
| #define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc |
| #define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 |
| #define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 |
| #define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 |
| #define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 |
| #define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 |
| #define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 |
| #define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 |
| #define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 |
| #define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa |
| #define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 |
| #define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc |
| #define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 |
| #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe |
| #define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 |
| #define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 |
| #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 |
| #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 |
| #define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 |
| #define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 |
| #define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 |
| #define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 |
| #define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 |
| #define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 |
| #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 |
| #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 |
| #define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 |
| #define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 |
| #define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 |
| #define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 |
| #define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 |
| #define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 |
| #define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff |
| #define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 |
| #define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 |
| #define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 |
| #define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 |
| #define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 |
| #define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 |
| #define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 |
| #define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff |
| #define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 |
| #define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 |
| #define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 |
| #define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 |
| #define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 |
| #define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 |
| #define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 |
| #define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff |
| #define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 |
| #define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 |
| #define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 |
| #define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 |
| #define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 |
| #define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 |
| #define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 |
| #define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff |
| #define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 |
| #define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 |
| #define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 |
| #define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 |
| #define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 |
| #define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 |
| #define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 |
| #define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 |
| #define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 |
| #define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc |
| #define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 |
| #define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 |
| #define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 |
| #define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 |
| #define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 |
| #define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 |
| #define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 |
| #define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 |
| #define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa |
| #define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 |
| #define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc |
| #define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 |
| #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe |
| #define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 |
| #define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 |
| #define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f |
| #define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 |
| #define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 |
| #define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc |
| #define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 |
| #define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 |
| #define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 |
| #define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 |
| #define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 |
| #define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 |
| #define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 |
| #define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 |
| #define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa |
| #define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 |
| #define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc |
| #define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 |
| #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe |
| #define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 |
| #define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 |
| #define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f |
| #define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 |
| #define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 |
| #define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e |
| #define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 |
| #define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 |
| #define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 |
| #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 |
| #define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb |
| #define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 |
| #define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc |
| #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 |
| #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd |
| #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 |
| #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe |
| #define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000 |
| #define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11 |
| #define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff |
| #define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 |
| #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 |
| #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 |
| #define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 |
| #define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 |
| #define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 |
| #define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 |
| #define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 |
| #define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 |
| #define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 |
| #define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 |
| #define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 |
| #define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 |
| #define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 |
| #define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 |
| #define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 |
| #define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa |
| #define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 |
| #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb |
| #define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 |
| #define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc |
| #define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 |
| #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd |
| #define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 |
| #define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe |
| #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 |
| #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf |
| #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000 |
| #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10 |
| #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000 |
| #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 |
| #define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 |
| #define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 |
| #define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 |
| #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000 |
| #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18 |
| #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000 |
| #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19 |
| #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf |
| #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 |
| #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 |
| #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 |
| #define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 |
| #define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 |
| #define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 |
| #define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 |
| #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 |
| #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa |
| #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf |
| #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 |
| #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 |
| #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 |
| #define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 |
| #define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 |
| #define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 |
| #define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 |
| #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 |
| #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa |
| #define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff |
| #define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 |
| #define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 |
| #define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 |
| #define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 |
| #define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 |
| #define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 |
| #define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 |
| #define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 |
| #define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 |
| #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 |
| #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 |
| #define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 |
| #define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 |
| #define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 |
| #define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 |
| #define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff |
| #define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 |
| #define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 |
| #define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 |
| #define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 |
| #define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 |
| #define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 |
| #define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 |
| #define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 |
| #define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 |
| #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 |
| #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 |
| #define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 |
| #define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 |
| #define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 |
| #define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 |
| #define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 |
| #define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 |
| #define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000 |
| #define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19 |
| #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000 |
| #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a |
| #define MC_ARB_REMREQ__RD_WATER_MASK 0xff |
| #define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 |
| #define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 |
| #define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 |
| #define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 |
| #define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 |
| #define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 |
| #define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 |
| #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 |
| #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 |
| #define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 |
| #define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 |
| #define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 |
| #define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 |
| #define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 |
| #define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 |
| #define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 |
| #define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 |
| #define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 |
| #define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 |
| #define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 |
| #define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 |
| #define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 |
| #define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 |
| #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 |
| #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 |
| #define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 |
| #define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 |
| #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 |
| #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf |
| #define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff |
| #define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 |
| #define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 |
| #define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 |
| #define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 |
| #define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 |
| #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 |
| #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 |
| #define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff |
| #define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 |
| #define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 |
| #define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 |
| #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 |
| #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 |
| #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 |
| #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 |
| #define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 |
| #define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c |
| #define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff |
| #define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 |
| #define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 |
| #define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 |
| #define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 |
| #define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 |
| #define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 |
| #define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 |
| #define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 |
| #define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 |
| #define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 |
| #define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 |
| #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff |
| #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 |
| #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff |
| #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 |
| #define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1 |
| #define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0 |
| #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2 |
| #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1 |
| #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4 |
| #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2 |
| #define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8 |
| #define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3 |
| #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10 |
| #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4 |
| #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20 |
| #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5 |
| #define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40 |
| #define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6 |
| #define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80 |
| #define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7 |
| #define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100 |
| #define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8 |
| #define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200 |
| #define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9 |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400 |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800 |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000 |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000 |
| #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd |
| #define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000 |
| #define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe |
| #define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000 |
| #define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf |
| #define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000 |
| #define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10 |
| #define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000 |
| #define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11 |
| #define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000 |
| #define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12 |
| #define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000 |
| #define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13 |
| #define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000 |
| #define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14 |
| #define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000 |
| #define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15 |
| #define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000 |
| #define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16 |
| #define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000 |
| #define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17 |
| #define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000 |
| #define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18 |
| #define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000 |
| #define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19 |
| #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000 |
| #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a |
| #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000 |
| #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b |
| #define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000 |
| #define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c |
| #define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000 |
| #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d |
| #define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000 |
| #define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e |
| #define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000 |
| #define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f |
| #define MC_ARB_CG__CG_ARB_REQ_MASK 0xff |
| #define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 |
| #define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 |
| #define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 |
| #define MC_ARB_CG__RSV_0_MASK 0xff0000 |
| #define MC_ARB_CG__RSV_0__SHIFT 0x10 |
| #define MC_ARB_CG__RSV_1_MASK 0xff000000 |
| #define MC_ARB_CG__RSV_1__SHIFT 0x18 |
| #define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1 |
| #define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0 |
| #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2 |
| #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1 |
| #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4 |
| #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2 |
| #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8 |
| #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3 |
| #define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10 |
| #define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4 |
| #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20 |
| #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5 |
| #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40 |
| #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6 |
| #define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80 |
| #define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7 |
| #define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100 |
| #define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8 |
| #define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200 |
| #define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9 |
| #define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400 |
| #define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa |
| #define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800 |
| #define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb |
| #define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000 |
| #define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc |
| #define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000 |
| #define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd |
| #define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000 |
| #define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe |
| #define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000 |
| #define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf |
| #define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000 |
| #define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10 |
| #define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000 |
| #define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11 |
| #define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000 |
| #define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12 |
| #define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000 |
| #define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13 |
| #define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000 |
| #define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14 |
| #define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000 |
| #define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15 |
| #define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000 |
| #define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000 |
| #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19 |
| #define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000 |
| #define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a |
| #define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000 |
| #define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b |
| #define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000 |
| #define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c |
| #define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000 |
| #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d |
| #define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000 |
| #define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e |
| #define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000 |
| #define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f |
| #define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff |
| #define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 |
| #define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 |
| #define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 |
| #define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 |
| #define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 |
| #define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 |
| #define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 |
| #define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 |
| #define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 |
| #define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 |
| #define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 |
| #define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 |
| #define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 |
| #define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 |
| #define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 |
| #define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 |
| #define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 |
| #define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 |
| #define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 |
| #define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 |
| #define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 |
| #define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 |
| #define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 |
| #define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 |
| #define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 |
| #define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 |
| #define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 |
| #define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 |
| #define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa |
| #define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 |
| #define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb |
| #define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 |
| #define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc |
| #define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 |
| #define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd |
| #define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 |
| #define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe |
| #define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 |
| #define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf |
| #define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 |
| #define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 |
| #define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 |
| #define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 |
| #define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 |
| #define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 |
| #define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 |
| #define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 |
| #define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 |
| #define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 |
| #define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 |
| #define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 |
| #define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 |
| #define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 |
| #define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 |
| #define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 |
| #define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000 |
| #define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18 |
| #define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000 |
| #define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19 |
| #define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 |
| #define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a |
| #define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 |
| #define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b |
| #define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 |
| #define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c |
| #define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 |
| #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d |
| #define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 |
| #define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e |
| #define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 |
| #define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f |
| #define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff |
| #define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 |
| #define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 |
| #define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 |
| #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 |
| #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 |
| #define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 |
| #define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 |
| #define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff |
| #define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0 |
| #define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00 |
| #define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8 |
| #define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000 |
| #define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10 |
| #define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000 |
| #define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11 |
| #define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000 |
| #define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12 |
| #define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000 |
| #define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13 |
| #define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000 |
| #define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14 |
| #define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000 |
| #define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15 |
| #define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000 |
| #define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16 |
| #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000 |
| #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17 |
| #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000 |
| #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18 |
| #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000 |
| #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19 |
| #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000 |
| #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a |
| #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000 |
| #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b |
| #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000 |
| #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c |
| #define MC_ARB_BURST_TIME__STATE0_MASK 0x1f |
| #define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 |
| #define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 |
| #define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 |
| #define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00 |
| #define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa |
| #define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000 |
| #define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf |
| #define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000 |
| #define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14 |
| #define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000 |
| #define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19 |
| #define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 |
| #define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 |
| #define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 |
| #define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 |
| #define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 |
| #define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 |
| #define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 |
| #define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 |
| #define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 |
| #define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 |
| #define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 |
| #define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 |
| #define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 |
| #define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc |
| #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 |
| #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd |
| #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 |
| #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf |
| #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 |
| #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 |
| #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 |
| #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 |
| #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 |
| #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 |
| #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 |
| #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 |
| #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 |
| #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 |
| #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 |
| #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a |
| #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 |
| #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b |
| #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 |
| #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c |
| #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 |
| #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d |
| #define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e |
| #define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 |
| #define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 |
| #define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 |
| #define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 |
| #define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 |
| #define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 |
| #define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 |
| #define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 |
| #define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 |
| #define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 |
| #define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 |
| #define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 |
| #define MC_CG_CONFIG__INDEX__SHIFT 0x6 |
| #define MC_CITF_CNTL__IGNOREPM_MASK 0x4 |
| #define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 |
| #define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 |
| #define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 |
| #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 |
| #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 |
| #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 |
| #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 |
| #define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 |
| #define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 |
| #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 |
| #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 |
| #define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f |
| #define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 |
| #define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 |
| #define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 |
| #define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff |
| #define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 |
| #define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 |
| #define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 |
| #define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 |
| #define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 |
| #define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 |
| #define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 |
| #define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 |
| #define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 |
| #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 |
| #define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 |
| #define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 |
| #define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 |
| #define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 |
| #define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 |
| #define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 |
| #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e |
| #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 |
| #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 |
| #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 |
| #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 |
| #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 |
| #define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f |
| #define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 |
| #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 |
| #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc |
| #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 |
| #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 |
| #define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 |
| #define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 |
| #define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 |
| #define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 |
| #define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 |
| #define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 |
| #define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 |
| #define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 |
| #define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 |
| #define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 |
| #define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 |
| #define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 |
| #define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 |
| #define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 |
| #define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 |
| #define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 |
| #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 |
| #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 |
| #define MC_CITF_DAGB_DLY__DLY_MASK 0x1f |
| #define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 |
| #define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 |
| #define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 |
| #define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000 |
| #define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 |
| #define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf |
| #define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 |
| #define MC_RD_GRP_EXT__TC0_MASK 0xf0 |
| #define MC_RD_GRP_EXT__TC0__SHIFT 0x4 |
| #define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf |
| #define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 |
| #define MC_WR_GRP_EXT__TC0_MASK 0xf0 |
| #define MC_WR_GRP_EXT__TC0__SHIFT 0x4 |
| #define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f |
| #define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 |
| #define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 |
| #define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 |
| #define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 |
| #define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe |
| #define MC_WR_TC0__ENABLE_MASK 0x1 |
| #define MC_WR_TC0__ENABLE__SHIFT 0x0 |
| #define MC_WR_TC0__PRESCALE_MASK 0x6 |
| #define MC_WR_TC0__PRESCALE__SHIFT 0x1 |
| #define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_WR_TC0__STALL_MODE_MASK 0x30 |
| #define MC_WR_TC0__STALL_MODE__SHIFT 0x4 |
| #define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_WR_TC0__MAX_BURST_MASK 0x780 |
| #define MC_WR_TC0__MAX_BURST__SHIFT 0x7 |
| #define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 |
| #define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb |
| #define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_WR_TC1__ENABLE_MASK 0x1 |
| #define MC_WR_TC1__ENABLE__SHIFT 0x0 |
| #define MC_WR_TC1__PRESCALE_MASK 0x6 |
| #define MC_WR_TC1__PRESCALE__SHIFT 0x1 |
| #define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_WR_TC1__STALL_MODE_MASK 0x30 |
| #define MC_WR_TC1__STALL_MODE__SHIFT 0x4 |
| #define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 |
| #define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_WR_TC1__MAX_BURST_MASK 0x780 |
| #define MC_WR_TC1__MAX_BURST__SHIFT 0x7 |
| #define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 |
| #define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb |
| #define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f |
| #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 |
| #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 |
| #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 |
| #define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff |
| #define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0 |
| #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 |
| #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 |
| #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 |
| #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 |
| #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 |
| #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 |
| #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 |
| #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 |
| #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 |
| #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc |
| #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 |
| #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf |
| #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 |
| #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 |
| #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 |
| #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 |
| #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 |
| #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 |
| #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 |
| #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 |
| #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 |
| #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 |
| #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 |
| #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 |
| #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 |
| #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 |
| #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 |
| #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 |
| #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 |
| #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc |
| #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 |
| #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf |
| #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 |
| #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 |
| #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 |
| #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 |
| #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 |
| #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 |
| #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 |
| #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 |
| #define MC_RD_CB__ENABLE_MASK 0x1 |
| #define MC_RD_CB__ENABLE__SHIFT 0x0 |
| #define MC_RD_CB__PRESCALE_MASK 0x6 |
| #define MC_RD_CB__PRESCALE__SHIFT 0x1 |
| #define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_RD_CB__STALL_MODE_MASK 0x30 |
| #define MC_RD_CB__STALL_MODE__SHIFT 0x4 |
| #define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_RD_CB__MAX_BURST_MASK 0x780 |
| #define MC_RD_CB__MAX_BURST__SHIFT 0x7 |
| #define MC_RD_CB__LAZY_TIMER_MASK 0x7800 |
| #define MC_RD_CB__LAZY_TIMER__SHIFT 0xb |
| #define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_RD_DB__ENABLE_MASK 0x1 |
| #define MC_RD_DB__ENABLE__SHIFT 0x0 |
| #define MC_RD_DB__PRESCALE_MASK 0x6 |
| #define MC_RD_DB__PRESCALE__SHIFT 0x1 |
| #define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_RD_DB__STALL_MODE_MASK 0x30 |
| #define MC_RD_DB__STALL_MODE__SHIFT 0x4 |
| #define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_RD_DB__MAX_BURST_MASK 0x780 |
| #define MC_RD_DB__MAX_BURST__SHIFT 0x7 |
| #define MC_RD_DB__LAZY_TIMER_MASK 0x7800 |
| #define MC_RD_DB__LAZY_TIMER__SHIFT 0xb |
| #define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_RD_TC0__ENABLE_MASK 0x1 |
| #define MC_RD_TC0__ENABLE__SHIFT 0x0 |
| #define MC_RD_TC0__PRESCALE_MASK 0x6 |
| #define MC_RD_TC0__PRESCALE__SHIFT 0x1 |
| #define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_RD_TC0__STALL_MODE_MASK 0x30 |
| #define MC_RD_TC0__STALL_MODE__SHIFT 0x4 |
| #define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_RD_TC0__MAX_BURST_MASK 0x780 |
| #define MC_RD_TC0__MAX_BURST__SHIFT 0x7 |
| #define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 |
| #define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb |
| #define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_RD_TC1__ENABLE_MASK 0x1 |
| #define MC_RD_TC1__ENABLE__SHIFT 0x0 |
| #define MC_RD_TC1__PRESCALE_MASK 0x6 |
| #define MC_RD_TC1__PRESCALE__SHIFT 0x1 |
| #define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_RD_TC1__STALL_MODE_MASK 0x30 |
| #define MC_RD_TC1__STALL_MODE__SHIFT 0x4 |
| #define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 |
| #define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_RD_TC1__MAX_BURST_MASK 0x780 |
| #define MC_RD_TC1__MAX_BURST__SHIFT 0x7 |
| #define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 |
| #define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb |
| #define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_RD_HUB__ENABLE_MASK 0x1 |
| #define MC_RD_HUB__ENABLE__SHIFT 0x0 |
| #define MC_RD_HUB__PRESCALE_MASK 0x6 |
| #define MC_RD_HUB__PRESCALE__SHIFT 0x1 |
| #define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_RD_HUB__STALL_MODE_MASK 0x30 |
| #define MC_RD_HUB__STALL_MODE__SHIFT 0x4 |
| #define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_RD_HUB__MAX_BURST_MASK 0x780 |
| #define MC_RD_HUB__MAX_BURST__SHIFT 0x7 |
| #define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 |
| #define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb |
| #define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_WR_CB__ENABLE_MASK 0x1 |
| #define MC_WR_CB__ENABLE__SHIFT 0x0 |
| #define MC_WR_CB__PRESCALE_MASK 0x6 |
| #define MC_WR_CB__PRESCALE__SHIFT 0x1 |
| #define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_WR_CB__STALL_MODE_MASK 0x30 |
| #define MC_WR_CB__STALL_MODE__SHIFT 0x4 |
| #define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_WR_CB__MAX_BURST_MASK 0x780 |
| #define MC_WR_CB__MAX_BURST__SHIFT 0x7 |
| #define MC_WR_CB__LAZY_TIMER_MASK 0x7800 |
| #define MC_WR_CB__LAZY_TIMER__SHIFT 0xb |
| #define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_WR_DB__ENABLE_MASK 0x1 |
| #define MC_WR_DB__ENABLE__SHIFT 0x0 |
| #define MC_WR_DB__PRESCALE_MASK 0x6 |
| #define MC_WR_DB__PRESCALE__SHIFT 0x1 |
| #define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_WR_DB__STALL_MODE_MASK 0x30 |
| #define MC_WR_DB__STALL_MODE__SHIFT 0x4 |
| #define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_WR_DB__MAX_BURST_MASK 0x780 |
| #define MC_WR_DB__MAX_BURST__SHIFT 0x7 |
| #define MC_WR_DB__LAZY_TIMER_MASK 0x7800 |
| #define MC_WR_DB__LAZY_TIMER__SHIFT 0xb |
| #define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_WR_HUB__ENABLE_MASK 0x1 |
| #define MC_WR_HUB__ENABLE__SHIFT 0x0 |
| #define MC_WR_HUB__PRESCALE_MASK 0x6 |
| #define MC_WR_HUB__PRESCALE__SHIFT 0x1 |
| #define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_WR_HUB__STALL_MODE_MASK 0x30 |
| #define MC_WR_HUB__STALL_MODE__SHIFT 0x4 |
| #define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 |
| #define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_WR_HUB__MAX_BURST_MASK 0x780 |
| #define MC_WR_HUB__MAX_BURST__SHIFT 0x7 |
| #define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 |
| #define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb |
| #define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff |
| #define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 |
| #define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 |
| #define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 |
| #define MC_RD_GRP_LCL__CB0_MASK 0xf000 |
| #define MC_RD_GRP_LCL__CB0__SHIFT 0xc |
| #define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 |
| #define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 |
| #define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 |
| #define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 |
| #define MC_RD_GRP_LCL__DB0_MASK 0xf000000 |
| #define MC_RD_GRP_LCL__DB0__SHIFT 0x18 |
| #define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 |
| #define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c |
| #define MC_WR_GRP_LCL__CB0_MASK 0xf |
| #define MC_WR_GRP_LCL__CB0__SHIFT 0x0 |
| #define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 |
| #define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 |
| #define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 |
| #define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 |
| #define MC_WR_GRP_LCL__DB0_MASK 0xf000 |
| #define MC_WR_GRP_LCL__DB0__SHIFT 0xc |
| #define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 |
| #define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 |
| #define MC_WR_GRP_LCL__SX0_MASK 0xf00000 |
| #define MC_WR_GRP_LCL__SX0__SHIFT 0x14 |
| #define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 |
| #define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c |
| #define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff |
| #define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 |
| #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2 |
| #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1 |
| #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4 |
| #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2 |
| #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8 |
| #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3 |
| #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10 |
| #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4 |
| #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20 |
| #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5 |
| #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40 |
| #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6 |
| #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80 |
| #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7 |
| #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100 |
| #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8 |
| #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200 |
| #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9 |
| #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400 |
| #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa |
| #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800 |
| #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb |
| #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000 |
| #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc |
| #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000 |
| #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd |
| #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000 |
| #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe |
| #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000 |
| #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf |
| #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000 |
| #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10 |
| #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000 |
| #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11 |
| #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000 |
| #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12 |
| #define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f |
| #define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 |
| #define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 |
| #define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 |
| #define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 |
| #define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc |
| #define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 |
| #define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 |
| #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f |
| #define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 |
| #define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 |
| #define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 |
| #define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 |
| #define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc |
| #define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 |
| #define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 |
| #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f |
| #define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 |
| #define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 |
| #define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 |
| #define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 |
| #define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc |
| #define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 |
| #define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 |
| #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 |
| #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 |
| #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 |
| #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 |
| #define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f |
| #define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 |
| #define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 |
| #define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 |
| #define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 |
| #define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc |
| #define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 |
| #define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 |
| #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f |
| #define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 |
| #define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 |
| #define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 |
| #define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 |
| #define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc |
| #define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 |
| #define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 |
| #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f |
| #define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 |
| #define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 |
| #define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 |
| #define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 |
| #define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc |
| #define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 |
| #define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 |
| #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 |
| #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000 |
| #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe |
| #define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000 |
| #define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf |
| #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000 |
| #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10 |
| #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000 |
| #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11 |
| #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000 |
| #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12 |
| #define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000 |
| #define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13 |
| #define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 |
| #define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 |
| #define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff |
| #define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 |
| #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 |
| #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 |
| #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 |
| #define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 |
| #define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 |
| #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf |
| #define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 |
| #define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 |
| #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 |
| #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 |
| #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 |
| #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 |
| #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 |
| #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 |
| #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 |
| #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 |
| #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 |
| #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 |
| #define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 |
| #define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 |
| #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000 |
| #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17 |
| #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 |
| #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 |
| #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 |
| #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 |
| #define MC_HUB_WDP_BP__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe |
| #define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 |
| #define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 |
| #define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 |
| #define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 |
| #define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 |
| #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 |
| #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 |
| #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 |
| #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 |
| #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 |
| #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 |
| #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 |
| #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 |
| #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 |
| #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 |
| #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 |
| #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 |
| #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 |
| #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 |
| #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 |
| #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 |
| #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 |
| #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 |
| #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 |
| #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa |
| #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 |
| #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb |
| #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 |
| #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc |
| #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 |
| #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd |
| #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 |
| #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe |
| #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 |
| #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf |
| #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 |
| #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 |
| #define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 |
| #define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 |
| #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 |
| #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 |
| #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 |
| #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 |
| #define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 |
| #define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 |
| #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 |
| #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 |
| #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 |
| #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 |
| #define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 |
| #define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 |
| #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 |
| #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 |
| #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 |
| #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 |
| #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 |
| #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 |
| #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 |
| #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 |
| #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 |
| #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 |
| #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 |
| #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 |
| #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 |
| #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 |
| #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 |
| #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 |
| #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 |
| #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 |
| #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 |
| #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa |
| #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 |
| #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb |
| #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 |
| #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc |
| #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 |
| #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd |
| #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 |
| #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe |
| #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 |
| #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf |
| #define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 |
| #define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 |
| #define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 |
| #define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 |
| #define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 |
| #define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 |
| #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 |
| #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 |
| #define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 |
| #define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 |
| #define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 |
| #define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 |
| #define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 |
| #define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 |
| #define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 |
| #define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 |
| #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 |
| #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 |
| #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 |
| #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 |
| #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 |
| #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 |
| #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 |
| #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 |
| #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 |
| #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 |
| #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 |
| #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 |
| #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 |
| #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 |
| #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 |
| #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 |
| #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 |
| #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa |
| #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 |
| #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb |
| #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 |
| #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc |
| #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 |
| #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd |
| #define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 |
| #define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe |
| #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 |
| #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 |
| #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 |
| #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 |
| #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 |
| #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 |
| #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 |
| #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 |
| #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 |
| #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 |
| #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000 |
| #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a |
| #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000 |
| #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b |
| #define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 |
| #define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 |
| #define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe |
| #define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 |
| #define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 |
| #define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 |
| #define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 |
| #define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 |
| #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 |
| #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e |
| #define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 |
| #define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 |
| #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc |
| #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf |
| #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 |
| #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 |
| #define MC_HUB_WDP_CREDITS__VM0_MASK 0xff |
| #define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 |
| #define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 |
| #define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 |
| #define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 |
| #define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 |
| #define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 |
| #define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 |
| #define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff |
| #define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 |
| #define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 |
| #define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 |
| #define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000 |
| #define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10 |
| #define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000 |
| #define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18 |
| #define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf |
| #define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 |
| #define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 |
| #define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 |
| #define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 |
| #define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000 |
| #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19 |
| #define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf |
| #define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 |
| #define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 |
| #define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 |
| #define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 |
| #define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000 |
| #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19 |
| #define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff |
| #define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0 |
| #define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00 |
| #define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8 |
| #define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff |
| #define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 |
| #define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 |
| #define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 |
| #define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 |
| #define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 |
| #define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 |
| #define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 |
| #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff |
| #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 |
| #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 |
| #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 |
| #define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f |
| #define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 |
| #define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 |
| #define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 |
| #define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 |
| #define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000 |
| #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f |
| #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 |
| #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c |
| #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 |
| #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 |
| #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c |
| #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 |
| #define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe |
| #define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 |
| #define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 |
| #define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 |
| #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 |
| #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 |
| #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 |
| #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 |
| #define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe |
| #define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 |
| #define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 |
| #define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 |
| #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 |
| #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 |
| #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 |
| #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 |
| #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe |
| #define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 |
| #define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 |
| #define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 |
| #define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000 |
| #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15 |
| #define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 |
| #define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 |
| #define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 |
| #define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 |
| #define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 |
| #define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 |
| #define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb |
| #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 |
| #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 |
| #define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000 |
| #define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19 |
| #define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 |
| #define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 |
| #define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 |
| #define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 |
| #define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 |
| #define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 |
| #define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb |
| #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 |
| #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 |
| #define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000 |
| #define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19 |
| #define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 |
| #define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 |
| #define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 |
| #define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 |
| #define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 |
| #define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 |
| #define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb |
| #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 |
| #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 |
| #define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000 |
| #define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19 |
| #define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 |
| #define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 |
| #define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 |
| #define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 |
| #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 |
| #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 |
| #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb |
| #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 |
| #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 |
| #define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000 |
| #define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19 |
| #define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f |
| #define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80 |
| #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 |
| #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 |
| #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff |
| #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 |
| #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 |
| #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 |
| #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff |
| #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 |
| #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 |
| #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 |
| #define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000 |
| #define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 |
| #define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 |
| #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 |
| #define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 |
| #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 |
| #define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 |
| #define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 |
| #define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 |
| #define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 |
| #define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 |
| #define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd |
| #define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 |
| #define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 |
| #define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 |
| #define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 |
| #define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 |
| #define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 |
| #define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 |
| #define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 |
| #define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 |
| #define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 |
| #define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd |
| #define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 |
| #define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 |
| #define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 |
| #define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 |
| #define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 |
| #define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 |
| #define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 |
| #define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 |
| #define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 |
| #define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 |
| #define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd |
| #define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 |
| #define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 |
| #define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 |
| #define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 |
| #define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 |
| #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 |
| #define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 |
| #define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 |
| #define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 |
| #define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 |
| #define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 |
| #define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 |
| #define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 |
| #define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd |
| #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 |
| #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 |
| #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 |
| #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 |
| #define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 |
| #define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 |
| #define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc |
| #define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 |
| #define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000 |
| #define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10 |
| #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000 |
| #define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12 |
| #define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_IH__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 |
| #define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 |
| #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000 |
| #define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12 |
| #define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 |
| #define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 |
| #define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe |
| #define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 |
| #define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 |
| #define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 |
| #define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe |
| #define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 |
| #define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 |
| #define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 |
| #define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe |
| #define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 |
| #define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 |
| #define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 |
| #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe |
| #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 |
| #define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 |
| #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 |
| #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 |
| #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 |
| #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 |
| #define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 |
| #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 |
| #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 |
| #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 |
| #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 |
| #define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000 |
| #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12 |
| #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000 |
| #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13 |
| #define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000 |
| #define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14 |
| #define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000 |
| #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12 |
| #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000 |
| #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13 |
| #define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000 |
| #define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14 |
| #define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_VP8__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 |
| #define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 |
| #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 |
| #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 |
| #define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 |
| #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 |
| #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 |
| #define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 |
| #define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 |
| #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 |
| #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 |
| #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 |
| #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 |
| #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 |
| #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 |
| #define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 |
| #define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 |
| #define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 |
| #define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 |
| #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 |
| #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 |
| #define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 |
| #define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 |
| #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 |
| #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 |
| #define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 |
| #define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 |
| #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 |
| #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb |
| #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 |
| #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf |
| #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 |
| #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT |
