blob: 0a0a889cc405acda117fdd9a790100fe18637845 [file] [log] [blame]
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _mmhub_2_0_0_SH_MASK_HEADER
#define _mmhub_2_0_0_SH_MASK_HEADER
// addressBlock: mmhub_dagbdec
//DAGB0_RDCLI0
#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI1
#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI2
#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI3
#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI4
#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI5
#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI6
#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI7
#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI8
#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI9
#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI10
#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI11
#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI12
#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI13
#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI14
#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI15
#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI16
#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI17
#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI18
#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L
//DAGB0_RD_CNTL
#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
//DAGB0_RD_GMI_CNTL
#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
//DAGB0_RD_ADDR_DAGB
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
//DAGB0_RD_CGTT_CLK_CTRL
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST1
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST2
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
//DAGB0_RD_VC0_CNTL
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC1_CNTL
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC2_CNTL
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC3_CNTL
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC4_CNTL
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC5_CNTL
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC6_CNTL
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC7_CNTL
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_CNTL_MISC
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
#define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
#define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L
//DAGB0_RD_TLB_CREDIT
#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
//DAGB0_RDCLI_ASK_PENDING
#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_GO_PENDING
#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_GBLSEND_PENDING
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_TLB_PENDING
#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_OARB_PENDING
#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_OSD_PENDING
#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI0
#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI1
#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI2
#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI3
#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI4
#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI5
#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI6
#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI7
#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI8
#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI9
#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI10
#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI11
#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI12
#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI13
#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI14
#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI15
#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI16
#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI17
#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI18
#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L
//DAGB0_WR_CNTL
#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
//DAGB0_WR_GMI_CNTL
#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
//DAGB0_WR_ADDR_DAGB
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
//DAGB0_WR_CGTT_CLK_CTRL
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST1
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST2
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
//DAGB0_WR_DATA_DAGB_MAX_BURST0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST1
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST2
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
//DAGB0_WR_VC0_CNTL
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC1_CNTL
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC2_CNTL
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC3_CNTL
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC4_CNTL
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC5_CNTL
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC6_CNTL
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC7_CNTL
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_CNTL_MISC
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L
//DAGB0_WR_TLB_CREDIT
#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
//DAGB0_WR_DATA_CREDIT
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
//DAGB0_WR_MISC_CREDIT
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
//DAGB0_WRCLI_ASK_PENDING
#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GO_PENDING
#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GBLSEND_PENDING
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_TLB_PENDING
#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_OARB_PENDING
#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_OSD_PENDING
#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_ASK_PENDING
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_GO_PENDING
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
//DAGB0_DAGB_DLY
#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
//DAGB0_CNTL_MISC
#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
//DAGB0_CNTL_MISC2
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L
//DAGB0_FIFO_EMPTY
#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
//DAGB0_FIFO_FULL
#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
//DAGB0_WR_CREDITS_FULL
#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
//DAGB0_RD_CREDITS_FULL
#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
//DAGB0_PERFCOUNTER_LO
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
//DAGB0_PERFCOUNTER_HI
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
//DAGB0_PERFCOUNTER0_CFG
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER1_CFG
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER2_CFG
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER_RSLT_CNTL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
//DAGB0_RESERVE0
#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE1
#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE2
#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE3
#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE4
#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE5
#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE6
#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE7
#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE8
#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE9
#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE10
#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE11
#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE12
#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE13
#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE14
#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE15
#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE16
#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE17
#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE18
#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE19
#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE20
#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE21
#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE22
#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE23
#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE24
#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE25
#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE26
#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE27
#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE28
#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE29
#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE30
#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE31
#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE32
#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE33
#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE34
#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE35
#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE36
#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE37
#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE38
#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE39
#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE40
#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE41
#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE42
#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE43
#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE44
#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE45
#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE46
#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE47
#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE48
#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE49
#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE50
#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE51
#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE52
#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE53
#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE54
#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE55
#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE56
#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE57
#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE58
#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE59
#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE60
#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE61
#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE62
#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE63
#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE64
#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE65
#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE66
#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE67
#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE68
#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE69
#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE70
#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE71
#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE72
#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE73
#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE74
#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE75
#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE76
#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE77
#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE78
#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE79
#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE80
#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE81
#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE82
#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE83
#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE84
#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE85
#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE86
#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE87
#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE88
#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE89
#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE90
#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE91
#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE92
#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE93
#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE94
#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE95
#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE96
#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE97
#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE98
#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE99
#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE100
#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE101
#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE102
#define DAGB0_RESERVE102__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE102__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE103
#define DAGB0_RESERVE103__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE103__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE104
#define DAGB0_RESERVE104__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE104__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE105
#define DAGB0_RESERVE105__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE105__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE106
#define DAGB0_RESERVE106__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE106__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE107
#define DAGB0_RESERVE107__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE107__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE108
#define DAGB0_RESERVE108__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE108__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE109
#define DAGB0_RESERVE109__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE109__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE110
#define DAGB0_RESERVE110__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE110__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE111
#define DAGB0_RESERVE111__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE111__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE112
#define DAGB0_RESERVE112__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE112__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE113
#define DAGB0_RESERVE113__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE113__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE114
#define DAGB0_RESERVE114__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE114__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE115
#define DAGB0_RESERVE115__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE115__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE116
#define DAGB0_RESERVE116__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE116__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE117
#define DAGB0_RESERVE117__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE117__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE118
#define DAGB0_RESERVE118__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE118__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE119
#define DAGB0_RESERVE119__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE119__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE120
#define DAGB0_RESERVE120__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE120__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE121
#define DAGB0_RESERVE121__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE121__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE122
#define DAGB0_RESERVE122__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE122__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE123
#define DAGB0_RESERVE123__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE123__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE124
#define DAGB0_RESERVE124__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE124__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE125
#define DAGB0_RESERVE125__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE125__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE126
#define DAGB0_RESERVE126__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE126__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE127
#define DAGB0_RESERVE127__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE127__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE128
#define DAGB0_RESERVE128__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE128__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE129
#define DAGB0_RESERVE129__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE129__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE130
#define DAGB0_RESERVE130__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE130__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE131
#define DAGB0_RESERVE131__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE131__RESERVE_MASK 0xFFFFFFFFL
// addressBlock: mmhub_mmea_mmeadec
//MMEA0_DRAM_RD_CLI2GRP_MAP0
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
//MMEA0_DRAM_RD_CLI2GRP_MAP1
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
//MMEA0_DRAM_WR_CLI2GRP_MAP0
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
//MMEA0_DRAM_WR_CLI2GRP_MAP1
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
//MMEA0_DRAM_RD_GRP2VC_MAP
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
//MMEA0_DRAM_WR_GRP2VC_MAP
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
//MMEA0_DRAM_RD_LAZY
#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
//MMEA0_DRAM_WR_LAZY
#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
//MMEA0_DRAM_RD_CAM_CNTL
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
//MMEA0_DRAM_WR_CAM_CNTL
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
//MMEA0_DRAM_PAGE_BURST
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
//MMEA0_DRAM_RD_PRI_AGE
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
//MMEA0_DRAM_WR_PRI_AGE
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
//MMEA0_DRAM_RD_PRI_QUEUING
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
//MMEA0_DRAM_WR_PRI_QUEUING
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
//MMEA0_DRAM_RD_PRI_FIXED
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
//MMEA0_DRAM_WR_PRI_FIXED
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
//MMEA0_DRAM_RD_PRI_URGENCY
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
//MMEA0_DRAM_WR_PRI_URGENCY