| /* |
| * Copyright (C) 2018 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _mmhub_9_4_1_DEFAULT_HEADER |
| #define _mmhub_9_4_1_DEFAULT_HEADER |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec0 |
| #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB0_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB0_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB0_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec1 |
| #define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB1_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB1_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB1_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec2 |
| #define mmDAGB2_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB2_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB2_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB2_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB2_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB2_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB2_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB2_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB2_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB2_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB2_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB2_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB2_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB2_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB2_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB2_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB2_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB2_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB2_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB2_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB2_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB2_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB2_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB2_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB2_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB2_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB2_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec3 |
| #define mmDAGB3_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB3_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB3_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB3_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB3_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB3_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB3_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB3_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB3_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB3_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB3_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB3_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB3_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB3_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB3_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB3_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB3_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB3_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB3_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB3_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB3_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB3_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB3_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB3_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB3_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB3_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB3_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB3_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB3_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB3_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec4 |
| #define mmDAGB4_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB4_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB4_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB4_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB4_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB4_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB4_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB4_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB4_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB4_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB4_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB4_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB4_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB4_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB4_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB4_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB4_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB4_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB4_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB4_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB4_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB4_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB4_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB4_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB4_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB4_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB4_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB4_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB4_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB4_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_ea_mmeadec0 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA0_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA0_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA0_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA0_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA0_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA0_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA0_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA0_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA0_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA0_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA0_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA0_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA0_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA0_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA0_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec1 |
| #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA1_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA1_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA1_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA1_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA1_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA1_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA1_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA1_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA1_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA1_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA1_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA1_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA1_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA1_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA1_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA1_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec2 |
| #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA2_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA2_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA2_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA2_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA2_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA2_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA2_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA2_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA2_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA2_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA2_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA2_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA2_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA2_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA2_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA2_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA2_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA2_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA2_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA2_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA2_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA2_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA2_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA2_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA2_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA2_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA2_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA2_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA2_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA2_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA2_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA2_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA2_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA2_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA2_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA2_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA2_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA2_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA2_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA2_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA2_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA2_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA2_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA2_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA2_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA2_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA2_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA2_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA2_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA2_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA2_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA2_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA2_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA2_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA2_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec3 |
| #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA3_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA3_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA3_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA3_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA3_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA3_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA3_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA3_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA3_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA3_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA3_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA3_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA3_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA3_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA3_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA3_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA3_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA3_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA3_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA3_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA3_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA3_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA3_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA3_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA3_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA3_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA3_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA3_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA3_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA3_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA3_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA3_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA3_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA3_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA3_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA3_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA3_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA3_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA3_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA3_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA3_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA3_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA3_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA3_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA3_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA3_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA3_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA3_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA3_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA3_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA3_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA3_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA3_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA3_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA3_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA3_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA3_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec4 |
| #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA4_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA4_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA4_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA4_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA4_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA4_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA4_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA4_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA4_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA4_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA4_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA4_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA4_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA4_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA4_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA4_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA4_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA4_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA4_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA4_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA4_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA4_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA4_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA4_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA4_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA4_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA4_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA4_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA4_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA4_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA4_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA4_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA4_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA4_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA4_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA4_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA4_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA4_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA4_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA4_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA4_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA4_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA4_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA4_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA4_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA4_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA4_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA4_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA4_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA4_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA4_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA4_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA4_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA4_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA4_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA4_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA4_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_pctldec0 |
| #define mmPCTL0_CTRL_DEFAULT 0x00011040 |
| #define mmPCTL0_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 |
| #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 |
| #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_MISC_DEFAULT 0x00011000 |
| #define mmPCTL0_SLICE0_MISC_DEFAULT 0x00000800 |
| #define mmPCTL0_SLICE1_MISC_DEFAULT 0x00000800 |
| #define mmPCTL0_SLICE2_MISC_DEFAULT 0x00000800 |
| #define mmPCTL0_SLICE3_MISC_DEFAULT 0x00000800 |
| #define mmPCTL0_SLICE4_MISC_DEFAULT 0x00000800 |
| #define mmPCTL0_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1dec |
| #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1pldec |
| #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1prdec |
| #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2dec |
| #define mmATCL2_0_ATC_L2_CNTL_DEFAULT 0x0001c0c9 |
| #define mmATCL2_0_ATC_L2_CNTL2_DEFAULT 0x00600100 |
| #define mmATCL2_0_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CNTL3_DEFAULT 0x000001f8 |
| #define mmATCL2_0_ATC_L2_STATUS_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_STATUS2_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_STATUS3_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_MISC_CG_DEFAULT 0x00000200 |
| #define mmATCL2_0_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_CNTL4_DEFAULT 0x00000000 |
| #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pfdec |
| #define mmVML2PF0_VM_L2_CNTL_DEFAULT 0x00080602 |
| #define mmVML2PF0_VM_L2_CNTL2_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CNTL3_DEFAULT 0x80100007 |
| #define mmVML2PF0_VM_L2_STATUS_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 |
| #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CNTL4_DEFAULT 0x000000c1 |
| #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 |
| #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2vcdec |
| #define mmVML2VC0_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC0_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedpfdec |
| #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 |
| #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_FB_OFFSET_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_STEERING_DEFAULT 0x00000001 |
| #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_APT_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff |
| #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedvcdec |
| #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_AGP_TOP_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_AGP_BOT_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_AGP_BASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedhvdec |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
| #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntldec |
| #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pldec |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2prdec |
| #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec5 |
| #define mmDAGB5_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB5_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB5_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB5_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB5_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB5_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB5_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB5_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB5_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB5_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB5_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB5_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB5_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB5_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB5_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB5_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB5_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB5_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB5_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB5_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB5_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB5_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB5_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB5_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB5_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB5_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB5_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB5_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB5_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB5_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec6 |
| #define mmDAGB6_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB6_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB6_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB6_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB6_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB6_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB6_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB6_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB6_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB6_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB6_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB6_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB6_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB6_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB6_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB6_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB6_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB6_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB6_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB6_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB6_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB6_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB6_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB6_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB6_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB6_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB6_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB6_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB6_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB6_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_dagb_dagbdec7 |
| #define mmDAGB7_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB7_RD_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB7_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB7_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB7_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_RD_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB7_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB7_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB7_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB7_WR_GMI_CNTL_DEFAULT 0x00003045 |
| #define mmDAGB7_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB7_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB7_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB7_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB7_WR_CNTL_MISC_DEFAULT 0x69a0e408 |
| #define mmDAGB7_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB7_WR_DATA_CREDIT_DEFAULT 0x60606070 |
| #define mmDAGB7_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB7_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB7_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB7_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB7_CNTL_MISC2_DEFAULT 0x003c0000 |
| #define mmDAGB7_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB7_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB7_WR_CREDITS_FULL_DEFAULT 0x1fffffff |
| #define mmDAGB7_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB7_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB7_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB7_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB7_RESERVE0_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE1_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE2_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE3_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE4_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE5_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE6_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE7_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE8_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE9_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE10_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE11_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE12_DEFAULT 0xffffffff |
| #define mmDAGB7_RESERVE13_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_ea_mmeadec5 |
| #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA5_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA5_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA5_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA5_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA5_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA5_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA5_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA5_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA5_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA5_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA5_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA5_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA5_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA5_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA5_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA5_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA5_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA5_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA5_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA5_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA5_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA5_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA5_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA5_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA5_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA5_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA5_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA5_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA5_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA5_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA5_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA5_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA5_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA5_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA5_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA5_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA5_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA5_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA5_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA5_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA5_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA5_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA5_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA5_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA5_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA5_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA5_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA5_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA5_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA5_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA5_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA5_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA5_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA5_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA5_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA5_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA5_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec6 |
| #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA6_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA6_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA6_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA6_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA6_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA6_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA6_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA6_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA6_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA6_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA6_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA6_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA6_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA6_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA6_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA6_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA6_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA6_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA6_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA6_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA6_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA6_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA6_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA6_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA6_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA6_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA6_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA6_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA6_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA6_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA6_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA6_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA6_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA6_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA6_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA6_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA6_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA6_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA6_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA6_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA6_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA6_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA6_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA6_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA6_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA6_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA6_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA6_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA6_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA6_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA6_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA6_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA6_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA6_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA6_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA6_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA6_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec7 |
| #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA7_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA7_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA7_DRAM_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA7_DRAM_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA7_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA7_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA7_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA7_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA7_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA7_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA7_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 |
| #define mmMMEA7_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 |
| #define mmMMEA7_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA7_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff |
| #define mmMMEA7_GMI_RD_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA7_GMI_WR_LAZY_DEFAULT 0x78000924 |
| #define mmMMEA7_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA7_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 |
| #define mmMMEA7_GMI_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA7_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA7_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf |
| #define mmMMEA7_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 |
| #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA7_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 |
| #define mmMMEA7_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA7_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA7_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA7_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA7_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA7_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA7_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA7_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA7_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA7_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA7_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA7_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff |
| #define mmMMEA7_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA7_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA7_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA7_SDP_ARB_DRAM_DEFAULT 0x00101e40 |
| #define mmMMEA7_SDP_ARB_GMI_DEFAULT 0x00101e40 |
| #define mmMMEA7_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA7_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_GMI_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_CREDITS_DEFAULT 0x000101bf |
| #define mmMMEA7_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA7_SDP_REQ_CNTL_DEFAULT 0x0000001f |
| #define mmMMEA7_MISC_DEFAULT 0x0c00a070 |
| #define mmMMEA7_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA7_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA7_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA7_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA7_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA7_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA7_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA7_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA7_ERR_STATUS_DEFAULT 0x00000300 |
| #define mmMMEA7_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA7_ADDRDEC_SELECT_DEFAULT 0x00000000 |
| #define mmMMEA7_EDC_CNT3_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_pctldec1 |
| #define mmPCTL1_CTRL_DEFAULT 0x00011040 |
| #define mmPCTL1_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 |
| #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 |
| #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_MISC_DEFAULT 0x00011000 |
| #define mmPCTL1_SLICE0_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_SLICE1_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_SLICE2_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_SLICE3_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_SLICE4_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff |
| #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1dec:1 |
| #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 |
| #define mmVML1_1_MC_VM_MX_L1_TMZ_CNTL_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1pldec:1 |
| #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1prdec:1 |
| #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2dec:1 |
| #define mmATCL2_1_ATC_L2_CNTL_DEFAULT 0x0001c0c9 |
| #define mmATCL2_1_ATC_L2_CNTL2_DEFAULT 0x00600100 |
| #define mmATCL2_1_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CNTL3_DEFAULT 0x000001f8 |
| #define mmATCL2_1_ATC_L2_STATUS_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_STATUS2_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_STATUS3_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_MISC_CG_DEFAULT 0x00000200 |
| #define mmATCL2_1_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_CNTL4_DEFAULT 0x00000000 |
| #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pfdec:1 |
| #define mmVML2PF1_VM_L2_CNTL_DEFAULT 0x00080602 |
| #define mmVML2PF1_VM_L2_CNTL2_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CNTL3_DEFAULT 0x80100007 |
| #define mmVML2PF1_VM_L2_STATUS_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 |
| #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CNTL4_DEFAULT 0x000000c1 |
| #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 |
| #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2vcdec:1 |
| #define mmVML2VC1_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 |
| #define mmVML2VC1_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedpfdec:1 |
| #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 |
| #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_FB_OFFSET_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_STEERING_DEFAULT 0x00000001 |
| #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_APT_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff |
| #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 |
| #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedvcdec:1 |
| #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_AGP_TOP_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_AGP_BOT_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_AGP_BASE_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 |
| #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedhvdec:1 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 |
| #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 |
| #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 |
| #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pldec:1 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 |
| #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2prdec:1 |
| #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| #endif |
