blob: c185e9fce5880f76d1f8025eadd684084649f8ae [file] [log] [blame]
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _nbio_2_3_DEFAULT_HEADER
#define _nbio_2_3_DEFAULT_HEADER
// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
#define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
#define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
#define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_SYSDEC
#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
#define mmPCIE_INDEX_DEFAULT 0x00000000
#define mmPCIE_DATA_DEFAULT 0x00000000
#define mmPCIE_INDEX2_DEFAULT 0x00000000
#define mmPCIE_DATA2_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
#define mmSYSHUB_INDEX_DEFAULT 0x00000000
#define mmSYSHUB_DATA_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
#define mmRCC_BIF_STRAP0_DEFAULT 0x00040a00
#define mmRCC_BIF_STRAP1_DEFAULT 0x00400108
#define mmRCC_BIF_STRAP2_DEFAULT 0x000a0079
#define mmRCC_BIF_STRAP3_DEFAULT 0x00000000
#define mmRCC_BIF_STRAP4_DEFAULT 0x00100010
#define mmRCC_BIF_STRAP5_DEFAULT 0x31130010
#define mmRCC_BIF_STRAP6_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
#define mmEP_PCIE_CNTL_DEFAULT 0x00000000
#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001
#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
#define mmRCC_DEV0_EPF0_RCC_ERR_LOG_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
#define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000
#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
#define mmRCC_RESET_EN_DEFAULT 0x00008000
#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
#define mmRCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
#define mmRCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
#define mmRCC_GPUIOV_REGION_DEFAULT 0x00000000
#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
#define mmRCC_XDMA_LO_DEFAULT 0x00000000
#define mmRCC_XDMA_HI_DEFAULT 0x00000000
#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000
#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
#define mmCC_BIF_BX_STRAP0_DEFAULT 0x00000000
#define mmCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000
#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
#define mmBUS_CNTL_DEFAULT 0x00000000
#define mmBIF_SCRATCH0_DEFAULT 0x00000000
#define mmBIF_SCRATCH1_DEFAULT 0x00000000
#define mmBX_RESET_EN_DEFAULT 0x00010000
#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
#define mmBX_RESET_CNTL_DEFAULT 0x00000000
#define mmINTERRUPT_CNTL_DEFAULT 0x00000000
#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000
#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
#define mmBIF_FB_EN_DEFAULT 0x00000000
#define mmBIF_INTR_CNTL_DEFAULT 0x00000000
#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
#define mmBACO_CNTL_DEFAULT 0x00000000
#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200
#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
#define mmNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000
#define mmNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000
#define mmNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001
#define mmNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002
#define mmNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003
#define mmNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004
#define mmNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005
#define mmNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006
#define mmNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007
#define mmNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008
#define mmNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009
#define mmNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a
#define mmNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b
#define mmNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c
#define mmNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d
#define mmNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e
#define mmNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f
#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
#define mmBIF_RB_CNTL_DEFAULT 0x00000000
#define mmBIF_RB_BASE_DEFAULT 0x00000000
#define mmBIF_RB_RPTR_DEFAULT 0x00000000
#define mmBIF_RB_WPTR_DEFAULT 0x00000000
#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
#define mmMAILBOX_INDEX_DEFAULT 0x00000000
#define mmBIF_MP1_INTR_CTRL_DEFAULT 0x00000000
#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
#define mmBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071
#define mmBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031
#define mmBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d
// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
#define mmBIF_BX_PF_BIF_BME_STATUS_DEFAULT 0x00000000
#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
#define mmBIF_BX_PF_BIF_TRANS_PENDING_DEFAULT 0x00000000
#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_CONTROL_DEFAULT 0x00000000
#define mmBIF_BX_PF_MAILBOX_INT_CNTL_DEFAULT 0x00000000
#define mmBIF_BX_PF_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_gdc_GDCDEC
#define mmA2S_CNTL_CL0_DEFAULT 0x02a80540
#define mmA2S_CNTL_CL1_DEFAULT 0x02a825a0
#define mmA2S_CNTL3_CL0_DEFAULT 0x00000000
#define mmA2S_CNTL3_CL1_DEFAULT 0x00000008
#define mmA2S_CNTL_SW0_DEFAULT 0x04040000
#define mmA2S_CNTL_SW1_DEFAULT 0x04040200
#define mmA2S_CNTL_SW2_DEFAULT 0x04040200
#define mmA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
#define mmA2S_TAG_ALLOC_0_DEFAULT 0x00000000
#define mmA2S_TAG_ALLOC_1_DEFAULT 0x00000000
#define mmA2S_MISC_CNTL_DEFAULT 0x0005000b
#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f
#define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000
#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000100
#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
#define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f
#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
#define mmBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000
#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
#define mmNGDC_PG_MISC_CTRL_DEFAULT 0x14006000
#define mmNGDC_PGMST_CTRL_DEFAULT 0x00000000
#define mmNGDC_PGSLV_CTRL_DEFAULT 0x00001084
// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
#define mmRCC_DEV0_EPF0_GFXMSIX_PBA_DEFAULT 0x00000000
// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
#define cfgPSWUSCFG0_0_VENDOR_ID_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_DEVICE_ID_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_COMMAND_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_REVISION_ID_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PROG_INTERFACE_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_SUB_CLASS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_BASE_CLASS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_CACHE_LINE_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LATENCY_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_HEADER_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_BIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_SECONDARY_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MEM_BASE_LIMIT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PREF_BASE_LIMIT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PREF_BASE_UPPER_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_CAP_PTR_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_INTERRUPT_PIN_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_ADAPTER_ID_W_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PMI_CAP_LIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PMI_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define cfgPSWUSCFG0_0_PCIE_CAP_DEFAULT 0x00000002
#define cfgPSWUSCFG0_0_DEVICE_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_DEVICE_CNTL_DEFAULT 0x00002910
#define cfgPSWUSCFG0_0_DEVICE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LINK_CAP_DEFAULT 0x00011c04
#define cfgPSWUSCFG0_0_LINK_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LINK_STATUS_DEFAULT 0x00000001
#define cfgPSWUSCFG0_0_DEVICE_CAP2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_DEVICE_CNTL2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_DEVICE_STATUS2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LINK_CAP2_DEFAULT 0x0000001e
#define cfgPSWUSCFG0_0_LINK_CNTL2_DEFAULT 0x00000004
#define cfgPSWUSCFG0_0_LINK_STATUS2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
#define cfgPSWUSCFG0_0_MSI_MSG_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MSG_DATA_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_SSID_CAP_LIST_DEFAULT 0x0000c800
#define cfgPSWUSCFG0_0_SSID_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MSI_MAP_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000
#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x04400000
#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
#define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
#define cfgPSWUSCFG0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
#define cfgPSWUSCFG0_0_PCIE_MC_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
#define cfgPSWUSCFG0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000
#define cfgPSWUSCFG0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x3c400000
#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST_DEFAULT 0x40000000
#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CTRL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x80000001
#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
#define cfgPSWUSCFG0_0_LINK_CAP_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LINK_CNTL_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LINK_STATUS_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP_DEFAULT 0x00000000
#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT 0x00001002
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT 0x00007310
#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT 0x73101002
#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT 0x00000048
#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT 0x73101002
#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00006400
#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT 0x0000f000
#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT 0x00000012
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT 0x00000f81
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT 0x00000d04
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT 0x00010000
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT 0x0000001e
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT 0x00000004
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000084
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT 0x00001000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00001002
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x0000ab38
#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0xab381002
#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000048
#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000002
#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0xab381002
#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00006400
#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x0000f000
#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000012
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x00000f81
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00000d04
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00010000
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000001e
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000004
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00001000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID_DEFAULT 0x00001002
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID_DEFAULT 0x00007316
#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000030
#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS_DEFAULT 0x00000003
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS_DEFAULT 0x0000000c
#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_HEADER_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF2_0_BIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_DEFAULT 0x73161002
#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR_DEFAULT 0x00000048
#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000003
#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_DEFAULT 0x73161002
#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00006400
#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_DEFAULT 0x0000c800
#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_SBRN_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_DEFAULT 0x00000002
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_DEFAULT 0x00000f81
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP_DEFAULT 0x00000d04
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_DEFAULT 0x00010000
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2_DEFAULT 0x0000001e
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_DEFAULT 0x00000004
#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000086
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP_DEFAULT 0x00001000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID_DEFAULT 0x00001002
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID_DEFAULT 0x00007314
#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS_DEFAULT 0x0000000c
#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_HEADER_DEFAULT 0x00000080
#define cfgBIF_CFG_DEV0_EPF3_0_BIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_DEFAULT 0x73141002
#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR_DEFAULT 0x00000048
#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_DEFAULT 0x00000004
#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_DEFAULT 0x73141002
#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_DEFAULT 0x00006400
#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SBRN_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_DEFAULT 0x00000002
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_DEFAULT 0x00000f81
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_DEFAULT 0x00002810
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP_DEFAULT 0x00000d04
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_DEFAULT 0x00010000
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2_DEFAULT 0x0000001e
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_DEFAULT 0x00000004
#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_DEFAULT 0x00000001
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_DEFAULT 0x00000082
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP_DEFAULT 0x00001000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_gdc_GDCDEC
#define smnA2S_CNTL_CL0_DEFAULT 0x02a80540
#define smnA2S_CNTL_CL1_DEFAULT 0x02a825a0
#define smnA2S_CNTL3_CL0_DEFAULT 0x00000000
#define smnA2S_CNTL3_CL1_DEFAULT 0x00000008
#define smnA2S_CNTL_SW0_DEFAULT 0x04040000
#define smnA2S_CNTL_SW1_DEFAULT 0x04040200
#define smnA2S_CNTL_SW2_DEFAULT 0x04040200
#define smnA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
#define smnA2S_TAG_ALLOC_0_DEFAULT 0x00000000
#define smnA2S_TAG_ALLOC_1_DEFAULT 0x00000000
#define smnA2S_MISC_CNTL_DEFAULT 0x0005000b
#define smnNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f
#define smnSHUB_REGS_IF_CTL_DEFAULT 0x00000000
#define smnNGDC_MGCG_CTRL_DEFAULT 0x00000100
#define smnNGDC_RESERVED_0_DEFAULT 0x00000000
#define smnNGDC_RESERVED_1_DEFAULT 0x00000000
#define smnNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f
#define smnBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
#define smnBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
#define smnBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
#define smnBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
#define smnBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000
#define smnBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
#define smnS2A_MISC_CNTL_DEFAULT 0x00000000
#define smnNGDC_PG_MISC_CTRL_DEFAULT 0x14006000
#define smnNGDC_PGMST_CTRL_DEFAULT 0x00000000
#define smnNGDC_PGSLV_CTRL_DEFAULT 0x00001084
// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
#define smnSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
#define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_TRANS_IDLE_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_HP_TIMER_SOCCLK_DEFAULT 0x00000100
#define smnSYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000100
#define smnSYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_SCRATCH_SOCCLK_DEFAULT 0x00000040
#define smnSYSHUB_CL_MASK_SOCCLK_DEFAULT 0x00000000
#define smnSYSHUB_HANG_CNTL_SOCCLK_DEFAULT 0x00000000
#define smnHST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000
#define smnHST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000
#define smnHST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000
#define smnHST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000
#define smnHST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000
#define smnHST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000
#define smnDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
#define smnDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
#define smnDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
#define smnSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
#define smnSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
#define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
#define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
#define smnSYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000100
#define smnSYSHUB_SCRATCH_SHUBCLK_DEFAULT 0x00000040
#define smnSYSHUB_SELECT_SHUBCLK_DEFAULT 0x00000000
#define smnSYSHUB_SCRATCH_LCLK_DEFAULT 0x00000040
#define smnNIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_0_IB_0_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_1_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_1_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_1_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_1_IB_0_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_QOS_CNTL_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_MAX_OT_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_MAX_COMB_OT_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AW_P_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AW_B_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AW_R_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AR_P_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AR_B_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_AR_R_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_TARGET_FC_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_KI_FC_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_0_QOS_RANGE_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_QOS_CNTL_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_MAX_OT_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_MAX_COMB_OT_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AW_P_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AW_B_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AW_R_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AR_P_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AR_B_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_AR_R_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_TARGET_FC_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_KI_FC_DEFAULT 0x00000000
#define smnNIC400_2_ASIB_1_QOS_RANGE_DEFAULT 0x00000000
#define smnNIC400_2_IB_0_FN_MOD_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
#define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
#define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
#define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
#define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
#define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
#define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
#define smnSION_CNTL_REG0_DEFAULT 0x00000000
#define smnSION_CNTL_REG1_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
#define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000
#define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000
#define smnSHUB_LINK_RESET_DEFAULT 0x00000000
#define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
#define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000003b
#define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
#define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000
#define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001
// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
#define smnGDCL_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF0_CTRL_DEFAULT 0x00000f61
#define smnGDCSOC_RAS_LEAF1_CTRL_DEFAULT 0x00000f61
#define smnGDCSOC_RAS_LEAF2_CTRL_DEFAULT 0x00010f01
#define smnGDCSOC_RAS_LEAF3_CTRL_DEFAULT 0x00000f61
#define smnGDCSOC_RAS_LEAF4_CTRL_DEFAULT 0x00000f61
#define smnGDCSOC_RAS_LEAF5_CTRL_DEFAULT 0x00000f61
#define smnGDCSOC_RAS_LEAF2_MISC_CTRL_DEFAULT 0x00000202
#define smnGDCSOC_RAS_LEAF2_MISC_CTRL2_DEFAULT 0x0013ff21
#define smnGDCSOC_RAS_LEAF0_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF1_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF2_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF3_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF4_STATUS_DEFAULT 0x00000000
#define smnGDCSOC_RAS_LEAF5_STATUS_DEFAULT 0x00000000
#define smnGDCSHUB_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
#define smnBIF_CFG_DEV0_SWDS_VENDOR_ID_DEFAULT 0x00001002
#define smnBIF_CFG_DEV0_SWDS_DEVICE_ID_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_COMMAND_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_REVISION_ID_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PROG_INTERFACE_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_SUB_CLASS_DEFAULT 0x00000004
#define smnBIF_CFG_DEV0_SWDS_BASE_CLASS_DEFAULT 0x00000006
#define smnBIF_CFG_DEV0_SWDS_CACHE_LINE_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LATENCY_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_HEADER_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_BIST_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_2_DEFAULT 0x00000000
#define smnSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
#define smnIO_BASE_LIMIT_DEFAULT 0x00000000
#define smnSECONDARY_STATUS_DEFAULT 0x00000000
#define smnMEM_BASE_LIMIT_DEFAULT 0x00000000
#define smnPREF_BASE_LIMIT_DEFAULT 0x00000000
#define smnPREF_BASE_UPPER_DEFAULT 0x00000000
#define smnPREF_LIMIT_UPPER_DEFAULT 0x00000000
#define smnIO_BASE_LIMIT_HI_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_CAP_PTR_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_ROM_BASE_ADDR_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_INTERRUPT_LINE_DEFAULT 0x000000ff
#define smnBIF_CFG_DEV0_SWDS_INTERRUPT_PIN_DEFAULT 0x00000000
#define smnIRQ_BRIDGE_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PMI_CAP_LIST_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PMI_CAP_DEFAULT 0x0000c800
#define smnBIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_LIST_DEFAULT 0x0000a000
#define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_DEFAULT 0x00000062
#define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL_DEFAULT 0x00002810
#define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LINK_CAP_DEFAULT 0x00000d04
#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_DEFAULT 0x00002001
#define smnSLOT_CAP_DEFAULT 0x00000000
#define smnSLOT_CNTL_DEFAULT 0x00000000
#define smnSLOT_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP2_DEFAULT 0x00010000
#define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LINK_CAP2_DEFAULT 0x0000001e
#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL2_DEFAULT 0x00000004
#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS2_DEFAULT 0x00000000
#define smnSLOT_CAP2_DEFAULT 0x00000000
#define smnSLOT_CNTL2_DEFAULT 0x00000000
#define smnSLOT_STATUS2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_MSI_CAP_LIST_DEFAULT 0x0000c000
#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_CNTL_DEFAULT 0x00000080
#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64_DEFAULT 0x00000000
#define smnSSID_CAP_LIST_DEFAULT 0x00000000
#define smnSSID_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
#define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
#define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
#define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
#define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
#define smnBIF_CFG_DEV0_SWDS_LINK_CAP_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000
#define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
#define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
#define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
#define smnMM_INDEX_DEFAULT 0x00000000
#define smnMM_DATA_DEFAULT 0x00000000
#define smnMM_INDEX_HI_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_SYSDEC
#define smnSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
#define smnSYSHUB_DATA_OVLP_DEFAULT 0x00000000
#define smnPCIE_INDEX_DEFAULT 0x00000000
#define smnPCIE_DATA_DEFAULT 0x00000000
#define smnPCIE_INDEX2_DEFAULT 0x00000000
#define smnPCIE_DATA2_DEFAULT 0x00000000
#define smnSBIOS_SCRATCH_0_DEFAULT 0x00000000
#define smnSBIOS_SCRATCH_1_DEFAULT 0x00000000
#define smnSBIOS_SCRATCH_2_DEFAULT 0x00000000
#define smnSBIOS_SCRATCH_3_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_0_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_1_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_2_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_3_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_4_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_5_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_6_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_7_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_8_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_9_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_10_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_11_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_12_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_13_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_14_DEFAULT 0x00000000
#define smnBIOS_SCRATCH_15_DEFAULT 0x00000000
#define smnBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
#define smnBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
#define smnBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
#define smnGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
#define smnRCC_STRAP0_RCC_BIF_STRAP0_DEFAULT 0x00040a00
#define smnRCC_STRAP0_RCC_BIF_STRAP1_DEFAULT 0x00400108
#define smnRCC_STRAP0_RCC_BIF_STRAP2_DEFAULT 0x000a0079
#define smnRCC_STRAP0_RCC_BIF_STRAP3_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_BIF_STRAP4_DEFAULT 0x00100010
#define smnRCC_STRAP0_RCC_BIF_STRAP5_DEFAULT 0x31130010
#define smnRCC_STRAP0_RCC_BIF_STRAP6_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
#define smnRCC_EP_DEV0_0_EP_PCIE_SCRATCH_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define smnRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
#define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
#define smnRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIEP_RESERVED_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
#define smnRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
#define smnRCC_DWN_DEV0_0_DN_PCIE_RESERVED_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define smnRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_DEFAULT 0x00000001
#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
#define smnRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_DEFAULT 0x00000500
#define smnRCC_DWNP_DEV0_0_PCIE_RX_CNTL_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
#define smnRCC_ERR_INT_CNTL_DEFAULT 0x00000000
#define smnRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
#define smnRCC_RESET_EN_DEFAULT 0x00008000
#define smnRCC_DEV0_0_RCC_VDM_SUPPORT_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
#define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
#define smnRCC_GPUIOV_REGION_DEFAULT 0x00000000
#define smnRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
#define smnRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
#define smnRCC_DEV0_0_RCC_BUS_CNTL_DEFAULT 0x00000000
#define smnRCC_CONFIG_CNTL_DEFAULT 0x00000000
#define smnRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
#define smnRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
#define smnRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
#define smnRCC_XDMA_LO_DEFAULT 0x00000000
#define smnRCC_XDMA_HI_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
#define smnRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
#define smnRCC_BUSNUM_LIST0_DEFAULT 0x00000000
#define smnRCC_BUSNUM_LIST1_DEFAULT 0x00000000
#define smnRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
#define smnRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
#define smnRCC_HOST_BUSNUM_DEFAULT 0x00000000
#define smnRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
#define smnRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
#define smnRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
#define smnRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
#define smnRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
#define smnRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
#define smnRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
#define smnRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
#define smnRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
#define smnRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000
#define smnRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_0_RCC_MH_ARB_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
#define smnCC_BIF_BX_STRAP0_DEFAULT 0x00000000
#define smnCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000
#define smnBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
#define smnBUS_CNTL_DEFAULT 0x00000000
#define smnBIF_SCRATCH0_DEFAULT 0x00000000
#define smnBIF_SCRATCH1_DEFAULT 0x00000000
#define smnBX_RESET_EN_DEFAULT 0x00010000
#define smnMM_CFGREGS_CNTL_DEFAULT 0x00000000
#define smnBX_RESET_CNTL_DEFAULT 0x00000000
#define smnINTERRUPT_CNTL_DEFAULT 0x00000000
#define smnINTERRUPT_CNTL2_DEFAULT 0x00000000
#define smnCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
#define smnBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000
#define smnBIF_DOORBELL_CNTL_DEFAULT 0x00000000
#define smnBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
#define smnBIF_FB_EN_DEFAULT 0x00000000
#define smnBIF_INTR_CNTL_DEFAULT 0x00000000
#define smnBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
#define smnBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
#define smnBACO_CNTL_DEFAULT 0x00000000
#define smnBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
#define smnBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200
#define smnBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
#define smnBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
#define smnBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
#define smnMEM_TYPE_CNTL_DEFAULT 0x00000000
#define smnNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000
#define smnNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000
#define smnNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001
#define smnNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002
#define smnNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003
#define smnNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004
#define smnNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005
#define smnNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006
#define smnNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007
#define smnNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008
#define smnNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009
#define smnNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a
#define smnNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b
#define smnNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c
#define smnNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d
#define smnNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e
#define smnNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f
#define smnREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
#define smnREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
#define smnBIF_RB_CNTL_DEFAULT 0x00000000
#define smnBIF_RB_BASE_DEFAULT 0x00000000
#define smnBIF_RB_RPTR_DEFAULT 0x00000000
#define smnBIF_RB_WPTR_DEFAULT 0x00000000
#define smnBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
#define smnBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
#define smnMAILBOX_INDEX_DEFAULT 0x00000000
#define smnBIF_MP1_INTR_CTRL_DEFAULT 0x00000000
#define smnBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define smnBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define smnBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
#define smnBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
#define smnBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
#define smnBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
#define smnBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
#define smnBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071
#define smnBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031
#define smnBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d
// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
#define smnBIF_BME_STATUS_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
#define smnDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
#define smnDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
#define smnDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
#define smnHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
#define smnHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
#define smnGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
#define smnGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
#define smnBIF_TRANS_PENDING_DEFAULT 0x00000000
#define smnNBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
#define smnMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
#define smnMAILBOX_CONTROL_DEFAULT 0x00000000
#define smnMAILBOX_INT_CNTL_DEFAULT 0x00000000
#define smnBIF_VMHV_MAILBOX_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
#define smnSHADOW_COMMAND_DEFAULT 0x00000000
#define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
#define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
#define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
#define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
#define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
#define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
#define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
#define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
#define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
#define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
#define smnSUC_INDEX_DEFAULT 0x00000000
#define smnSUC_DATA_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP8_DEFAULT 0x00000000
#define smnRCC_DEV1_PORT_STRAP9_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP1_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP8_DEFAULT 0x00000000
#define smnRCC_DEV2_PORT_STRAP9_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_BIF_STRAP0_DEFAULT 0x00040a00
#define smnRCC_STRAP1_RCC_BIF_STRAP1_DEFAULT 0x00400108
#define smnRCC_STRAP1_RCC_BIF_STRAP2_DEFAULT 0x000a0079
#define smnRCC_STRAP1_RCC_BIF_STRAP3_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_BIF_STRAP4_DEFAULT 0x00100010
#define smnRCC_STRAP1_RCC_BIF_STRAP5_DEFAULT 0x31130010
#define smnRCC_STRAP1_RCC_BIF_STRAP6_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF2_STRAP0_DEFAULT 0x10007316
#define smnRCC_DEV0_EPF2_STRAP2_DEFAULT 0x03002000
#define smnRCC_DEV0_EPF2_STRAP3_DEFAULT 0x0815cc59
#define smnRCC_DEV0_EPF2_STRAP4_DEFAULT 0x3c800000
#define smnRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00001002
#define smnRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000001
#define smnRCC_DEV0_EPF2_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF2_STRAP13_DEFAULT 0x000c0330
#define smnRCC_DEV0_EPF3_STRAP0_DEFAULT 0x10007314
#define smnRCC_DEV0_EPF3_STRAP2_DEFAULT 0x01002000
#define smnRCC_DEV0_EPF3_STRAP3_DEFAULT 0x0805cc51
#define smnRCC_DEV0_EPF3_STRAP4_DEFAULT 0x40000000
#define smnRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00001002
#define smnRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000001
#define smnRCC_DEV0_EPF3_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF3_STRAP13_DEFAULT 0x000c8000
#define smnRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP0_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP2_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP3_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP4_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP5_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP6_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP7_DEFAULT 0x00000000
#define smnRCC_DEV2_EPF0_STRAP13_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
#define smnRCC_DEV0_1_RCC_VDM_SUPPORT_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_BUS_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000
#define smnRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_MH_ARB_CNTL_DEFAULT 0x00000000
#define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
#define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
#define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
#define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
#define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
#define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
#define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
#define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
#define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_DEFAULT 0x00000001
#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
#define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500
#define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000
#define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
#define smnMISC_SCRATCH_DEFAULT 0x00000000
#define smnINTR_LINE_POLARITY_DEFAULT 0x00000000
#define smnINTR_LINE_ENABLE_DEFAULT 0x000000ff
#define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
#define smnBIFC_MISC_CTRL0_DEFAULT 0x08000024
#define smnBIFC_MISC_CTRL1_DEFAULT 0x90108c04
#define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000
#define smnBIFC_RCCBIH_BME_ERR_LOG0_DEFAULT 0x00000000
#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x80108010
#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x80108010
#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x80108010
#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x80108010
#define smnBIFC_DMA_ATTR_CNTL2_DEV0_DEFAULT 0x00000000
#define smnBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
#define smnBIFC_THT_CNTL_DEFAULT 0x00000111
#define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000
#define smnBIFC_GSI_CNTL_DEFAULT 0x000057c0
#define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
#define smnBIFC_PASID_CHECK_DIS_DEFAULT 0x00000001
#define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f
#define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000
#define smnBIFC_PASID_STS_DEFAULT 0x00000002
#define smnBIFC_ATHUB_ACT_CNTL_DEFAULT 0x00000004
#define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000
#define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000
#define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
#define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
#define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
#define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
#define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
#define smnNBIF_PGMST_CTRL_DEFAULT 0x00000000
#define smnNBIF_PGSLV_CTRL_DEFAULT 0x00000004
#define smnNBIF_PG_MISC_CTRL_DEFAULT 0x14006084
#define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000
#define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000
#define smnSMN_MST_CNTL1_DEFAULT 0x00000000
#define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000
#define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0061605f
#define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
#define smnNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000
#define smnNBIF_INTX_DSTATE_MISC_CNTL_DEFAULT 0x00000000
#define smnNBIF_PENDING_MISC_CNTL_DEFAULT 0x00000000
#define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00000000
#define smnBIF_GMI_WRR_WEIGHT2_DEFAULT 0x04040404
#define smnBIF_GMI_WRR_WEIGHT3_DEFAULT 0x04040404
#define smnNBIF_PWRBRK_REQUEST_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F0_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F1_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F2_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F3_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F4_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F5_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F6_DEFAULT 0x00000000
#define smnBIF_ATOMIC_ERR_LOG_DEV0_F7_DEFAULT 0x00000000
#define smnBIF_DMA_MP4_ERR_LOG_DEFAULT 0x00000000
#define smnBIF_PASID_ERR_LOG_DEFAULT 0x00000000
#define smnBIF_PASID_ERR_CLR_DEFAULT 0x00000000
#define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000
#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
#define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
#define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
#define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
#define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000100
#define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
#define smnSMN_MST_CNTL0_DEFAULT 0x00000001
#define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000
#define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000
#define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
#define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
#define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
#define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
#define smnBIFC_A2S_SDP_PORT_CTRL_DEFAULT 0x0000003f
#define smnBIFC_A2S_CNTL_SW0_DEFAULT 0x04040000
#define smnBIFC_A2S_MISC_CNTL_DEFAULT 0x0000000b
#define smnBIFC_A2S_TAG_ALLOC_0_DEFAULT 0x00000000
#define smnBIFC_A2S_TAG_ALLOC_1_DEFAULT 0x00000000
#define smnBIFC_A2S_CNTL_CL0_DEFAULT 0x00282540
#define smnBIFC_A2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
#define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_pfc_usb_RCCPFCDEC
#define smnRCC_PFC_USB_RCC_PFC_LTR_CN