// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 Avnet Embedded GmbH
 */

/dts-v1/;

#include "imx8mp-msc-sm2s-14N0600E.dtsi"
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM";
	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
		     "fsl,imx8mp";

	reg_vcc_3v3_audio: 3v3-audio-regulator {
		compatible = "regulator-fixed";
		regulator-name = "VCC_3V3_AUD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_vcc_1v8_audio: 1v8-audio-regulator {
		compatible = "regulator-fixed";
		regulator-name = "VCC_1V8_AUD";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "sgtl5000-audio";
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&codec_dai>;
		simple-audio-card,bitclock-master = <&codec_dai>;

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		codec_dai: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};
};

&i2c1 {
	sgtl5000: audio-codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;

		assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
		assigned-clock-rates = <24000000>;
		clocks = <&clk IMX8MP_CLK_CLKOUT1>;
		#sound-dai-cells = <0>;

		VDDA-supply = <&reg_vcc_3v3_audio>;
		VDDD-supply = <&reg_vcc_1v8_audio>;
		VDDIO-supply = <&reg_vcc_1v8_audio>;
	};
};

/* I2S-0 = sai2 */
&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;

	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <12288000>;

	fsl,sai-mclk-direction-output;
	status = "okay";
};

&flexcan1 {
	status = "okay";
};

&flexcan2 {
	status = "okay";
};

&usdhc2 {
	no-1-8-v;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_smarc_gpio>;

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC   0xd6
			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK    0xd6
			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
		>;
	};

	pinctrl_smarc_gpio: smarcgpiosgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x19>, /* GPIO0 */
			<MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x19>, /* GPIO1 */
			<MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x19>, /* GPIO2 */
			<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x19>, /* GPIO3 */
			<MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x19>, /* GPIO4 */
			<MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x19>, /* GPIO5 */
			<MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x19>, /* GPIO6 */
			<MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x19>, /* GPIO7 */
			<MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x19>, /* GPIO8 */
			<MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x19>, /* GPIO9 */
			<MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x19>, /* GPIO10 */
			<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x19>, /* GPIO11 */
			<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x19>, /* GPIO12 */
			<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19>; /* GPIO13 */
	};
};