blob: 2de69d56870d4372394ee5e1431ac039bb8803fd [file] [log] [blame]
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
chosen { };
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp1_uart3: serial@f991f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
timer@f9020000 {
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 2
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
};
};