arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

audio_subsys: bus@59000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x59000000 0x0 0x59000000 0x1000000>;

	audio_ipg_clk: clock-audio-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <120000000>;
		clock-output-names = "audio_ipg_clk";
	};

	dsp_lpcg: clock-controller@59580000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59580000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>,
			 <&audio_ipg_clk>,
			 <&audio_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
				<IMX_LPCG_CLK_7>;
		clock-output-names = "dsp_lpcg_adb_clk",
				     "dsp_lpcg_ipg_clk",
				     "dsp_lpcg_core_clk";
		power-domains = <&pd IMX_SC_R_DSP>;
	};

	dsp_ram_lpcg: clock-controller@59590000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59590000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_4>;
		clock-output-names = "dsp_ram_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_DSP_RAM>;
	};

	dsp: dsp@596e8000 {
		compatible = "fsl,imx8qxp-dsp";
		reg = <0x596e8000 0x88000>;
		clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
			 <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
			 <&dsp_lpcg IMX_LPCG_CLK_7>;
		clock-names = "ipg", "ocram", "core";
		power-domains = <&pd IMX_SC_R_MU_13A>,
			<&pd IMX_SC_R_MU_13B>,
			<&pd IMX_SC_R_DSP>,
			<&pd IMX_SC_R_DSP_RAM>;
		mbox-names = "txdb0", "txdb1",
			"rxdb0", "rxdb1";
		mboxes = <&lsio_mu13 2 0>,
			<&lsio_mu13 2 1>,
			<&lsio_mu13 3 0>,
			<&lsio_mu13 3 1>;
		memory-region = <&dsp_reserved>;
		status = "disabled";
	};
};