// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019-2020 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8mm-evk.dtsi"

/ {
	model = "FSL i.MX8MM EVK board";
	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";

	aliases {
		spi0 = &flexspi;
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25M {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100M {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750M {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
		>;
	};
};