| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2017~2018 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8qxp.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QXP MEK"; |
| compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; |
| |
| chosen { |
| stdout-path = &lpuart0; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x00000000 0x80000000 0 0x40000000>; |
| }; |
| |
| reg_usdhc2_vmmc: usdhc2-vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD1_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &dsp { |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; |
| status = "okay"; |
| |
| i2c-switch@71 { |
| compatible = "nxp,pca9646", "nxp,pca9546"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x71>; |
| reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; |
| |
| i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| |
| max7322: gpio@68 { |
| compatible = "maxim,max7322"; |
| reg = <0x68>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| |
| i2c@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <2>; |
| |
| pressure-sensor@60 { |
| compatible = "fsl,mpl3115"; |
| reg = <0x60>; |
| }; |
| }; |
| |
| i2c@3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <3>; |
| |
| pca9557_a: gpio@1a { |
| compatible = "nxp,pca9557"; |
| reg = <0x1a>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| pca9557_b: gpio@1d { |
| compatible = "nxp,pca9557"; |
| reg = <0x1d>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| light-sensor@44 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_isl29023>; |
| compatible = "isil,isl29023"; |
| reg = <0x44>; |
| interrupt-parent = <&lsio_gpio1>; |
| interrupts = <2 IRQ_TYPE_EDGE_FALLING>; |
| }; |
| }; |
| }; |
| }; |
| |
| &lpuart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart0>; |
| status = "okay"; |
| }; |
| |
| &scu_key { |
| status = "okay"; |
| }; |
| |
| &thermal_zones { |
| pmic-thermal0 { |
| polling-delay-passive = <250>; |
| polling-delay = <2000>; |
| thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; |
| |
| trips { |
| pmic_alert0: trip0 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| pmic_crit0: trip1 { |
| temperature = <125000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&pmic_alert0>; |
| cooling-device = |
| <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| &usdhc1 { |
| assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <200000000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| no-sd; |
| no-sdio; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; |
| assigned-clock-rates = <200000000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| bus-width = <4>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 |
| IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 |
| IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 |
| IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 |
| IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 |
| IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 |
| IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 |
| IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 |
| IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 |
| IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 |
| IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 |
| IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 |
| IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 |
| IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 |
| >; |
| }; |
| |
| pinctrl_ioexp_rst: ioexprstgrp { |
| fsl,pins = < |
| IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 |
| >; |
| }; |
| |
| pinctrl_isl29023: isl29023grp { |
| fsl,pins = < |
| IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 |
| >; |
| }; |
| |
| pinctrl_lpi2c1: lpi2c1grp { |
| fsl,pins = < |
| IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 |
| IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 |
| >; |
| }; |
| |
| pinctrl_lpuart0: lpuart0grp { |
| fsl,pins = < |
| IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 |
| IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| }; |
