[
    {
        "BriefDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PDIR_COUNTER": "na",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.",
        "SampleAfterValue": "20003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000001",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000001",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000001",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000001",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000002",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2104000002",
        "Offcore": "1",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]