[
    {
        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.ABORTED",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times HLE abort was triggered.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00001",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "20011",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00010",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.ABORTED_MEM",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x5d",
        "EventName": "TX_EXEC.MISC3",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x5d",
        "EventName": "TX_EXEC.MISC2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00002",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "101",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an RTM execution successfully committed",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.COMMIT",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times RTM commit succeeded.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of times an HLE execution successfully committed",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.COMMIT",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times HLE commit succeeded.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.STREAMING_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00800",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC08000",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00020",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Demand Data Read requests who miss L3 cache",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "2",
        "EventCode": "0xA3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Number of times an HLE execution started.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.START",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "100003",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "1009",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "50021",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "503",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0xa3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "1000003",
        "Speculative": "1",
        "UMask": "0x6"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "2003",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xcd",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "PEBS": "2",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
        "SampleAfterValue": "100007",
        "TakenAlone": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED_MEM",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00400",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FFFC00004",
        "Offcore": "1",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an RTM execution aborted.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.ABORTED",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times RTM abort was triggered.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of times an RTM execution started.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc9",
        "EventName": "RTM_RETIRED.START",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc8",
        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
        "PEBScounters": "0,1,2,3",
        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
        "SampleAfterValue": "100003",
        "Speculative": "1",
        "UMask": "0x4"
    }
]