tree 646a03ca6d4c81870066d697af1838762a5a5971
parent 6d3a47c29186aa8d26ff05a6209c94291ace0696
author Jens Kuske <jenskuske@gmail.com> 1449264280 +0100
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1449562313 +0100

clk: sunxi: Add H3 clocks support

The H3 clock control unit is similar to the those of other sun8i family
members like the A23.

It adds a new bus gates clock similar to the simple gates, but with a
different parent clock for each single gate.
Some of the gates use the new AHB2 clock as parent, whose clock source
is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
is mostly based on Allwinner kernel source code.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>