| commit | aba3c3fede54e55573954fa7a7e28ec304557e50 | [log] [tgz] |
|---|---|---|
| author | Shen, George <George.Shen@amd.com> | Mon Nov 15 22:38:18 2021 -0500 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Wed Dec 01 16:05:26 2021 -0500 |
| tree | 6fc85a130507bfda83ebfb4983d931ff0f421678 | |
| parent | 9311ed1e12417c81e1764d7656d97d9d459f9c5a [diff] |
drm/amd/display: Clear DPCD lane settings after repeater training [Why] VS and PE requested by repeater should not persist for the sink. [How] Clear DPCD lane settings after repeater link training finishes. Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>