tree edabb6be5fc1fa580b0a7d7c61f141f93d263980
parent d5a0945fdf89ad293ccaa2be588635f4bfc0cd62
author Gabriel Fernandez <gabriel.fernandez@st.com> 1489652201 +0100
committer Michael Turquette <mturquette@baylibre.com> 1492015856 +0200

clk: stm32f4: fix timeout management for pll and ready gate

Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.

Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>