commit af7f032dba8ccf7ee430a48656d25565672a6074
author Soren Brinkmann <soren.brinkmann@xilinx.com> Wed Dec 19 10:18:37 2012 -0800
committer Michal Simek <michal.simek@xilinx.com> Mon Jan 28 13:27:21 2013 +0100
tree 00594280fae0fed8a1fdc951cd46104f63922188
parent f184c5caa983940305b37f428a6bfc22105235e4

arm: zynq: timer: Remove unnecessary register write

Acknowedging an interrupt requires to read the interrupt register
only. The write was only required to work around a bug in
the QEMU implementation of the TTC, which is fixed.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>

arch/arm/mach-zynq/timer.c

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 570491d..f1d224b 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -121,8 +121,7 @@
 	struct xttcps_timer *timer = &xttce->xttc;
 
 	/* Acknowledge the interrupt and call event handler */
-	__raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET),
-			timer->base_addr + XTTCPS_ISR_OFFSET);
+	__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
 
 	xttce->ce.event_handler(&xttce->ce);