MIPS: Fix microMIPS LL/SC immediate offsets
In the microMIPS encoding some memory access instructions have their
immediate offset reduced to 12 bits only. That does not match the GCC
`R' constraint we use in some places to satisfy the requirement,
resulting in build failures like this:
{standard input}: Assembler messages:
{standard input}:720: Error: macro used $at after ".set noat"
{standard input}:720: Warning: macro instruction expanded into multiple instructions
Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to
the right constraint depending on whether microMIPS or standard MIPS
code is produced. Also apply the fix to where `m' is used as in the
worst case this change does nothing, e.g. where the pointer was already
in a register such as a function argument and no further offset was
requested, and in the best case it avoids an extraneous sequence of up
to two instructions to load the high 20 bits of the address in the LL/SC
loop. This reduces the risk of lock contention that is the higher the
more instructions there are in the critical section between LL and SC.
Strictly speaking we could just bulk-replace `R' with `ZC' as the latter
constraint adjusts automatically depending on the ISA selected.
However it was only introduced with GCC 4.9 and we keep supporing older
compilers for the standard MIPS configuration, hence the slightly more
complicated approach I chose.
The choice of a zero-argument function-like rather than an object-like
macro was made so that it does not look like a function call taking the
C expression used for the constraint as an argument. This is so as not
to confuse the reader or formatting checkers like `checkpatch.pl' and
follows previous practice.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 6dd6bfc..ec4b4d6 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -17,6 +17,7 @@
#include <linux/irqflags.h>
#include <linux/types.h>
#include <asm/barrier.h>
+#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/cmpxchg.h>
#include <asm/war.h>
@@ -53,7 +54,7 @@
" sc %0, %1 \n" \
" beqzl %0, 1b \n" \
" .set mips0 \n" \
- : "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
int temp; \
@@ -65,7 +66,7 @@
" " #asm_op " %0, %2 \n" \
" sc %0, %1 \n" \
" .set mips0 \n" \
- : "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!temp)); \
} else { \
@@ -95,7 +96,8 @@
" beqzl %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set mips0 \n" \
- : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (result), "=&r" (temp), \
+ "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
int temp; \
@@ -107,7 +109,8 @@
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" .set mips0 \n" \
- : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (result), "=&r" (temp), \
+ "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!result)); \
\
@@ -167,8 +170,9 @@
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "+m" (v->counter)
- : "Ir" (i), "m" (v->counter)
+ : "=&r" (result), "=&r" (temp),
+ "+" GCC_OFF12_ASM() (v->counter)
+ : "Ir" (i), GCC_OFF12_ASM() (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
int temp;
@@ -185,7 +189,8 @@
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "=&r" (result), "=&r" (temp),
+ "+" GCC_OFF12_ASM() (v->counter)
: "Ir" (i));
} else {
unsigned long flags;
@@ -328,7 +333,7 @@
" scd %0, %1 \n" \
" beqzl %0, 1b \n" \
" .set mips0 \n" \
- : "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
long temp; \
@@ -340,7 +345,7 @@
" " #asm_op " %0, %2 \n" \
" scd %0, %1 \n" \
" .set mips0 \n" \
- : "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!temp)); \
} else { \
@@ -370,7 +375,8 @@
" beqzl %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set mips0 \n" \
- : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
+ : "=&r" (result), "=&r" (temp), \
+ "+" GCC_OFF12_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
long temp; \
@@ -382,8 +388,9 @@
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
" .set mips0 \n" \
- : "=&r" (result), "=&r" (temp), "=m" (v->counter) \
- : "Ir" (i), "m" (v->counter) \
+ : "=&r" (result), "=&r" (temp), \
+ "=" GCC_OFF12_ASM() (v->counter) \
+ : "Ir" (i), GCC_OFF12_ASM() (v->counter) \
: "memory"); \
} while (unlikely(!result)); \
\
@@ -443,8 +450,9 @@
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
+ : "=&r" (result), "=&r" (temp),
+ "=" GCC_OFF12_ASM() (v->counter)
+ : "Ir" (i), GCC_OFF12_ASM() (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
long temp;
@@ -461,7 +469,8 @@
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "=&r" (result), "=&r" (temp),
+ "+" GCC_OFF12_ASM() (v->counter)
: "Ir" (i));
} else {
unsigned long flags;
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index bae6b0f..6663bcc 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,6 +17,7 @@
#include <linux/types.h>
#include <asm/barrier.h>
#include <asm/byteorder.h> /* sigh ... */
+#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/sgidefs.h>
#include <asm/war.h>
@@ -78,8 +79,8 @@
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*m)
+ : "ir" (1UL << bit), GCC_OFF12_ASM() (*m));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
do {
@@ -87,7 +88,7 @@
" " __LL "%0, %1 # set_bit \n"
" " __INS "%0, %3, %2, 1 \n"
" " __SC "%0, %1 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (bit), "r" (~0));
} while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
@@ -99,7 +100,7 @@
" or %0, %2 \n"
" " __SC "%0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (1UL << bit));
} while (unlikely(!temp));
} else
@@ -130,7 +131,7 @@
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (~(1UL << bit)));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
@@ -139,7 +140,7 @@
" " __LL "%0, %1 # clear_bit \n"
" " __INS "%0, $0, %2, 1 \n"
" " __SC "%0, %1 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (bit));
} while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
@@ -151,7 +152,7 @@
" and %0, %2 \n"
" " __SC "%0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (~(1UL << bit)));
} while (unlikely(!temp));
} else
@@ -196,7 +197,7 @@
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (1UL << bit));
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -209,7 +210,7 @@
" xor %0, %2 \n"
" " __SC "%0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
: "ir" (1UL << bit));
} while (unlikely(!temp));
} else
@@ -244,7 +245,7 @@
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
@@ -258,7 +259,7 @@
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} while (unlikely(!res));
@@ -312,7 +313,7 @@
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} while (unlikely(!res));
@@ -354,7 +355,7 @@
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
#ifdef CONFIG_CPU_MIPSR2
@@ -368,7 +369,7 @@
" " __EXT "%2, %0, %3, 1 \n"
" " __INS "%0, $0, %3, 1 \n"
" " __SC "%0, %1 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "ir" (bit)
: "memory");
} while (unlikely(!temp));
@@ -385,7 +386,7 @@
" xor %2, %3 \n"
" " __SC "%2, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} while (unlikely(!res));
@@ -427,7 +428,7 @@
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
@@ -441,7 +442,7 @@
" xor %2, %0, %3 \n"
" " __SC "\t%2, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
: "memory");
} while (unlikely(!res));
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index eefcaa3..28b1edf 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -10,6 +10,7 @@
#include <linux/bug.h>
#include <linux/irqflags.h>
+#include <asm/compiler.h>
#include <asm/war.h>
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
@@ -30,8 +31,8 @@
" sc %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
+ : GCC_OFF12_ASM() (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
@@ -45,8 +46,9 @@
" .set arch=r4000 \n"
" sc %2, %1 \n"
" .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
+ "=&r" (dummy)
+ : GCC_OFF12_ASM() (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
@@ -80,8 +82,8 @@
" scd %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
+ : GCC_OFF12_ASM() (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
@@ -93,8 +95,9 @@
" move %2, %z4 \n"
" scd %2, %1 \n"
" .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
+ "=&r" (dummy)
+ : GCC_OFF12_ASM() (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
@@ -155,8 +158,8 @@
" beqzl $1, 1b \n" \
"2: \n" \
" .set pop \n" \
- : "=&r" (__ret), "=R" (*m) \
- : "R" (*m), "Jr" (old), "Jr" (new) \
+ : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
+ : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
: "memory"); \
} else if (kernel_uses_llsc) { \
__asm__ __volatile__( \
@@ -172,8 +175,8 @@
" beqz $1, 1b \n" \
" .set pop \n" \
"2: \n" \
- : "=&r" (__ret), "=R" (*m) \
- : "R" (*m), "Jr" (old), "Jr" (new) \
+ : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
+ : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
: "memory"); \
} else { \
unsigned long __flags; \
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
index 71f5c5c..c73815e 100644
--- a/arch/mips/include/asm/compiler.h
+++ b/arch/mips/include/asm/compiler.h
@@ -16,4 +16,12 @@
#define GCC_REG_ACCUM "accum"
#endif
+#ifndef CONFIG_CPU_MICROMIPS
+#define GCC_OFF12_ASM() "R"
+#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
+#define GCC_OFF12_ASM() "ZC"
+#else
+#error "microMIPS compilation unsupported with GCC older than 4.9"
+#endif
+
#endif /* _ASM_COMPILER_H */
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
index 4da0c1f..ae6fedc 100644
--- a/arch/mips/include/asm/edac.h
+++ b/arch/mips/include/asm/edac.h
@@ -1,6 +1,8 @@
#ifndef ASM_EDAC_H
#define ASM_EDAC_H
+#include <asm/compiler.h>
+
/* ECC atomic, DMA, SMP and interrupt safe scrub function */
static inline void atomic_scrub(void *va, u32 size)
@@ -24,8 +26,8 @@
" sc %0, %1 \n"
" beqz %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*virt_addr)
- : "m" (*virt_addr));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*virt_addr)
+ : GCC_OFF12_ASM() (*virt_addr));
virt_addr++;
}
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 194cda0..d0177bf 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -14,6 +14,7 @@
#include <linux/uaccess.h>
#include <asm/asm-eva.h>
#include <asm/barrier.h>
+#include <asm/compiler.h>
#include <asm/errno.h>
#include <asm/war.h>
@@ -42,8 +43,10 @@
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
- : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
- : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
+ : "=r" (ret), "=&r" (oldval), \
+ "=" GCC_OFF12_ASM() (*uaddr) \
+ : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
+ "i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
__asm__ __volatile__( \
@@ -68,8 +71,10 @@
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
- : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
- : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
+ : "=r" (ret), "=&r" (oldval), \
+ "=" GCC_OFF12_ASM() (*uaddr) \
+ : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
+ "i" (-EFAULT) \
: "memory"); \
} else \
ret = -ENOSYS; \
@@ -166,8 +171,9 @@
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
- : "+r" (ret), "=&r" (val), "=R" (*uaddr)
- : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
+ : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
+ : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+ "i" (-EFAULT)
: "memory");
} else if (cpu_has_llsc) {
__asm__ __volatile__(
@@ -193,8 +199,9 @@
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
- : "+r" (ret), "=&r" (val), "=R" (*uaddr)
- : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
+ : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
+ : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+ "i" (-EFAULT)
: "memory");
} else
return -ENOSYS;
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
index fc946c8..2e54b4b 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
@@ -49,6 +49,7 @@
#include <linux/types.h>
+#include <asm/compiler.h>
#include <asm/war.h>
#ifndef R10000_LLSC_WAR
@@ -84,8 +85,8 @@
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=m" (*addr)
- : "ir" (~mask), "ir" (value), "m" (*addr));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
+ : "ir" (~mask), "ir" (value), GCC_OFF12_ASM() (*addr));
}
/*
@@ -105,8 +106,8 @@
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=m" (*addr)
- : "ir" (mask), "m" (*addr));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
+ : "ir" (mask), GCC_OFF12_ASM() (*addr));
}
/*
@@ -126,8 +127,8 @@
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=m" (*addr)
- : "ir" (~mask), "m" (*addr));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
+ : "ir" (~mask), GCC_OFF12_ASM() (*addr));
}
/*
@@ -147,8 +148,8 @@
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
- : "=&r" (temp), "=m" (*addr)
- : "ir" (mask), "m" (*addr));
+ : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
+ : "ir" (mask), GCC_OFF12_ASM() (*addr));
}
/*
@@ -219,8 +220,8 @@
" .set arch=r4000 \n" \
"1: ll %0, %1 #custom_read_reg32 \n" \
" .set pop \n" \
- : "=r" (tmp), "=m" (*address) \
- : "m" (*address))
+ : "=r" (tmp), "=" GCC_OFF12_ASM() (*address) \
+ : GCC_OFF12_ASM() (*address))
#define custom_write_reg32(address, tmp) \
__asm__ __volatile__( \
@@ -230,7 +231,7 @@
" "__beqz"%0, 1b \n" \
" nop \n" \
" .set pop \n" \
- : "=&r" (tmp), "=m" (*address) \
- : "0" (tmp), "m" (*address))
+ : "=&r" (tmp), "=" GCC_OFF12_ASM() (*address) \
+ : "0" (tmp), GCC_OFF12_ASM() (*address))
#endif /* __ASM_REGOPS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 024a71b..75739c8 100644
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -76,6 +76,8 @@
#include <linux/prefetch.h>
+#include <asm/compiler.h>
+
#include <asm/octeon/cvmx-fpa.h>
/**
* By default we disable the max depth support. Most programs
@@ -273,7 +275,7 @@
" lbu %[ticket], %[now_serving]\n"
"4:\n"
".set pop\n" :
- [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
+ [ticket_ptr] "=" GCC_OFF12_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
[now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
[my_ticket] "=r"(my_ticket)
);
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 78d201f..c6d06d3 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -12,6 +12,7 @@
#include <linux/compiler.h>
#include <asm/barrier.h>
+#include <asm/compiler.h>
#include <asm/war.h>
/*
@@ -88,7 +89,7 @@
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"
- : [ticket_ptr] "+m" (lock->lock),
+ : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
[serving_now_ptr] "+m" (lock->h.serving_now),
[ticket] "=&r" (tmp),
[my_ticket] "=&r" (my_ticket)
@@ -121,7 +122,7 @@
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"
- : [ticket_ptr] "+m" (lock->lock),
+ : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
[serving_now_ptr] "+m" (lock->h.serving_now),
[ticket] "=&r" (tmp),
[my_ticket] "=&r" (my_ticket)
@@ -163,7 +164,7 @@
" li %[ticket], 0 \n"
" .previous \n"
" .set pop \n"
- : [ticket_ptr] "+m" (lock->lock),
+ : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
[ticket] "=&r" (tmp),
[my_ticket] "=&r" (tmp2),
[now_serving] "=&r" (tmp3)
@@ -187,7 +188,7 @@
" li %[ticket], 0 \n"
" .previous \n"
" .set pop \n"
- : [ticket_ptr] "+m" (lock->lock),
+ : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
[ticket] "=&r" (tmp),
[my_ticket] "=&r" (tmp2),
[now_serving] "=&r" (tmp3)
@@ -234,8 +235,8 @@
" beqzl %1, 1b \n"
" nop \n"
" .set reorder \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} else {
do {
@@ -244,8 +245,8 @@
" bltz %1, 1b \n"
" addu %1, 1 \n"
"2: sc %1, %0 \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} while (unlikely(!tmp));
}
@@ -268,8 +269,8 @@
" sub %1, 1 \n"
" sc %1, %0 \n"
" beqzl %1, 1b \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} else {
do {
@@ -277,8 +278,8 @@
"1: ll %1, %2 # arch_read_unlock \n"
" sub %1, 1 \n"
" sc %1, %0 \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} while (unlikely(!tmp));
}
@@ -298,8 +299,8 @@
" beqzl %1, 1b \n"
" nop \n"
" .set reorder \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} else {
do {
@@ -308,8 +309,8 @@
" bnez %1, 1b \n"
" lui %1, 0x8000 \n"
"2: sc %1, %0 \n"
- : "=m" (rw->lock), "=&r" (tmp)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} while (unlikely(!tmp));
}
@@ -348,8 +349,8 @@
__WEAK_LLSC_MB
" li %2, 1 \n"
"2: \n"
- : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} else {
__asm__ __volatile__(
@@ -365,8 +366,8 @@
__WEAK_LLSC_MB
" li %2, 1 \n"
"2: \n"
- : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
}
@@ -392,8 +393,8 @@
" li %2, 1 \n"
" .set reorder \n"
"2: \n"
- : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} else {
do {
@@ -405,8 +406,9 @@
" sc %1, %0 \n"
" li %2, 1 \n"
"2: \n"
- : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
- : "m" (rw->lock)
+ : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp),
+ "=&r" (ret)
+ : GCC_OFF12_ASM() (rw->lock)
: "memory");
} while (unlikely(!tmp));
