| commit | b1240a39511b9206293b82ac372c5114d6e15821 | [log] [tgz] |
|---|---|---|
| author | Chen Wang <unicorn_wang@outlook.com> | Fri Nov 24 14:26:02 2023 +0800 |
| committer | Chen Wang <unicorn_wang@outlook.com> | Tue Jul 09 08:19:52 2024 +0800 |
| tree | f77a2325aaa3553b48b1da70f20cee3b02d393e4 | |
| parent | 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 [diff] |
riscv: dts: add clock generator for Sophgo SG2042 SoC Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Guo Ren <guoren@kernel.org>