tree 8cc3c51f4d367633fe1a3fc80d8630e5f961d73f
parent edc609fd19e1cd1b6d0125915195a28c107a293b
author Ritesh Harjani <riteshh@codeaurora.org> 1479710241 +0530
committer Ulf Hansson <ulf.hansson@linaro.org> 1480406717 +0100

mmc: sdhci-msm: Add clock changes for DDR mode.

SDHC MSM controller need 2x clock for MCLK at GCC.
Hence make required changes to have 2x clock for
DDR timing modes.

Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>