/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _nbio_7_11_0_SH_MASK_HEADER
#define _nbio_7_11_0_SH_MASK_HEADER


// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
//NB_VENDOR_ID
#define NB_VENDOR_ID__VENDOR_ID__SHIFT                                                                        0x0
#define NB_VENDOR_ID__VENDOR_ID_MASK                                                                          0xFFFFL
//NB_DEVICE_ID
#define NB_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
#define NB_DEVICE_ID__DEVICE_ID_MASK                                                                          0xFFFFL
//NB_COMMAND
#define NB_COMMAND__IO_ACCESS_EN__SHIFT                                                                       0x0
#define NB_COMMAND__MEM_ACCESS_EN__SHIFT                                                                      0x1
#define NB_COMMAND__BUS_MASTER_EN__SHIFT                                                                      0x2
#define NB_COMMAND__IO_ACCESS_EN_MASK                                                                         0x0001L
#define NB_COMMAND__MEM_ACCESS_EN_MASK                                                                        0x0002L
#define NB_COMMAND__BUS_MASTER_EN_MASK                                                                        0x0004L
//NB_STATUS
#define NB_STATUS__CAP_LIST__SHIFT                                                                            0x4
#define NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                               0xc
#define NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                               0xd
#define NB_STATUS__CAP_LIST_MASK                                                                              0x0010L
#define NB_STATUS__RECEIVED_TARGET_ABORT_MASK                                                                 0x1000L
#define NB_STATUS__RECEIVED_MASTER_ABORT_MASK                                                                 0x2000L
//NB_SUB_CLASS
#define NB_SUB_CLASS__SUB_CLASS_INF__SHIFT                                                                    0x0
#define NB_SUB_CLASS__SUB_CLASS_INF_MASK                                                                      0xFFL
//NB_BASE_CODE
#define NB_BASE_CODE__BASE_CLASS_CODE__SHIFT                                                                  0x0
#define NB_BASE_CODE__BASE_CLASS_CODE_MASK                                                                    0xFFL
//NB_CACHE_LINE
#define NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                                 0x0
#define NB_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                                   0xFFL
//NB_LATENCY
#define NB_LATENCY__LATENCY_TIMER__SHIFT                                                                      0x0
#define NB_LATENCY__LATENCY_TIMER_MASK                                                                        0xFFL
//NB_HEADER
#define NB_HEADER__HEADER_TYPE__SHIFT                                                                         0x0
#define NB_HEADER__DEVICE_TYPE__SHIFT                                                                         0x7
#define NB_HEADER__HEADER_TYPE_MASK                                                                           0x7FL
#define NB_HEADER__DEVICE_TYPE_MASK                                                                           0x80L
//NB_ADAPTER_ID
#define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                                             0x0
#define NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                                    0x10
#define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                               0x0000FFFFL
#define NB_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                                      0xFFFF0000L
//NB_CAPABILITIES_PTR
#define NB_CAPABILITIES_PTR__CAP_PTR__SHIFT                                                                   0x0
#define NB_CAPABILITIES_PTR__CAP_PTR_MASK                                                                     0x000000FFL
//NB_HEADER_W
#define NB_HEADER_W__DEVICE_TYPE__SHIFT                                                                       0x7
#define NB_HEADER_W__DEVICE_TYPE_MASK                                                                         0x00000080L
//NB_PCI_CTRL
#define NB_PCI_CTRL__PMEDis__SHIFT                                                                            0x4
#define NB_PCI_CTRL__SErrDis__SHIFT                                                                           0x5
#define NB_PCI_CTRL__MMIOEnable__SHIFT                                                                        0x17
#define NB_PCI_CTRL__HPDis__SHIFT                                                                             0x1a
#define NB_PCI_CTRL__PMEDis_MASK                                                                              0x00000010L
#define NB_PCI_CTRL__SErrDis_MASK                                                                             0x00000020L
#define NB_PCI_CTRL__MMIOEnable_MASK                                                                          0x00800000L
#define NB_PCI_CTRL__HPDis_MASK                                                                               0x04000000L
//NB_ADAPTER_ID_W
#define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                           0x0
#define NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                                  0x10
#define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                             0x0000FFFFL
#define NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                                    0xFFFF0000L
//NBCFG_SCRATCH_0
#define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT                                                               0x0
#define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK                                                                 0xFFFFFFFFL
//NBCFG_SCRATCH_1
#define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT                                                               0x0
#define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK                                                                 0xFFFFFFFFL
//NBCFG_SCRATCH_2
#define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT                                                               0x0
#define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK                                                                 0xFFFFFFFFL
//NBCFG_SCRATCH_3
#define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT                                                               0x0
#define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK                                                                 0xFFFFFFFFL
//NBCFG_SCRATCH_4
#define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT                                                               0x0
#define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK                                                                 0xFFFFFFFFL
//NB_PCI_ARB
#define NB_PCI_ARB__VGA_HOLE__SHIFT                                                                           0x3
#define NB_PCI_ARB__PMEMode__SHIFT                                                                            0x8
#define NB_PCI_ARB__PMETurnOff__SHIFT                                                                         0x9
#define NB_PCI_ARB__PMETOAckStatus__SHIFT                                                                     0xa
#define NB_PCI_ARB__PMETarget__SHIFT                                                                          0x10
#define NB_PCI_ARB__VGA_HOLE_MASK                                                                             0x00000008L
#define NB_PCI_ARB__PMEMode_MASK                                                                              0x00000100L
#define NB_PCI_ARB__PMETurnOff_MASK                                                                           0x00000200L
#define NB_PCI_ARB__PMETOAckStatus_MASK                                                                       0x00000400L
#define NB_PCI_ARB__PMETarget_MASK                                                                            0x00FF0000L
//NB_DRAM_SLOT1_BASE
#define NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT                                                                  0x17
#define NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK                                                                    0xFF800000L
//NB_INDEX_DATA_MUTEX0
#define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT                                                     0x0
#define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT                                              0x1f
#define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK                                                       0x7FFFFFFFL
#define NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK                                                0x80000000L
//NB_INDEX_DATA_MUTEX1
#define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT                                                     0x0
#define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT                                              0x1f
#define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK                                                       0x7FFFFFFFL
#define NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK                                                0x80000000L
//NB_VENDOR_ID_W
#define NB_VENDOR_ID_W__VENDOR_ID__SHIFT                                                                      0x0
#define NB_VENDOR_ID_W__VENDOR_ID_MASK                                                                        0xFFFFL
//NB_DEVICE_ID_W
#define NB_DEVICE_ID_W__DEVICE_ID__SHIFT                                                                      0x0
#define NB_DEVICE_ID_W__DEVICE_ID_MASK                                                                        0xFFFFL


// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
//BIF_CFG_DEV0_RC_VENDOR_ID
#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV0_RC_DEVICE_ID
#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV0_RC_COMMAND
#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
//BIF_CFG_DEV0_RC_STATUS
#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
//BIF_CFG_DEV0_RC_REVISION_ID
#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
//BIF_CFG_DEV0_RC_PROG_INTERFACE
#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
//BIF_CFG_DEV0_RC_SUB_CLASS
#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
//BIF_CFG_DEV0_RC_BASE_CLASS
#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_RC_CACHE_LINE
#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
//BIF_CFG_DEV0_RC_LATENCY
#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
//BIF_CFG_DEV0_RC_HEADER
#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
//BIF_CFG_DEV0_RC_BIST
#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT                                                                0x0
#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT                                                                0x6
#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK                                                                  0x40L
#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK                                                                   0x80L
//BIF_CFG_DEV0_RC_BASE_ADDR_1
#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_BASE_ADDR_2
#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                          0x8
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                            0x10
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                0x18
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                              0x000000FFL
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                            0x0000FF00L
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                              0x00FF0000L
#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                  0xFF000000L
//BIF_CFG_DEV0_RC_IO_BASE_LIMIT
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT                                                         0x4
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                        0xc
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                      0x000FL
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK                                                           0x00F0L
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                     0x0F00L
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK                                                          0xF000L
//BIF_CFG_DEV0_RC_SECONDARY_STATUS
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                   0x5
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                            0x7
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                0x9
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                          0xb
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                        0xc
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                        0xd
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                        0xe
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK                                                     0x0020L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                              0x0080L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                  0x0600L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                            0x0800L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                          0x1000L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                          0x2000L
#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                          0x4000L
//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                 0x4
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                 0x10
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                0x14
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                   0x0000FFF0L
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                           0x4
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                              0x0000000FL
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                             0x0000FFF0L
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_RC_PREF_BASE_UPPER
#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER
#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                               0x10
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_RC_CAP_PTR
#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
//BIF_CFG_DEV0_RC_ROM_BASE_ADDR
#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_RC_INTERRUPT_LINE
#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
//BIF_CFG_DEV0_RC_INTERRUPT_PIN
#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
//BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                        0x3
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                       0x4
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                             0x5
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                           0x6
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                   0x7
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                         0x8
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                       0x9
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                          0xa
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                     0xb
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                              0x0001L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                          0x0008L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                         0x0010L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                               0x0020L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                             0x0040L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                     0x0080L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                           0x0100L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                         0x0200L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                            0x0400L
#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                       0x0800L
//BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                   0x01L
//BIF_CFG_DEV0_RC_PMI_CAP_LIST
#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV0_RC_PMI_CAP
#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_RC_PCIE_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV0_RC_PCIE_CAP
#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
//BIF_CFG_DEV0_RC_DEVICE_CAP
#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
//BIF_CFG_DEV0_RC_DEVICE_CNTL
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
//BIF_CFG_DEV0_RC_DEVICE_STATUS
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
//BIF_CFG_DEV0_RC_LINK_CAP
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
//BIF_CFG_DEV0_RC_LINK_CNTL
#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                        0x2
#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                          0x0004L
#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
//BIF_CFG_DEV0_RC_LINK_STATUS
#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
//BIF_CFG_DEV0_RC_SLOT_CAP
#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                               0x1
#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                   0x2
#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                               0x3
#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                0x4
#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                     0x5
#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                      0x6
#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                 0x7
#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                        0x11
#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                       0x12
#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                    0x13
#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                    0x00000001L
#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                 0x00000002L
#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                     0x00000004L
#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                  0x00000010L
#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                        0x00000040L
#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                   0x00007F80L
#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                   0x00018000L
#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                          0x00020000L
#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                         0x00040000L
#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                      0xFFF80000L
//BIF_CFG_DEV0_RC_SLOT_CNTL
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                               0x1
#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                               0x2
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                          0x3
#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                 0x6
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                  0x8
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                 0xa
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                          0xb
#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                 0xc
#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                         0xd
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                 0x0002L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                            0x0008L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                   0x00C0L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                    0x0300L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                   0x0400L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                            0x0800L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                   0x1000L
#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                           0x2000L
//BIF_CFG_DEV0_RC_SLOT_STATUS
#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                0x1
#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                0x2
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                           0x3
#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                 0x4
#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                  0x5
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                             0x6
#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                  0x8
#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                 0x0001L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                  0x0002L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                  0x0004L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                             0x0008L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                   0x0010L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                    0x0020L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                               0x0040L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                        0x0080L
#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                    0x0100L
//BIF_CFG_DEV0_RC_ROOT_CNTL
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                             0x1
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                          0x4
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                               0x0002L
#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                            0x0010L
//BIF_CFG_DEV0_RC_ROOT_CAP
#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                0x0001L
//BIF_CFG_DEV0_RC_ROOT_STATUS
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT                                                        0x10
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT                                                       0x11
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK                                                          0x00010000L
#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK                                                         0x00020000L
//BIF_CFG_DEV0_RC_DEVICE_CAP2
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_RC_DEVICE_CNTL2
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
//BIF_CFG_DEV0_RC_DEVICE_STATUS2
#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_RC_LINK_CAP2
#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                            0x9
#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                              0x0000FE00L
#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
//BIF_CFG_DEV0_RC_LINK_CNTL2
#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
//BIF_CFG_DEV0_RC_LINK_STATUS2
#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
//BIF_CFG_DEV0_RC_SLOT_CAP2
#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED__SHIFT                                                            0x0
#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED_MASK                                                              0xFFFFFFFFL
//BIF_CFG_DEV0_RC_SLOT_CNTL2
#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK                                                             0xFFFFL
//BIF_CFG_DEV0_RC_SLOT_STATUS2
#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_RC_MSI_CAP_LIST
#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV0_RC_MSI_MSG_CNTL
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_MSI_MSG_DATA
#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
//BIF_CFG_DEV0_RC_SSID_CAP_LIST
#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV0_RC_SSID_CAP
#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                         0x10
#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK                                                           0xFFFF0000L
//BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_RC_MSI_MAP_CAP
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN__SHIFT                                                                0x0
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD__SHIFT                                                              0x1
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                          0xb
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN_MASK                                                                  0x0001L
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD_MASK                                                                0x0002L
#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE_MASK                                                            0xF800L
//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                            0x5
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                             0x6
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                              0x00000020L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                               0x00000040L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                            0x2
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                               0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                           0x00000002L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                              0x00000004L
//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                       0x1
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                  0x2
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                             0x3
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                0x4
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                  0x5
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                     0x6
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                      0x1b
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                              0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                         0x00000002L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                    0x00000004L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                               0x00000008L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                  0x00000010L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                    0x00000020L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                       0x00000040L
#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                        0xF8000000L
//BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                     0x10
#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                       0x9
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                         0x0000FE00L
//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV0_RC_PCIE_ACS_CAP
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
//BIF_CFG_DEV0_RC_LINK_CAP_16GT
#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC_LINK_CNTL_16GT
#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_RC_LINK_STATUS_16GT
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV0_RC_RTR_DATA1
#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME__SHIFT                                                           0xc
#define BIF_CFG_DEV0_RC_RTR_DATA1__VALID__SHIFT                                                               0x1f
#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME_MASK                                                             0x00FFF000L
#define BIF_CFG_DEV0_RC_RTR_DATA1__VALID_MASK                                                                 0x80000000L
//BIF_CFG_DEV0_RC_RTR_DATA2
#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME__SHIFT                                                            0x0
#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                        0xc
#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME_MASK                                                              0x00000FFFL
#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME_MASK                                                          0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
//BIF_CFG_DEV1_RC_VENDOR_ID
#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV1_RC_DEVICE_ID
#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV1_RC_COMMAND
#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
//BIF_CFG_DEV1_RC_STATUS
#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
//BIF_CFG_DEV1_RC_REVISION_ID
#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
//BIF_CFG_DEV1_RC_PROG_INTERFACE
#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
//BIF_CFG_DEV1_RC_SUB_CLASS
#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
//BIF_CFG_DEV1_RC_BASE_CLASS
#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV1_RC_CACHE_LINE
#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
//BIF_CFG_DEV1_RC_LATENCY
#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
//BIF_CFG_DEV1_RC_HEADER
#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
//BIF_CFG_DEV1_RC_BIST
#define BIF_CFG_DEV1_RC_BIST__BIST_COMP__SHIFT                                                                0x0
#define BIF_CFG_DEV1_RC_BIST__BIST_STRT__SHIFT                                                                0x6
#define BIF_CFG_DEV1_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
#define BIF_CFG_DEV1_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
#define BIF_CFG_DEV1_RC_BIST__BIST_STRT_MASK                                                                  0x40L
#define BIF_CFG_DEV1_RC_BIST__BIST_CAP_MASK                                                                   0x80L
//BIF_CFG_DEV1_RC_BASE_ADDR_1
#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_BASE_ADDR_2
#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                          0x8
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                            0x10
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                0x18
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                              0x000000FFL
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                            0x0000FF00L
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                              0x00FF0000L
#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                  0xFF000000L
//BIF_CFG_DEV1_RC_IO_BASE_LIMIT
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE__SHIFT                                                         0x4
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                        0xc
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                      0x000FL
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_MASK                                                           0x00F0L
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                     0x0F00L
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_MASK                                                          0xF000L
//BIF_CFG_DEV1_RC_SECONDARY_STATUS
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                   0x5
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                            0x7
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                0x9
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                          0xb
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                        0xc
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                        0xd
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                        0xe
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP_MASK                                                     0x0020L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                              0x0080L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                  0x0600L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                            0x0800L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                          0x1000L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                          0x2000L
#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                          0x4000L
//BIF_CFG_DEV1_RC_MEM_BASE_LIMIT
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                 0x4
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                 0x10
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                0x14
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                    0x0000000FL
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                   0x0000FFF0L
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
//BIF_CFG_DEV1_RC_PREF_BASE_LIMIT
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                           0x4
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                              0x0000000FL
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                             0x0000FFF0L
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_RC_PREF_BASE_UPPER
#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER
#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                               0x10
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV1_RC_CAP_PTR
#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
//BIF_CFG_DEV1_RC_ROM_BASE_ADDR
#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_RC_INTERRUPT_LINE
#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
//BIF_CFG_DEV1_RC_INTERRUPT_PIN
#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
//BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                        0x3
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                       0x4
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                             0x5
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                           0x6
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                   0x7
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                         0x8
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                       0x9
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                          0xa
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                     0xb
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                              0x0001L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                          0x0008L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                         0x0010L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                               0x0020L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                             0x0040L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                     0x0080L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                           0x0100L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                         0x0200L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                            0x0400L
#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                       0x0800L
//BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                   0x01L
//BIF_CFG_DEV1_RC_PMI_CAP_LIST
#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV1_RC_PMI_CAP
#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
//BIF_CFG_DEV1_RC_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
//BIF_CFG_DEV1_RC_PCIE_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV1_RC_PCIE_CAP
#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
//BIF_CFG_DEV1_RC_DEVICE_CAP
#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
//BIF_CFG_DEV1_RC_DEVICE_CNTL
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
//BIF_CFG_DEV1_RC_DEVICE_STATUS
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
//BIF_CFG_DEV1_RC_LINK_CAP
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
//BIF_CFG_DEV1_RC_LINK_CNTL
#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                        0x2
#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
#define BIF_CFG_DEV1_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                          0x0004L
#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
//BIF_CFG_DEV1_RC_LINK_STATUS
#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
//BIF_CFG_DEV1_RC_SLOT_CAP
#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                               0x1
#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                   0x2
#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                               0x3
#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                0x4
#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                     0x5
#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                      0x6
#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                 0x7
#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                 0xf
#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                        0x11
#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                       0x12
#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                    0x13
#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                    0x00000001L
#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                 0x00000002L
#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                     0x00000004L
#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                 0x00000008L
#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                  0x00000010L
#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                       0x00000020L
#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                        0x00000040L
#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                   0x00007F80L
#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                   0x00018000L
#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                          0x00020000L
#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                         0x00040000L
#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                      0xFFF80000L
//BIF_CFG_DEV1_RC_SLOT_CNTL
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                               0x1
#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                               0x2
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                          0x3
#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                           0x4
#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                 0x6
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                  0x8
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                 0xa
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                          0xb
#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                 0xc
#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                         0xd
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                0x0001L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                 0x0002L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                            0x0008L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                             0x0010L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                   0x00C0L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                    0x0300L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                   0x0400L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                            0x0800L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                   0x1000L
#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                           0x2000L
//BIF_CFG_DEV1_RC_SLOT_STATUS
#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                0x1
#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                0x2
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                           0x3
#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                 0x4
#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                  0x5
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                             0x6
#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                  0x8
#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                 0x0001L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                  0x0002L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                  0x0004L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                             0x0008L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                   0x0010L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                    0x0020L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                               0x0040L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                        0x0080L
#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                    0x0100L
//BIF_CFG_DEV1_RC_ROOT_CNTL
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                             0x1
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                0x2
#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                          0x4
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                               0x0002L
#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                            0x0010L
//BIF_CFG_DEV1_RC_ROOT_CAP
#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                0x0001L
//BIF_CFG_DEV1_RC_ROOT_STATUS
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS__SHIFT                                                        0x10
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING__SHIFT                                                       0x11
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS_MASK                                                          0x00010000L
#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING_MASK                                                         0x00020000L
//BIF_CFG_DEV1_RC_DEVICE_CAP2
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV1_RC_DEVICE_CNTL2
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
//BIF_CFG_DEV1_RC_DEVICE_STATUS2
#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_RC_LINK_CAP2
#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                            0x9
#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                              0x0000FE00L
#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
//BIF_CFG_DEV1_RC_LINK_CNTL2
#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
//BIF_CFG_DEV1_RC_LINK_STATUS2
#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
//BIF_CFG_DEV1_RC_SLOT_CAP2
#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED__SHIFT                                                            0x0
#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED_MASK                                                              0xFFFFFFFFL
//BIF_CFG_DEV1_RC_SLOT_CNTL2
#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED_MASK                                                             0xFFFFL
//BIF_CFG_DEV1_RC_SLOT_STATUS2
#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_RC_MSI_CAP_LIST
#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV1_RC_MSI_MSG_CNTL
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_MSI_MSG_DATA
#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
//BIF_CFG_DEV1_RC_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
//BIF_CFG_DEV1_RC_SSID_CAP_LIST
#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV1_RC_SSID_CAP
#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                         0x10
#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID_MASK                                                           0xFFFF0000L
//BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV1_RC_MSI_MAP_CAP
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN__SHIFT                                                                0x0
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD__SHIFT                                                              0x1
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                          0xb
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN_MASK                                                                  0x0001L
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD_MASK                                                                0x0002L
#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE_MASK                                                            0xF800L
//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
//BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                            0x5
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                             0x6
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                              0x00000020L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                               0x00000040L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
//BIF_CFG_DEV1_RC_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                         0x1
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                            0x2
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                               0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                           0x00000002L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                              0x00000004L
//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                       0x1
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                  0x2
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                             0x3
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                0x4
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                  0x5
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                     0x6
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                      0x1b
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                              0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                         0x00000002L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                    0x00000004L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                               0x00000008L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                  0x00000010L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                    0x00000020L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                       0x00000040L
#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                        0xF8000000L
//BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                     0x10
#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                       0x9
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                         0x0000FE00L
//BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
//BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV1_RC_PCIE_ACS_CAP
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
//BIF_CFG_DEV1_RC_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
//BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
//BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
//BIF_CFG_DEV1_RC_LINK_CAP_16GT
#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC_LINK_CNTL_16GT
#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_RC_LINK_STATUS_16GT
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
//BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_RC_MARGINING_PORT_CAP
#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
//BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS
#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV1_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV1_RC_RTR_DATA1
#define BIF_CFG_DEV1_RC_RTR_DATA1__RESET_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC_RTR_DATA1__DLUP_TIME__SHIFT                                                           0xc
#define BIF_CFG_DEV1_RC_RTR_DATA1__VALID__SHIFT                                                               0x1f
#define BIF_CFG_DEV1_RC_RTR_DATA1__RESET_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV1_RC_RTR_DATA1__DLUP_TIME_MASK                                                             0x00FFF000L
#define BIF_CFG_DEV1_RC_RTR_DATA1__VALID_MASK                                                                 0x80000000L
//BIF_CFG_DEV1_RC_RTR_DATA2
#define BIF_CFG_DEV1_RC_RTR_DATA2__FLR_TIME__SHIFT                                                            0x0
#define BIF_CFG_DEV1_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                        0xc
#define BIF_CFG_DEV1_RC_RTR_DATA2__FLR_TIME_MASK                                                              0x00000FFFL
#define BIF_CFG_DEV1_RC_RTR_DATA2__D3HOTD0_TIME_MASK                                                          0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
//BIF_CFG_DEV2_RC_VENDOR_ID
#define BIF_CFG_DEV2_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV2_RC_DEVICE_ID
#define BIF_CFG_DEV2_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
//BIF_CFG_DEV2_RC_COMMAND
#define BIF_CFG_DEV2_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
#define BIF_CFG_DEV2_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
#define BIF_CFG_DEV2_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
#define BIF_CFG_DEV2_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
#define BIF_CFG_DEV2_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
#define BIF_CFG_DEV2_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV2_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
#define BIF_CFG_DEV2_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
#define BIF_CFG_DEV2_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
#define BIF_CFG_DEV2_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
#define BIF_CFG_DEV2_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
#define BIF_CFG_DEV2_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
#define BIF_CFG_DEV2_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
#define BIF_CFG_DEV2_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
#define BIF_CFG_DEV2_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
#define BIF_CFG_DEV2_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV2_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
#define BIF_CFG_DEV2_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
#define BIF_CFG_DEV2_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
#define BIF_CFG_DEV2_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
//BIF_CFG_DEV2_RC_STATUS
#define BIF_CFG_DEV2_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
#define BIF_CFG_DEV2_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
#define BIF_CFG_DEV2_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
#define BIF_CFG_DEV2_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
#define BIF_CFG_DEV2_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
#define BIF_CFG_DEV2_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
#define BIF_CFG_DEV2_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
#define BIF_CFG_DEV2_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
#define BIF_CFG_DEV2_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
#define BIF_CFG_DEV2_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
#define BIF_CFG_DEV2_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
#define BIF_CFG_DEV2_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
#define BIF_CFG_DEV2_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
#define BIF_CFG_DEV2_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
#define BIF_CFG_DEV2_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
#define BIF_CFG_DEV2_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
#define BIF_CFG_DEV2_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
#define BIF_CFG_DEV2_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
#define BIF_CFG_DEV2_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
#define BIF_CFG_DEV2_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
//BIF_CFG_DEV2_RC_REVISION_ID
#define BIF_CFG_DEV2_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
#define BIF_CFG_DEV2_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
#define BIF_CFG_DEV2_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
//BIF_CFG_DEV2_RC_PROG_INTERFACE
#define BIF_CFG_DEV2_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
//BIF_CFG_DEV2_RC_SUB_CLASS
#define BIF_CFG_DEV2_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
//BIF_CFG_DEV2_RC_BASE_CLASS
#define BIF_CFG_DEV2_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_RC_CACHE_LINE
#define BIF_CFG_DEV2_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
#define BIF_CFG_DEV2_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
//BIF_CFG_DEV2_RC_LATENCY
#define BIF_CFG_DEV2_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
//BIF_CFG_DEV2_RC_HEADER
#define BIF_CFG_DEV2_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
#define BIF_CFG_DEV2_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
#define BIF_CFG_DEV2_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
#define BIF_CFG_DEV2_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
//BIF_CFG_DEV2_RC_BIST
#define BIF_CFG_DEV2_RC_BIST__BIST_COMP__SHIFT                                                                0x0
#define BIF_CFG_DEV2_RC_BIST__BIST_STRT__SHIFT                                                                0x6
#define BIF_CFG_DEV2_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
#define BIF_CFG_DEV2_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
#define BIF_CFG_DEV2_RC_BIST__BIST_STRT_MASK                                                                  0x40L
#define BIF_CFG_DEV2_RC_BIST__BIST_CAP_MASK                                                                   0x80L
//BIF_CFG_DEV2_RC_BASE_ADDR_1
#define BIF_CFG_DEV2_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_BASE_ADDR_2
#define BIF_CFG_DEV2_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                          0x8
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                            0x10
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                0x18
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                              0x000000FFL
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                            0x0000FF00L
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                              0x00FF0000L
#define BIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                  0xFF000000L
//BIF_CFG_DEV2_RC_IO_BASE_LIMIT
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE__SHIFT                                                         0x4
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                        0xc
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                      0x000FL
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_BASE_MASK                                                           0x00F0L
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                     0x0F00L
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT__IO_LIMIT_MASK                                                          0xF000L
//BIF_CFG_DEV2_RC_SECONDARY_STATUS
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                   0x5
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                            0x7
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                0x9
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                          0xb
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                        0xc
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                        0xd
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                        0xe
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__PCI_66_CAP_MASK                                                     0x0020L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                              0x0080L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                  0x0600L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                            0x0800L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                          0x1000L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                          0x2000L
#define BIF_CFG_DEV2_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                          0x4000L
//BIF_CFG_DEV2_RC_MEM_BASE_LIMIT
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                 0x4
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                 0x10
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                0x14
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                    0x0000000FL
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                   0x0000FFF0L
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
#define BIF_CFG_DEV2_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
//BIF_CFG_DEV2_RC_PREF_BASE_LIMIT
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                           0x4
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                              0x0000000FL
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                             0x0000FFF0L
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_RC_PREF_BASE_UPPER
#define BIF_CFG_DEV2_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER
#define BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                               0x10
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV2_RC_CAP_PTR
#define BIF_CFG_DEV2_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
#define BIF_CFG_DEV2_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
//BIF_CFG_DEV2_RC_ROM_BASE_ADDR
#define BIF_CFG_DEV2_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_RC_INTERRUPT_LINE
#define BIF_CFG_DEV2_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
//BIF_CFG_DEV2_RC_INTERRUPT_PIN
#define BIF_CFG_DEV2_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
//BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                        0x3
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                       0x4
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                             0x5
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                           0x6
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                   0x7
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                         0x8
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                       0x9
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                          0xa
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                     0xb
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                              0x0001L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                          0x0008L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                         0x0010L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                               0x0020L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                             0x0040L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                     0x0080L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                           0x0100L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                         0x0200L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                            0x0400L
#define BIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                       0x0800L
//BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                   0x01L
//BIF_CFG_DEV2_RC_PMI_CAP_LIST
#define BIF_CFG_DEV2_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV2_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV2_RC_PMI_CAP
#define BIF_CFG_DEV2_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
#define BIF_CFG_DEV2_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
#define BIF_CFG_DEV2_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
#define BIF_CFG_DEV2_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
#define BIF_CFG_DEV2_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
#define BIF_CFG_DEV2_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
#define BIF_CFG_DEV2_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
#define BIF_CFG_DEV2_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
#define BIF_CFG_DEV2_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
#define BIF_CFG_DEV2_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
#define BIF_CFG_DEV2_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
#define BIF_CFG_DEV2_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
#define BIF_CFG_DEV2_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
#define BIF_CFG_DEV2_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
#define BIF_CFG_DEV2_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
#define BIF_CFG_DEV2_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
//BIF_CFG_DEV2_RC_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
#define BIF_CFG_DEV2_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_RC_PCIE_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV2_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV2_RC_PCIE_CAP
#define BIF_CFG_DEV2_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV2_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
#define BIF_CFG_DEV2_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
#define BIF_CFG_DEV2_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
#define BIF_CFG_DEV2_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
#define BIF_CFG_DEV2_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
#define BIF_CFG_DEV2_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
#define BIF_CFG_DEV2_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
//BIF_CFG_DEV2_RC_DEVICE_CAP
#define BIF_CFG_DEV2_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
#define BIF_CFG_DEV2_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
#define BIF_CFG_DEV2_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
#define BIF_CFG_DEV2_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
#define BIF_CFG_DEV2_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
#define BIF_CFG_DEV2_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
#define BIF_CFG_DEV2_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
//BIF_CFG_DEV2_RC_DEVICE_CNTL
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
//BIF_CFG_DEV2_RC_DEVICE_STATUS
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
#define BIF_CFG_DEV2_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
//BIF_CFG_DEV2_RC_LINK_CAP
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
#define BIF_CFG_DEV2_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV2_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
#define BIF_CFG_DEV2_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
#define BIF_CFG_DEV2_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
#define BIF_CFG_DEV2_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
#define BIF_CFG_DEV2_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
#define BIF_CFG_DEV2_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
#define BIF_CFG_DEV2_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
#define BIF_CFG_DEV2_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
#define BIF_CFG_DEV2_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
#define BIF_CFG_DEV2_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
#define BIF_CFG_DEV2_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
#define BIF_CFG_DEV2_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
#define BIF_CFG_DEV2_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
#define BIF_CFG_DEV2_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
#define BIF_CFG_DEV2_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
#define BIF_CFG_DEV2_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
//BIF_CFG_DEV2_RC_LINK_CNTL
#define BIF_CFG_DEV2_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                        0x2
#define BIF_CFG_DEV2_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
#define BIF_CFG_DEV2_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
#define BIF_CFG_DEV2_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
#define BIF_CFG_DEV2_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
#define BIF_CFG_DEV2_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
#define BIF_CFG_DEV2_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
#define BIF_CFG_DEV2_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
#define BIF_CFG_DEV2_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
#define BIF_CFG_DEV2_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                          0x0004L
#define BIF_CFG_DEV2_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
#define BIF_CFG_DEV2_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
#define BIF_CFG_DEV2_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
#define BIF_CFG_DEV2_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
#define BIF_CFG_DEV2_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
#define BIF_CFG_DEV2_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
#define BIF_CFG_DEV2_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
#define BIF_CFG_DEV2_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
//BIF_CFG_DEV2_RC_LINK_STATUS
#define BIF_CFG_DEV2_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
#define BIF_CFG_DEV2_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
#define BIF_CFG_DEV2_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
#define BIF_CFG_DEV2_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
#define BIF_CFG_DEV2_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
#define BIF_CFG_DEV2_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
#define BIF_CFG_DEV2_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
//BIF_CFG_DEV2_RC_SLOT_CAP
#define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                               0x1
#define BIF_CFG_DEV2_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                   0x2
#define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                               0x3
#define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                0x4
#define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                     0x5
#define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                      0x6
#define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                 0x7
#define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                        0x11
#define BIF_CFG_DEV2_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                       0x12
#define BIF_CFG_DEV2_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                    0x13
#define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                    0x00000001L
#define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                 0x00000002L
#define BIF_CFG_DEV2_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                     0x00000004L
#define BIF_CFG_DEV2_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                  0x00000010L
#define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                        0x00000040L
#define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                   0x00007F80L
#define BIF_CFG_DEV2_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                   0x00018000L
#define BIF_CFG_DEV2_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                          0x00020000L
#define BIF_CFG_DEV2_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                         0x00040000L
#define BIF_CFG_DEV2_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                      0xFFF80000L
//BIF_CFG_DEV2_RC_SLOT_CNTL
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                               0x1
#define BIF_CFG_DEV2_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                               0x2
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                          0x3
#define BIF_CFG_DEV2_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                 0x6
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                  0x8
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                 0xa
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                          0xb
#define BIF_CFG_DEV2_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                 0xc
#define BIF_CFG_DEV2_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                         0xd
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                0x0001L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                 0x0002L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                            0x0008L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                   0x00C0L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                    0x0300L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                   0x0400L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                            0x0800L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                   0x1000L
#define BIF_CFG_DEV2_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                           0x2000L
//BIF_CFG_DEV2_RC_SLOT_STATUS
#define BIF_CFG_DEV2_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                0x1
#define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                0x2
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                           0x3
#define BIF_CFG_DEV2_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                 0x4
#define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                  0x5
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                             0x6
#define BIF_CFG_DEV2_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                  0x8
#define BIF_CFG_DEV2_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                 0x0001L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                  0x0002L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                  0x0004L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                             0x0008L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                   0x0010L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                    0x0020L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                               0x0040L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                        0x0080L
#define BIF_CFG_DEV2_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                    0x0100L
//BIF_CFG_DEV2_RC_ROOT_CNTL
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                             0x1
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                0x2
#define BIF_CFG_DEV2_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV2_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                          0x4
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                               0x0002L
#define BIF_CFG_DEV2_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV2_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV2_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                            0x0010L
//BIF_CFG_DEV2_RC_ROOT_CAP
#define BIF_CFG_DEV2_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                0x0001L
//BIF_CFG_DEV2_RC_ROOT_STATUS
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_STATUS__SHIFT                                                        0x10
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_PENDING__SHIFT                                                       0x11
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_STATUS_MASK                                                          0x00010000L
#define BIF_CFG_DEV2_RC_ROOT_STATUS__PME_PENDING_MASK                                                         0x00020000L
//BIF_CFG_DEV2_RC_DEVICE_CAP2
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
#define BIF_CFG_DEV2_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_RC_DEVICE_CNTL2
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
#define BIF_CFG_DEV2_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
//BIF_CFG_DEV2_RC_DEVICE_STATUS2
#define BIF_CFG_DEV2_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_RC_LINK_CAP2
#define BIF_CFG_DEV2_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
#define BIF_CFG_DEV2_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                            0x9
#define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
#define BIF_CFG_DEV2_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
#define BIF_CFG_DEV2_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
#define BIF_CFG_DEV2_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
#define BIF_CFG_DEV2_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
#define BIF_CFG_DEV2_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
#define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                              0x0000FE00L
#define BIF_CFG_DEV2_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
#define BIF_CFG_DEV2_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
#define BIF_CFG_DEV2_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
#define BIF_CFG_DEV2_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
//BIF_CFG_DEV2_RC_LINK_CNTL2
#define BIF_CFG_DEV2_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
#define BIF_CFG_DEV2_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
#define BIF_CFG_DEV2_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
#define BIF_CFG_DEV2_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
#define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
#define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
#define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
#define BIF_CFG_DEV2_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
#define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
#define BIF_CFG_DEV2_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
//BIF_CFG_DEV2_RC_LINK_STATUS2
#define BIF_CFG_DEV2_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
#define BIF_CFG_DEV2_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
#define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
#define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
#define BIF_CFG_DEV2_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
#define BIF_CFG_DEV2_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
#define BIF_CFG_DEV2_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
#define BIF_CFG_DEV2_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
#define BIF_CFG_DEV2_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
//BIF_CFG_DEV2_RC_SLOT_CAP2
#define BIF_CFG_DEV2_RC_SLOT_CAP2__RESERVED__SHIFT                                                            0x0
#define BIF_CFG_DEV2_RC_SLOT_CAP2__RESERVED_MASK                                                              0xFFFFFFFFL
//BIF_CFG_DEV2_RC_SLOT_CNTL2
#define BIF_CFG_DEV2_RC_SLOT_CNTL2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_SLOT_CNTL2__RESERVED_MASK                                                             0xFFFFL
//BIF_CFG_DEV2_RC_SLOT_STATUS2
#define BIF_CFG_DEV2_RC_SLOT_STATUS2__RESERVED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_SLOT_STATUS2__RESERVED_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_RC_MSI_CAP_LIST
#define BIF_CFG_DEV2_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
#define BIF_CFG_DEV2_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
//BIF_CFG_DEV2_RC_MSI_MSG_CNTL
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
#define BIF_CFG_DEV2_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
//BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
#define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
//BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_MSI_MSG_DATA
#define BIF_CFG_DEV2_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_RC_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
//BIF_CFG_DEV2_RC_SSID_CAP_LIST
#define BIF_CFG_DEV2_RC_SSID_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV2_RC_SSID_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV2_RC_SSID_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV2_RC_SSID_CAP
#define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                         0x10
#define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC_SSID_CAP__SUBSYSTEM_ID_MASK                                                           0xFFFF0000L
//BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_RC_MSI_MAP_CAP
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__EN__SHIFT                                                                0x0
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__FIXD__SHIFT                                                              0x1
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                          0xb
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__EN_MASK                                                                  0x0001L
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__FIXD_MASK                                                                0x0002L
#define BIF_CFG_DEV2_RC_MSI_MAP_CAP__CAP_TYPE_MASK                                                            0xF800L
//BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
//BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
//BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
//BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
//BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV2_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
//BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
#define BIF_CFG_DEV2_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
//BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
//BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
//BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
#define BIF_CFG_DEV2_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
//BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
//BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
#define BIF_CFG_DEV2_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
//BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                            0x5
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                             0x6
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                              0x00000020L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                               0x00000040L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
#define BIF_CFG_DEV2_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
//BIF_CFG_DEV2_RC_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                         0x1
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                            0x2
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                               0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                           0x00000002L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                              0x00000004L
//BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                       0x1
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                  0x2
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                             0x3
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                0x4
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                  0x5
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                     0x6
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                      0x1b
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                              0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                         0x00000002L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                    0x00000004L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                               0x00000008L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                  0x00000010L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                    0x00000020L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                       0x00000040L
#define BIF_CFG_DEV2_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                        0xF8000000L
//BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                     0x10
#define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                       0x9
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
#define BIF_CFG_DEV2_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                         0x0000FE00L
//BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
//BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV2_RC_PCIE_ACS_CAP
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
//BIF_CFG_DEV2_RC_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
#define BIF_CFG_DEV2_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
//BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
//BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV2_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
//BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
//BIF_CFG_DEV2_RC_LINK_CAP_16GT
#define BIF_CFG_DEV2_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC_LINK_CNTL_16GT
#define BIF_CFG_DEV2_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_RC_LINK_STATUS_16GT
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
#define BIF_CFG_DEV2_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
//BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV2_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV2_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
#define BIF_CFG_DEV2_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
//BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
#define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
#define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
#define BIF_CFG_DEV2_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
//BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_RC_MARGINING_PORT_CAP
#define BIF_CFG_DEV2_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
#define BIF_CFG_DEV2_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
//BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS
#define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
#define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
#define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
#define BIF_CFG_DEV2_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
//BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
//BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
#define BIF_CFG_DEV2_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
//BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV2_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV2_RC_RTR_DATA1
#define BIF_CFG_DEV2_RC_RTR_DATA1__RESET_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC_RTR_DATA1__DLUP_TIME__SHIFT                                                           0xc
#define BIF_CFG_DEV2_RC_RTR_DATA1__VALID__SHIFT                                                               0x1f
#define BIF_CFG_DEV2_RC_RTR_DATA1__RESET_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_RC_RTR_DATA1__DLUP_TIME_MASK                                                             0x00FFF000L
#define BIF_CFG_DEV2_RC_RTR_DATA1__VALID_MASK                                                                 0x80000000L
//BIF_CFG_DEV2_RC_RTR_DATA2
#define BIF_CFG_DEV2_RC_RTR_DATA2__FLR_TIME__SHIFT                                                            0x0
#define BIF_CFG_DEV2_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                        0xc
#define BIF_CFG_DEV2_RC_RTR_DATA2__FLR_TIME_MASK                                                              0x00000FFFL
#define BIF_CFG_DEV2_RC_RTR_DATA2__D3HOTD0_TIME_MASK                                                          0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF0_COMMAND
#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF0_STATUS
#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_LATENCY
#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_HEADER
#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF0_BIST
#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_MIN_GRANT
#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF0_PMI_CAP
#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                       0x0000FE00L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                      0x0040L
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                       0x0080L
//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK                                                             0x001FL
#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                  0x0002L
//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                            0xf
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                            0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                  0x0100L
#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                              0x8000L
//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                      0x003FL
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                   0x3F00L
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                      0xf
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                     0x003FL
#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                        0x8000L
//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                    0x0000003FL
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF0_RTR_DATA1
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF0_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF0_RTR_DATA2
#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L
//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                                               0x0
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                                              0x10
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                                             0x14
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                                                 0x0000FFFFL
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                                                0x000F0000L
#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                                               0xFFF00000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
//BIF_CFG_DEV0_EPF1_VENDOR_ID
#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF1_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF1_COMMAND
#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF1_STATUS
#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF1_REVISION_ID
#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF1_SUB_CLASS
#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF1_BASE_CLASS
#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_CACHE_LINE
#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF1_LATENCY
#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_HEADER
#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF1_BIST
#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_CAP_PTR
#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF1_MIN_GRANT
#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF1_MAX_LATENCY
#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF1_PMI_CAP
#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF1_PCIE_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF1_LINK_CAP
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF1_LINK_CNTL
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF1_LINK_STATUS
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF1_LINK_CAP2
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF1_MSI_MASK
#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_MSI_PENDING
#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_MSIX_PBA
#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                       0x0000FE00L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                      0x0040L
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                       0x0080L
//BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK                                                             0x001FL
#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                  0x0002L
//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                            0xf
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                            0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                  0x0100L
#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                              0x8000L
//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                      0x003FL
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                   0x3F00L
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                      0xf
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                     0x003FL
#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                        0x8000L
//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                    0x0000003FL
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
//BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_EPF1_LINK_CAP_16GT
#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
//BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
//BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF1_RTR_DATA1
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF1_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF1_RTR_DATA2
#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
//BIF_CFG_DEV0_EPF2_VENDOR_ID
#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF2_DEVICE_ID
#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF2_COMMAND
#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF2_STATUS
#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF2_REVISION_ID
#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF2_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF2_SUB_CLASS
#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF2_BASE_CLASS
#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF2_CACHE_LINE
#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF2_LATENCY
#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF2_HEADER
#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF2_BIST
#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF2_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_ADAPTER_ID
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_CAP_PTR
#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF2_MIN_GRANT
#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF2_MAX_LATENCY
#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF2_PMI_CAP
#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF2_SBRN
#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV0_EPF2_FLADJ
#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV0_EPF2_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF2_PCIE_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF2_DEVICE_CAP
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF2_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF2_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF2_LINK_CAP
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF2_LINK_CNTL
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF2_LINK_STATUS
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF2_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF2_LINK_CAP2
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF2_LINK_CNTL2
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF2_LINK_STATUS2
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF2_MSI_MASK
#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF2_MSI_MASK_64
#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_MSI_PENDING
#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF2_MSIX_TABLE
#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF2_MSIX_PBA
#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF2_SATA_CAP_0
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF2_SATA_CAP_1
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF2_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF2_RTR_DATA1
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF2_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF2_RTR_DATA2
#define BIF_CFG_DEV0_EPF2_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF2_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF2_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF2_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
//BIF_CFG_DEV2_EPF0_VENDOR_ID
#define BIF_CFG_DEV2_EPF0_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF0_DEVICE_ID
#define BIF_CFG_DEV2_EPF0_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF0_COMMAND
#define BIF_CFG_DEV2_EPF0_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_EPF0_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV2_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV2_EPF0_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV2_EPF0_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV2_EPF0_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV2_EPF0_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV2_EPF0_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV2_EPF0_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_EPF0_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV2_EPF0_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV2_EPF0_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV2_EPF0_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV2_EPF0_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV2_EPF0_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV2_EPF0_STATUS
#define BIF_CFG_DEV2_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF0_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV2_EPF0_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV2_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF0_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF0_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV2_EPF0_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF0_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV2_EPF0_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV2_EPF0_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF0_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV2_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV2_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV2_EPF0_REVISION_ID
#define BIF_CFG_DEV2_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV2_EPF0_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV2_EPF0_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV2_EPF0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF0_SUB_CLASS
#define BIF_CFG_DEV2_EPF0_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF0_BASE_CLASS
#define BIF_CFG_DEV2_EPF0_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF0_CACHE_LINE
#define BIF_CFG_DEV2_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV2_EPF0_LATENCY
#define BIF_CFG_DEV2_EPF0_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF0_HEADER
#define BIF_CFG_DEV2_EPF0_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF0_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV2_EPF0_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV2_EPF0_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV2_EPF0_BIST
#define BIF_CFG_DEV2_EPF0_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV2_EPF0_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV2_EPF0_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV2_EPF0_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV2_EPF0_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV2_EPF0_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV2_EPF0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_CAP_PTR
#define BIF_CFG_DEV2_EPF0_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF0_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV2_EPF0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV2_EPF0_MIN_GRANT
#define BIF_CFG_DEV2_EPF0_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF0_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF0_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV2_EPF0_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV2_EPF0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF0_PMI_CAP
#define BIF_CFG_DEV2_EPF0_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF0_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV2_EPF0_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV2_EPF0_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV2_EPF0_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV2_EPF0_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV2_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV2_EPF0_SBRN
#define BIF_CFG_DEV2_EPF0_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV2_EPF0_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV2_EPF0_FLADJ
#define BIF_CFG_DEV2_EPF0_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF0_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV2_EPF0_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV2_EPF0_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV2_EPF0_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV2_EPF0_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF0_PCIE_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV2_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV2_EPF0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV2_EPF0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV2_EPF0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV2_EPF0_LINK_CAP
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF0_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV2_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV2_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF0_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV2_EPF0_LINK_CNTL
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV2_EPF0_LINK_STATUS
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV2_EPF0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV2_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV2_EPF0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF0_LINK_CAP2
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV2_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_EPF0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV2_EPF0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV2_EPF0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV2_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF0_MSI_MASK
#define BIF_CFG_DEV2_EPF0_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF0_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV2_EPF0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_MSI_PENDING
#define BIF_CFG_DEV2_EPF0_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV2_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV2_EPF0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV2_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV2_EPF0_MSIX_PBA
#define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV2_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV2_EPF0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV2_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV2_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV2_EPF0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV2_EPF0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
//BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
//BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
//BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV2_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV2_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV2_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
#define BIF_CFG_DEV2_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                       0x0000FE00L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
//BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV2_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV2_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
#define BIF_CFG_DEV2_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
//BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
//BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
#define BIF_CFG_DEV2_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
//BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV2_EPF0_LINK_CAP_16GT
#define BIF_CFG_DEV2_EPF0_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
#define BIF_CFG_DEV2_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
//BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV2_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV2_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV2_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
//BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
//BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF0_RTR_DATA1
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV2_EPF0_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV2_EPF0_RTR_DATA2
#define BIF_CFG_DEV2_EPF0_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV2_EPF0_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
//BIF_CFG_DEV0_EPF4_VENDOR_ID
#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF4_DEVICE_ID
#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF4_COMMAND
#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF4_STATUS
#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF4_REVISION_ID
#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF4_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF4_SUB_CLASS
#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF4_BASE_CLASS
#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF4_CACHE_LINE
#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF4_LATENCY
#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF4_HEADER
#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF4_BIST
#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF4_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_ADAPTER_ID
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_CAP_PTR
#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF4_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF4_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF4_MIN_GRANT
#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF4_MAX_LATENCY
#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF4_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF4_PMI_CAP
#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF4_SBRN
#define BIF_CFG_DEV0_EPF4_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV0_EPF4_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV0_EPF4_FLADJ
#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF4_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV0_EPF4_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV0_EPF4_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF4_PCIE_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF4_DEVICE_CAP
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF4_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF4_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF4_LINK_CAP
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF4_LINK_CNTL
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF4_LINK_STATUS
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF4_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF4_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF4_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF4_LINK_CAP2
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF4_LINK_CNTL2
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF4_LINK_STATUS2
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF4_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF4_MSI_MASK
#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF4_MSI_MASK_64
#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_MSI_PENDING
#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF4_MSIX_TABLE
#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF4_MSIX_PBA
#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF4_SATA_CAP_0
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV0_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF4_SATA_CAP_1
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV0_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV0_EPF4_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF4_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF4_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF4_RTR_DATA1
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF4_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF4_RTR_DATA2
#define BIF_CFG_DEV0_EPF4_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF4_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF4_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF4_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf3_bifcfgdecp
//BIF_CFG_DEV2_EPF3_VENDOR_ID
#define BIF_CFG_DEV2_EPF3_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF3_DEVICE_ID
#define BIF_CFG_DEV2_EPF3_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF3_COMMAND
#define BIF_CFG_DEV2_EPF3_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_EPF3_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV2_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV2_EPF3_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV2_EPF3_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV2_EPF3_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV2_EPF3_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV2_EPF3_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV2_EPF3_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_EPF3_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV2_EPF3_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV2_EPF3_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV2_EPF3_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV2_EPF3_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV2_EPF3_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV2_EPF3_STATUS
#define BIF_CFG_DEV2_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF3_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV2_EPF3_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV2_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF3_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF3_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV2_EPF3_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF3_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV2_EPF3_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV2_EPF3_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF3_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV2_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV2_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV2_EPF3_REVISION_ID
#define BIF_CFG_DEV2_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV2_EPF3_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV2_EPF3_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV2_EPF3_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF3_SUB_CLASS
#define BIF_CFG_DEV2_EPF3_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF3_BASE_CLASS
#define BIF_CFG_DEV2_EPF3_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF3_CACHE_LINE
#define BIF_CFG_DEV2_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV2_EPF3_LATENCY
#define BIF_CFG_DEV2_EPF3_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF3_HEADER
#define BIF_CFG_DEV2_EPF3_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF3_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV2_EPF3_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV2_EPF3_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV2_EPF3_BIST
#define BIF_CFG_DEV2_EPF3_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV2_EPF3_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV2_EPF3_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV2_EPF3_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV2_EPF3_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV2_EPF3_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV2_EPF3_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_ADAPTER_ID
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_CAP_PTR
#define BIF_CFG_DEV2_EPF3_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF3_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV2_EPF3_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF3_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV2_EPF3_MIN_GRANT
#define BIF_CFG_DEV2_EPF3_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF3_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF3_MAX_LATENCY
#define BIF_CFG_DEV2_EPF3_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV2_EPF3_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV2_EPF3_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF3_PMI_CAP
#define BIF_CFG_DEV2_EPF3_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF3_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV2_EPF3_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV2_EPF3_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV2_EPF3_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV2_EPF3_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV2_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV2_EPF3_SBRN
#define BIF_CFG_DEV2_EPF3_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV2_EPF3_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV2_EPF3_FLADJ
#define BIF_CFG_DEV2_EPF3_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF3_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV2_EPF3_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV2_EPF3_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV2_EPF3_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV2_EPF3_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF3_PCIE_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV2_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV2_EPF3_DEVICE_CAP
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV2_EPF3_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV2_EPF3_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV2_EPF3_LINK_CAP
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF3_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV2_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV2_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF3_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV2_EPF3_LINK_CNTL
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV2_EPF3_LINK_STATUS
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV2_EPF3_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF3_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV2_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV2_EPF3_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF3_LINK_CAP2
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV2_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_EPF3_LINK_CNTL2
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV2_EPF3_LINK_STATUS2
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV2_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV2_EPF3_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV2_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF3_MSI_MASK
#define BIF_CFG_DEV2_EPF3_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF3_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV2_EPF3_MSI_MASK_64
#define BIF_CFG_DEV2_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_MSI_PENDING
#define BIF_CFG_DEV2_EPF3_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV2_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV2_EPF3_MSIX_TABLE
#define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV2_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV2_EPF3_MSIX_PBA
#define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV2_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV2_EPF3_SATA_CAP_0
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV2_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF3_SATA_CAP_1
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV2_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV2_EPF3_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV2_EPF3_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF3_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV2_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV2_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV2_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV2_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF3_RTR_DATA1
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV2_EPF3_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV2_EPF3_RTR_DATA2
#define BIF_CFG_DEV2_EPF3_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF3_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV2_EPF3_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_EPF3_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf4_bifcfgdecp
//BIF_CFG_DEV2_EPF4_VENDOR_ID
#define BIF_CFG_DEV2_EPF4_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF4_DEVICE_ID
#define BIF_CFG_DEV2_EPF4_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF4_COMMAND
#define BIF_CFG_DEV2_EPF4_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_EPF4_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV2_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV2_EPF4_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV2_EPF4_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV2_EPF4_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV2_EPF4_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV2_EPF4_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV2_EPF4_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_EPF4_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV2_EPF4_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV2_EPF4_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV2_EPF4_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV2_EPF4_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV2_EPF4_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV2_EPF4_STATUS
#define BIF_CFG_DEV2_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF4_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV2_EPF4_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV2_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF4_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF4_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV2_EPF4_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF4_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV2_EPF4_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV2_EPF4_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF4_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV2_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV2_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV2_EPF4_REVISION_ID
#define BIF_CFG_DEV2_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV2_EPF4_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV2_EPF4_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV2_EPF4_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF4_SUB_CLASS
#define BIF_CFG_DEV2_EPF4_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF4_BASE_CLASS
#define BIF_CFG_DEV2_EPF4_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF4_CACHE_LINE
#define BIF_CFG_DEV2_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV2_EPF4_LATENCY
#define BIF_CFG_DEV2_EPF4_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF4_HEADER
#define BIF_CFG_DEV2_EPF4_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF4_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV2_EPF4_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV2_EPF4_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV2_EPF4_BIST
#define BIF_CFG_DEV2_EPF4_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV2_EPF4_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV2_EPF4_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV2_EPF4_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV2_EPF4_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV2_EPF4_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV2_EPF4_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_ADAPTER_ID
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_CAP_PTR
#define BIF_CFG_DEV2_EPF4_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF4_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV2_EPF4_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF4_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV2_EPF4_MIN_GRANT
#define BIF_CFG_DEV2_EPF4_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF4_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF4_MAX_LATENCY
#define BIF_CFG_DEV2_EPF4_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV2_EPF4_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV2_EPF4_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF4_PMI_CAP
#define BIF_CFG_DEV2_EPF4_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF4_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV2_EPF4_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV2_EPF4_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV2_EPF4_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV2_EPF4_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV2_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV2_EPF4_SBRN
#define BIF_CFG_DEV2_EPF4_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV2_EPF4_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV2_EPF4_FLADJ
#define BIF_CFG_DEV2_EPF4_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF4_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV2_EPF4_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV2_EPF4_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV2_EPF4_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV2_EPF4_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF4_PCIE_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV2_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV2_EPF4_DEVICE_CAP
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV2_EPF4_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV2_EPF4_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV2_EPF4_LINK_CAP
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF4_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV2_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV2_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF4_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV2_EPF4_LINK_CNTL
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV2_EPF4_LINK_STATUS
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV2_EPF4_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF4_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV2_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV2_EPF4_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF4_LINK_CAP2
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV2_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_EPF4_LINK_CNTL2
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV2_EPF4_LINK_STATUS2
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV2_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV2_EPF4_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV2_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF4_MSI_MASK
#define BIF_CFG_DEV2_EPF4_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF4_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV2_EPF4_MSI_MASK_64
#define BIF_CFG_DEV2_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_MSI_PENDING
#define BIF_CFG_DEV2_EPF4_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV2_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV2_EPF4_MSIX_TABLE
#define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV2_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV2_EPF4_MSIX_PBA
#define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV2_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV2_EPF4_SATA_CAP_0
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV2_EPF4_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF4_SATA_CAP_1
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV2_EPF4_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV2_EPF4_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV2_EPF4_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF4_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV2_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV2_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV2_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV2_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF4_RTR_DATA1
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV2_EPF4_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV2_EPF4_RTR_DATA2
#define BIF_CFG_DEV2_EPF4_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF4_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV2_EPF4_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_EPF4_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf5_bifcfgdecp
//BIF_CFG_DEV2_EPF5_VENDOR_ID
#define BIF_CFG_DEV2_EPF5_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF5_DEVICE_ID
#define BIF_CFG_DEV2_EPF5_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF5_COMMAND
#define BIF_CFG_DEV2_EPF5_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_EPF5_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV2_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV2_EPF5_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV2_EPF5_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV2_EPF5_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV2_EPF5_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV2_EPF5_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV2_EPF5_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_EPF5_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV2_EPF5_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV2_EPF5_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV2_EPF5_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV2_EPF5_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV2_EPF5_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV2_EPF5_STATUS
#define BIF_CFG_DEV2_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF5_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV2_EPF5_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV2_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF5_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF5_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV2_EPF5_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF5_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV2_EPF5_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV2_EPF5_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF5_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV2_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV2_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV2_EPF5_REVISION_ID
#define BIF_CFG_DEV2_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV2_EPF5_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV2_EPF5_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV2_EPF5_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF5_SUB_CLASS
#define BIF_CFG_DEV2_EPF5_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF5_BASE_CLASS
#define BIF_CFG_DEV2_EPF5_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF5_CACHE_LINE
#define BIF_CFG_DEV2_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV2_EPF5_LATENCY
#define BIF_CFG_DEV2_EPF5_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF5_HEADER
#define BIF_CFG_DEV2_EPF5_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF5_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV2_EPF5_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV2_EPF5_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV2_EPF5_BIST
#define BIF_CFG_DEV2_EPF5_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV2_EPF5_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV2_EPF5_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV2_EPF5_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV2_EPF5_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV2_EPF5_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV2_EPF5_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_ADAPTER_ID
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_CAP_PTR
#define BIF_CFG_DEV2_EPF5_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF5_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV2_EPF5_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF5_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV2_EPF5_MIN_GRANT
#define BIF_CFG_DEV2_EPF5_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF5_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF5_MAX_LATENCY
#define BIF_CFG_DEV2_EPF5_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV2_EPF5_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV2_EPF5_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF5_PMI_CAP
#define BIF_CFG_DEV2_EPF5_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF5_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV2_EPF5_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV2_EPF5_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV2_EPF5_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV2_EPF5_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV2_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF5_PCIE_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV2_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV2_EPF5_DEVICE_CAP
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV2_EPF5_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV2_EPF5_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV2_EPF5_LINK_CAP
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF5_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV2_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV2_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF5_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV2_EPF5_LINK_CNTL
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV2_EPF5_LINK_STATUS
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV2_EPF5_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF5_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV2_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV2_EPF5_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF5_LINK_CAP2
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV2_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_EPF5_LINK_CNTL2
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV2_EPF5_LINK_STATUS2
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV2_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV2_EPF5_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV2_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF5_MSI_MASK
#define BIF_CFG_DEV2_EPF5_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF5_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV2_EPF5_MSI_MASK_64
#define BIF_CFG_DEV2_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_MSI_PENDING
#define BIF_CFG_DEV2_EPF5_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV2_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV2_EPF5_MSIX_TABLE
#define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV2_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV2_EPF5_MSIX_PBA
#define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV2_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV2_EPF5_SATA_CAP_0
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV2_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF5_SATA_CAP_1
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV2_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV2_EPF5_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV2_EPF5_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF5_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV2_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV2_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV2_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV2_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF5_RTR_DATA1
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV2_EPF5_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV2_EPF5_RTR_DATA2
#define BIF_CFG_DEV2_EPF5_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF5_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV2_EPF5_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_EPF5_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf6_bifcfgdecp
//BIF_CFG_DEV2_EPF6_VENDOR_ID
#define BIF_CFG_DEV2_EPF6_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF6_DEVICE_ID
#define BIF_CFG_DEV2_EPF6_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV2_EPF6_COMMAND
#define BIF_CFG_DEV2_EPF6_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV2_EPF6_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV2_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV2_EPF6_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV2_EPF6_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV2_EPF6_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV2_EPF6_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV2_EPF6_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV2_EPF6_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV2_EPF6_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV2_EPF6_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV2_EPF6_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV2_EPF6_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV2_EPF6_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV2_EPF6_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV2_EPF6_STATUS
#define BIF_CFG_DEV2_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF6_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV2_EPF6_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV2_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF6_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF6_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV2_EPF6_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF6_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV2_EPF6_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV2_EPF6_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF6_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV2_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV2_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV2_EPF6_REVISION_ID
#define BIF_CFG_DEV2_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV2_EPF6_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV2_EPF6_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV2_EPF6_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF6_SUB_CLASS
#define BIF_CFG_DEV2_EPF6_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF6_BASE_CLASS
#define BIF_CFG_DEV2_EPF6_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF6_CACHE_LINE
#define BIF_CFG_DEV2_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV2_EPF6_LATENCY
#define BIF_CFG_DEV2_EPF6_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF6_HEADER
#define BIF_CFG_DEV2_EPF6_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF6_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV2_EPF6_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV2_EPF6_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV2_EPF6_BIST
#define BIF_CFG_DEV2_EPF6_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV2_EPF6_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV2_EPF6_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV2_EPF6_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV2_EPF6_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV2_EPF6_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV2_EPF6_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_ADAPTER_ID
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_CAP_PTR
#define BIF_CFG_DEV2_EPF6_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF6_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV2_EPF6_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF6_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV2_EPF6_MIN_GRANT
#define BIF_CFG_DEV2_EPF6_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF6_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF6_MAX_LATENCY
#define BIF_CFG_DEV2_EPF6_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV2_EPF6_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV2_EPF6_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF6_PMI_CAP
#define BIF_CFG_DEV2_EPF6_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV2_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF6_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV2_EPF6_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV2_EPF6_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV2_EPF6_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV2_EPF6_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV2_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF6_PCIE_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV2_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV2_EPF6_DEVICE_CAP
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV2_EPF6_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV2_EPF6_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV2_EPF6_LINK_CAP
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV2_EPF6_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV2_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV2_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV2_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF6_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV2_EPF6_LINK_CNTL
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV2_EPF6_LINK_STATUS
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV2_EPF6_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF6_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV2_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV2_EPF6_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF6_LINK_CAP2
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV2_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV2_EPF6_LINK_CNTL2
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV2_EPF6_LINK_STATUS2
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV2_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV2_EPF6_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV2_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF6_MSI_MASK
#define BIF_CFG_DEV2_EPF6_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF6_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV2_EPF6_MSI_MASK_64
#define BIF_CFG_DEV2_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_MSI_PENDING
#define BIF_CFG_DEV2_EPF6_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV2_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV2_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV2_EPF6_MSIX_TABLE
#define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV2_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV2_EPF6_MSIX_PBA
#define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV2_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV2_EPF6_SATA_CAP_0
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV2_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF6_SATA_CAP_1
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV2_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV2_EPF6_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV2_EPF6_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF6_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV2_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV2_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV2_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV2_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV2_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV2_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV2_EPF6_RTR_DATA1
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV2_EPF6_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV2_EPF6_RTR_DATA2
#define BIF_CFG_DEV2_EPF6_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF6_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV2_EPF6_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV2_EPF6_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
//BIF_CFG_DEV0_EPF5_VENDOR_ID
#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF5_DEVICE_ID
#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF5_COMMAND
#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF5_STATUS
#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF5_REVISION_ID
#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF5_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF5_SUB_CLASS
#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF5_BASE_CLASS
#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF5_CACHE_LINE
#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF5_LATENCY
#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF5_HEADER
#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF5_BIST
#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF5_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_ADAPTER_ID
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_CAP_PTR
#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF5_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF5_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF5_MIN_GRANT
#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF5_MAX_LATENCY
#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF5_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF5_PMI_CAP
#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF5_SBRN
#define BIF_CFG_DEV0_EPF5_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV0_EPF5_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV0_EPF5_FLADJ
#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF5_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV0_EPF5_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV0_EPF5_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF5_PCIE_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF5_DEVICE_CAP
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF5_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF5_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF5_LINK_CAP
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF5_LINK_CNTL
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF5_LINK_STATUS
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF5_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF5_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF5_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF5_LINK_CAP2
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF5_LINK_CNTL2
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF5_LINK_STATUS2
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF5_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF5_MSI_MASK
#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF5_MSI_MASK_64
#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_MSI_PENDING
#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF5_MSIX_TABLE
#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF5_MSIX_PBA
#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF5_SATA_CAP_0
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV0_EPF5_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF5_SATA_CAP_1
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV0_EPF5_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV0_EPF5_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF5_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF5_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF5_RTR_DATA1
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF5_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF5_RTR_DATA2
#define BIF_CFG_DEV0_EPF5_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF5_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF5_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF5_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
//BIF_CFG_DEV1_EPF1_VENDOR_ID
#define BIF_CFG_DEV1_EPF1_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_EPF1_DEVICE_ID
#define BIF_CFG_DEV1_EPF1_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_EPF1_COMMAND
#define BIF_CFG_DEV1_EPF1_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV1_EPF1_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV1_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV1_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV1_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV1_EPF1_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV1_EPF1_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV1_EPF1_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV1_EPF1_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV1_EPF1_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV1_EPF1_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV1_EPF1_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV1_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV1_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV1_EPF1_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV1_EPF1_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV1_EPF1_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV1_EPF1_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV1_EPF1_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV1_EPF1_STATUS
#define BIF_CFG_DEV1_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV1_EPF1_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV1_EPF1_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV1_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF1_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV1_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV1_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV1_EPF1_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV1_EPF1_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV1_EPF1_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV1_EPF1_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV1_EPF1_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV1_EPF1_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV1_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV1_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV1_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV1_EPF1_REVISION_ID
#define BIF_CFG_DEV1_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV1_EPF1_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV1_EPF1_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV1_EPF1_PROG_INTERFACE
#define BIF_CFG_DEV1_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF1_SUB_CLASS
#define BIF_CFG_DEV1_EPF1_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF1_BASE_CLASS
#define BIF_CFG_DEV1_EPF1_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF1_CACHE_LINE
#define BIF_CFG_DEV1_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV1_EPF1_LATENCY
#define BIF_CFG_DEV1_EPF1_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF1_HEADER
#define BIF_CFG_DEV1_EPF1_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF1_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV1_EPF1_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV1_EPF1_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV1_EPF1_BIST
#define BIF_CFG_DEV1_EPF1_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV1_EPF1_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV1_EPF1_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV1_EPF1_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV1_EPF1_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV1_EPF1_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV1_EPF1_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_BASE_ADDR_6
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_ADAPTER_ID
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR
#define BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_CAP_PTR
#define BIF_CFG_DEV1_EPF1_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV1_EPF1_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV1_EPF1_INTERRUPT_LINE
#define BIF_CFG_DEV1_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF1_INTERRUPT_PIN
#define BIF_CFG_DEV1_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV1_EPF1_MIN_GRANT
#define BIF_CFG_DEV1_EPF1_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF1_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV1_EPF1_MAX_LATENCY
#define BIF_CFG_DEV1_EPF1_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV1_EPF1_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV1_EPF1_ADAPTER_ID_W
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PMI_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_EPF1_PMI_CAP
#define BIF_CFG_DEV1_EPF1_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV1_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV1_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV1_EPF1_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV1_EPF1_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV1_EPF1_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV1_EPF1_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV1_EPF1_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV1_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV1_EPF1_SBRN
#define BIF_CFG_DEV1_EPF1_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV1_EPF1_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV1_EPF1_FLADJ
#define BIF_CFG_DEV1_EPF1_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV1_EPF1_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV1_EPF1_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV1_EPF1_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV1_EPF1_DBESL_DBESLD
#define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV1_EPF1_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV1_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV1_EPF1_PCIE_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV1_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV1_EPF1_DEVICE_CAP
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV1_EPF1_DEVICE_CNTL
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV1_EPF1_DEVICE_STATUS
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV1_EPF1_LINK_CAP
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV1_EPF1_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV1_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV1_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV1_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV1_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV1_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV1_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV1_EPF1_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV1_EPF1_LINK_CNTL
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV1_EPF1_LINK_STATUS
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV1_EPF1_DEVICE_CAP2
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV1_EPF1_DEVICE_CNTL2
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV1_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV1_EPF1_DEVICE_STATUS2
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV1_EPF1_LINK_CAP2
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV1_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV1_EPF1_LINK_CNTL2
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV1_EPF1_LINK_STATUS2
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV1_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV1_EPF1_MSI_CAP_LIST
#define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV1_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_MSI_MSG_DATA
#define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV1_EPF1_MSI_MASK
#define BIF_CFG_DEV1_EPF1_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF1_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV1_EPF1_MSI_MASK_64
#define BIF_CFG_DEV1_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_MSI_PENDING
#define BIF_CFG_DEV1_EPF1_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_MSI_PENDING_64
#define BIF_CFG_DEV1_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST
#define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV1_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV1_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV1_EPF1_MSIX_TABLE
#define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV1_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV1_EPF1_MSIX_PBA
#define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV1_EPF1_SATA_CAP_0
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV1_EPF1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV1_EPF1_SATA_CAP_1
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV1_EPF1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV1_EPF1_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV1_EPF1_SATA_IDP_DATA
#define BIF_CFG_DEV1_EPF1_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV1_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV1_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV1_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV1_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV1_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_STATUS
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
#define BIF_CFG_DEV1_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
//BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF1_RTR_DATA1
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV1_EPF1_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV1_EPF1_RTR_DATA2
#define BIF_CFG_DEV1_EPF1_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV1_EPF1_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV1_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
//BIF_CFG_DEV0_EPF6_VENDOR_ID
#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF6_DEVICE_ID
#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF6_COMMAND
#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF6_STATUS
#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF6_REVISION_ID
#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF6_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF6_SUB_CLASS
#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF6_BASE_CLASS
#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF6_CACHE_LINE
#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF6_LATENCY
#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF6_HEADER
#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF6_BIST
#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF6_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_ADAPTER_ID
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_CAP_PTR
#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF6_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF6_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF6_MIN_GRANT
#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF6_MAX_LATENCY
#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF6_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF6_PMI_CAP
#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF6_SBRN
#define BIF_CFG_DEV0_EPF6_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV0_EPF6_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV0_EPF6_FLADJ
#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF6_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV0_EPF6_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV0_EPF6_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF6_PCIE_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF6_DEVICE_CAP
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF6_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF6_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF6_LINK_CAP
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF6_LINK_CNTL
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF6_LINK_STATUS
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF6_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF6_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF6_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF6_LINK_CAP2
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF6_LINK_CNTL2
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF6_LINK_STATUS2
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF6_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF6_MSI_MASK
#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF6_MSI_MASK_64
#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_MSI_PENDING
#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF6_MSIX_TABLE
#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF6_MSIX_PBA
#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF6_SATA_CAP_0
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV0_EPF6_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF6_SATA_CAP_1
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV0_EPF6_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV0_EPF6_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF6_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF6_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF6_RTR_DATA1
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF6_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF6_RTR_DATA2
#define BIF_CFG_DEV0_EPF6_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF6_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF6_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF6_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
//BIF_CFG_DEV0_EPF7_VENDOR_ID
#define BIF_CFG_DEV0_EPF7_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF7_DEVICE_ID
#define BIF_CFG_DEV0_EPF7_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV0_EPF7_COMMAND
#define BIF_CFG_DEV0_EPF7_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV0_EPF7_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_EPF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF7_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV0_EPF7_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF7_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV0_EPF7_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV0_EPF7_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV0_EPF7_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_EPF7_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV0_EPF7_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_EPF7_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV0_EPF7_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV0_EPF7_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV0_EPF7_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV0_EPF7_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV0_EPF7_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV0_EPF7_STATUS
#define BIF_CFG_DEV0_EPF7_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF7_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV0_EPF7_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV0_EPF7_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF7_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF7_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF7_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF7_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV0_EPF7_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV0_EPF7_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF7_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV0_EPF7_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF7_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV0_EPF7_REVISION_ID
#define BIF_CFG_DEV0_EPF7_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF7_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV0_EPF7_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV0_EPF7_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF7_SUB_CLASS
#define BIF_CFG_DEV0_EPF7_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF7_BASE_CLASS
#define BIF_CFG_DEV0_EPF7_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF7_CACHE_LINE
#define BIF_CFG_DEV0_EPF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF7_LATENCY
#define BIF_CFG_DEV0_EPF7_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF7_HEADER
#define BIF_CFG_DEV0_EPF7_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF7_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV0_EPF7_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV0_EPF7_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV0_EPF7_BIST
#define BIF_CFG_DEV0_EPF7_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV0_EPF7_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV0_EPF7_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV0_EPF7_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV0_EPF7_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV0_EPF7_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV0_EPF7_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_ADAPTER_ID
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_CAP_PTR
#define BIF_CFG_DEV0_EPF7_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF7_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV0_EPF7_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF7_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF7_MIN_GRANT
#define BIF_CFG_DEV0_EPF7_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF7_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF7_MAX_LATENCY
#define BIF_CFG_DEV0_EPF7_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV0_EPF7_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV0_EPF7_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF7_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF7_PMI_CAP
#define BIF_CFG_DEV0_EPF7_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV0_EPF7_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF7_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF7_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV0_EPF7_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV0_EPF7_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV0_EPF7_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV0_EPF7_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV0_EPF7_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV0_EPF7_SBRN
#define BIF_CFG_DEV0_EPF7_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV0_EPF7_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV0_EPF7_FLADJ
#define BIF_CFG_DEV0_EPF7_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF7_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV0_EPF7_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV0_EPF7_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV0_EPF7_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV0_EPF7_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF7_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF7_PCIE_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV0_EPF7_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV0_EPF7_DEVICE_CAP
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV0_EPF7_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF7_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV0_EPF7_LINK_CAP
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV0_EPF7_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV0_EPF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV0_EPF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF7_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV0_EPF7_LINK_CNTL
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV0_EPF7_LINK_STATUS
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV0_EPF7_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF7_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV0_EPF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF7_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF7_LINK_CAP2
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV0_EPF7_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV0_EPF7_LINK_CNTL2
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV0_EPF7_LINK_STATUS2
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV0_EPF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV0_EPF7_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_EPF7_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF7_MSI_MASK
#define BIF_CFG_DEV0_EPF7_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF7_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV0_EPF7_MSI_MASK_64
#define BIF_CFG_DEV0_EPF7_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_MSI_PENDING
#define BIF_CFG_DEV0_EPF7_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_EPF7_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV0_EPF7_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV0_EPF7_MSIX_TABLE
#define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV0_EPF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF7_MSIX_PBA
#define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV0_EPF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV0_EPF7_SATA_CAP_0
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV0_EPF7_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF7_SATA_CAP_1
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV0_EPF7_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV0_EPF7_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV0_EPF7_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF7_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV0_EPF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV0_EPF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV0_EPF7_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF7_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF7_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_EPF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_EPF7_RTR_DATA1
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV0_EPF7_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV0_EPF7_RTR_DATA2
#define BIF_CFG_DEV0_EPF7_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF7_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV0_EPF7_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV0_EPF7_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
//BIF_CFG_DEV1_EPF0_VENDOR_ID
#define BIF_CFG_DEV1_EPF0_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_EPF0_DEVICE_ID
#define BIF_CFG_DEV1_EPF0_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
//BIF_CFG_DEV1_EPF0_COMMAND
#define BIF_CFG_DEV1_EPF0_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
#define BIF_CFG_DEV1_EPF0_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV1_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV1_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
#define BIF_CFG_DEV1_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
#define BIF_CFG_DEV1_EPF0_COMMAND__AD_STEPPING__SHIFT                                                         0x7
#define BIF_CFG_DEV1_EPF0_COMMAND__SERR_EN__SHIFT                                                             0x8
#define BIF_CFG_DEV1_EPF0_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
#define BIF_CFG_DEV1_EPF0_COMMAND__INT_DIS__SHIFT                                                             0xa
#define BIF_CFG_DEV1_EPF0_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV1_EPF0_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
#define BIF_CFG_DEV1_EPF0_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV1_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV1_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
#define BIF_CFG_DEV1_EPF0_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
#define BIF_CFG_DEV1_EPF0_COMMAND__AD_STEPPING_MASK                                                           0x0080L
#define BIF_CFG_DEV1_EPF0_COMMAND__SERR_EN_MASK                                                               0x0100L
#define BIF_CFG_DEV1_EPF0_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
#define BIF_CFG_DEV1_EPF0_COMMAND__INT_DIS_MASK                                                               0x0400L
//BIF_CFG_DEV1_EPF0_STATUS
#define BIF_CFG_DEV1_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_STATUS__INT_STATUS__SHIFT                                                           0x3
#define BIF_CFG_DEV1_EPF0_STATUS__CAP_LIST__SHIFT                                                             0x4
#define BIF_CFG_DEV1_EPF0_STATUS__PCI_66_CAP__SHIFT                                                           0x5
#define BIF_CFG_DEV1_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF0_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
#define BIF_CFG_DEV1_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
#define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
#define BIF_CFG_DEV1_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
#define BIF_CFG_DEV1_EPF0_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
#define BIF_CFG_DEV1_EPF0_STATUS__INT_STATUS_MASK                                                             0x0008L
#define BIF_CFG_DEV1_EPF0_STATUS__CAP_LIST_MASK                                                               0x0010L
#define BIF_CFG_DEV1_EPF0_STATUS__PCI_66_CAP_MASK                                                             0x0020L
#define BIF_CFG_DEV1_EPF0_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
#define BIF_CFG_DEV1_EPF0_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
#define BIF_CFG_DEV1_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
#define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
#define BIF_CFG_DEV1_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
#define BIF_CFG_DEV1_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
//BIF_CFG_DEV1_EPF0_REVISION_ID
#define BIF_CFG_DEV1_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
#define BIF_CFG_DEV1_EPF0_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
#define BIF_CFG_DEV1_EPF0_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
//BIF_CFG_DEV1_EPF0_PROG_INTERFACE
#define BIF_CFG_DEV1_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF0_SUB_CLASS
#define BIF_CFG_DEV1_EPF0_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF0_BASE_CLASS
#define BIF_CFG_DEV1_EPF0_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF0_CACHE_LINE
#define BIF_CFG_DEV1_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
//BIF_CFG_DEV1_EPF0_LATENCY
#define BIF_CFG_DEV1_EPF0_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF0_HEADER
#define BIF_CFG_DEV1_EPF0_HEADER__HEADER_TYPE__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF0_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
#define BIF_CFG_DEV1_EPF0_HEADER__HEADER_TYPE_MASK                                                            0x7FL
#define BIF_CFG_DEV1_EPF0_HEADER__DEVICE_TYPE_MASK                                                            0x80L
//BIF_CFG_DEV1_EPF0_BIST
#define BIF_CFG_DEV1_EPF0_BIST__BIST_COMP__SHIFT                                                              0x0
#define BIF_CFG_DEV1_EPF0_BIST__BIST_STRT__SHIFT                                                              0x6
#define BIF_CFG_DEV1_EPF0_BIST__BIST_CAP__SHIFT                                                               0x7
#define BIF_CFG_DEV1_EPF0_BIST__BIST_COMP_MASK                                                                0x0FL
#define BIF_CFG_DEV1_EPF0_BIST__BIST_STRT_MASK                                                                0x40L
#define BIF_CFG_DEV1_EPF0_BIST__BIST_CAP_MASK                                                                 0x80L
//BIF_CFG_DEV1_EPF0_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_BASE_ADDR_6
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_ADAPTER_ID
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR
#define BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_CAP_PTR
#define BIF_CFG_DEV1_EPF0_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
#define BIF_CFG_DEV1_EPF0_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
//BIF_CFG_DEV1_EPF0_INTERRUPT_LINE
#define BIF_CFG_DEV1_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF0_INTERRUPT_PIN
#define BIF_CFG_DEV1_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
//BIF_CFG_DEV1_EPF0_MIN_GRANT
#define BIF_CFG_DEV1_EPF0_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF0_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
//BIF_CFG_DEV1_EPF0_MAX_LATENCY
#define BIF_CFG_DEV1_EPF0_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
#define BIF_CFG_DEV1_EPF0_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
//BIF_CFG_DEV1_EPF0_ADAPTER_ID_W
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PMI_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_EPF0_PMI_CAP
#define BIF_CFG_DEV1_EPF0_PMI_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
#define BIF_CFG_DEV1_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
#define BIF_CFG_DEV1_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
#define BIF_CFG_DEV1_EPF0_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
#define BIF_CFG_DEV1_EPF0_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
#define BIF_CFG_DEV1_EPF0_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
#define BIF_CFG_DEV1_EPF0_PMI_CAP__VERSION_MASK                                                               0x0007L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
#define BIF_CFG_DEV1_EPF0_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
//BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
#define BIF_CFG_DEV1_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
//BIF_CFG_DEV1_EPF0_SBRN
#define BIF_CFG_DEV1_EPF0_SBRN__SBRN__SHIFT                                                                   0x0
#define BIF_CFG_DEV1_EPF0_SBRN__SBRN_MASK                                                                     0xFFL
//BIF_CFG_DEV1_EPF0_FLADJ
#define BIF_CFG_DEV1_EPF0_FLADJ__FLADJ__SHIFT                                                                 0x0
#define BIF_CFG_DEV1_EPF0_FLADJ__NFC__SHIFT                                                                   0x6
#define BIF_CFG_DEV1_EPF0_FLADJ__FLADJ_MASK                                                                   0x3FL
#define BIF_CFG_DEV1_EPF0_FLADJ__NFC_MASK                                                                     0x40L
//BIF_CFG_DEV1_EPF0_DBESL_DBESLD
#define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
#define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
#define BIF_CFG_DEV1_EPF0_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
//BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV1_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV1_EPF0_PCIE_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__VERSION_MASK                                                              0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
#define BIF_CFG_DEV1_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
//BIF_CFG_DEV1_EPF0_DEVICE_CAP
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
//BIF_CFG_DEV1_EPF0_DEVICE_CNTL
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
//BIF_CFG_DEV1_EPF0_DEVICE_STATUS
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
//BIF_CFG_DEV1_EPF0_LINK_CAP
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
#define BIF_CFG_DEV1_EPF0_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV1_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
#define BIF_CFG_DEV1_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
#define BIF_CFG_DEV1_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
#define BIF_CFG_DEV1_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
#define BIF_CFG_DEV1_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
#define BIF_CFG_DEV1_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
#define BIF_CFG_DEV1_EPF0_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
//BIF_CFG_DEV1_EPF0_LINK_CNTL
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
//BIF_CFG_DEV1_EPF0_LINK_STATUS
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
//BIF_CFG_DEV1_EPF0_DEVICE_CAP2
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV1_EPF0_DEVICE_CNTL2
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
#define BIF_CFG_DEV1_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
//BIF_CFG_DEV1_EPF0_DEVICE_STATUS2
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV1_EPF0_LINK_CAP2
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
#define BIF_CFG_DEV1_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
//BIF_CFG_DEV1_EPF0_LINK_CNTL2
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
//BIF_CFG_DEV1_EPF0_LINK_STATUS2
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
//BIF_CFG_DEV1_EPF0_MSI_CAP_LIST
#define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
#define BIF_CFG_DEV1_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
//BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
#define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
//BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_MSI_MSG_DATA
#define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
//BIF_CFG_DEV1_EPF0_MSI_MASK
#define BIF_CFG_DEV1_EPF0_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF0_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
//BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
//BIF_CFG_DEV1_EPF0_MSI_MASK_64
#define BIF_CFG_DEV1_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_MSI_PENDING
#define BIF_CFG_DEV1_EPF0_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_MSI_PENDING_64
#define BIF_CFG_DEV1_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST
#define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV1_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
#define BIF_CFG_DEV1_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
//BIF_CFG_DEV1_EPF0_MSIX_TABLE
#define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
#define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
#define BIF_CFG_DEV1_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
//BIF_CFG_DEV1_EPF0_MSIX_PBA
#define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
#define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
#define BIF_CFG_DEV1_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
//BIF_CFG_DEV1_EPF0_SATA_CAP_0
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__CAP_ID__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__NEXT_PTR__SHIFT                                                         0x8
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                               0x14
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                               0x18
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__CAP_ID_MASK                                                             0x000000FFL
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__NEXT_PTR_MASK                                                           0x0000FF00L
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                                 0x00F00000L
#define BIF_CFG_DEV1_EPF0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                                 0xFF000000L
//BIF_CFG_DEV1_EPF0_SATA_CAP_1
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                              0x4
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                               0x18
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                   0x0000000FL
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                                0x00FFFFF0L
#define BIF_CFG_DEV1_EPF0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                                 0xFF000000L
//BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                    0x2
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                  0x00000003L
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                      0x00000FFCL
#define BIF_CFG_DEV1_EPF0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                  0xFFFFF000L
//BIF_CFG_DEV1_EPF0_SATA_IDP_DATA
#define BIF_CFG_DEV1_EPF0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_SATA_IDP_DATA__IDP_DATA_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
//BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
//BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
//BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
//BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
//BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
//BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
//BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
//BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
#define BIF_CFG_DEV1_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
//BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
//BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
#define BIF_CFG_DEV1_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
//BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
#define BIF_CFG_DEV1_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
//BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
#define BIF_CFG_DEV1_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
//BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
//BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
//BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
//BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
//BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                     0x9
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
#define BIF_CFG_DEV1_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                       0x0000FE00L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
//BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
#define BIF_CFG_DEV1_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
//BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
//BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
#define BIF_CFG_DEV1_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
//BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
//BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
//BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
#define BIF_CFG_DEV1_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
//BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
//BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
#define BIF_CFG_DEV1_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
//BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
//BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
#define BIF_CFG_DEV1_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
//BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV1_EPF0_LINK_CAP_16GT
#define BIF_CFG_DEV1_EPF0_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
#define BIF_CFG_DEV1_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
//BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV1_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV1_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
#define BIF_CFG_DEV1_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
//BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
#define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
#define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
//BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
//BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
//BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV1_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV1_EPF0_RTR_DATA1
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__VALID__SHIFT                                                             0x1f
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
#define BIF_CFG_DEV1_EPF0_RTR_DATA1__VALID_MASK                                                               0x80000000L
//BIF_CFG_DEV1_EPF0_RTR_DATA2
#define BIF_CFG_DEV1_EPF0_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
#define BIF_CFG_DEV1_EPF0_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
#define BIF_CFG_DEV1_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L


// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
//NB_NBCFG0_NB_VENDOR_ID
#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID__SHIFT                                                              0x0
#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID_MASK                                                                0xFFFFL
//NB_NBCFG0_NB_DEVICE_ID
#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID__SHIFT                                                              0x0
#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID_MASK                                                                0xFFFFL
//NB_NBCFG0_NB_COMMAND
#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN__SHIFT                                                             0x0
#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT                                                            0x1
#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN__SHIFT                                                            0x2
#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN_MASK                                                               0x0001L
#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN_MASK                                                              0x0002L
#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN_MASK                                                              0x0004L
//NB_NBCFG0_NB_STATUS
#define NB_NBCFG0_NB_STATUS__CAP_LIST__SHIFT                                                                  0x4
#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                     0xc
#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                     0xd
#define NB_NBCFG0_NB_STATUS__CAP_LIST_MASK                                                                    0x0010L
#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT_MASK                                                       0x1000L
#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT_MASK                                                       0x2000L
//NB_NBCFG0_NB_SUB_CLASS
#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT                                                          0x0
#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF_MASK                                                            0xFFL
//NB_NBCFG0_NB_BASE_CODE
#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT                                                        0x0
#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE_MASK                                                          0xFFL
//NB_NBCFG0_NB_CACHE_LINE
#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                       0x0
#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                         0xFFL
//NB_NBCFG0_NB_LATENCY
#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER__SHIFT                                                            0x0
#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER_MASK                                                              0xFFL
//NB_NBCFG0_NB_HEADER
#define NB_NBCFG0_NB_HEADER__HEADER_TYPE__SHIFT                                                               0x0
#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE__SHIFT                                                               0x7
#define NB_NBCFG0_NB_HEADER__HEADER_TYPE_MASK                                                                 0x7FL
#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE_MASK                                                                 0x80L
//NB_NBCFG0_NB_ADAPTER_ID
#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                                   0x0
#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                          0x10
#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                     0x0000FFFFL
#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                            0xFFFF0000L
//NB_NBCFG0_NB_CAPABILITIES_PTR
#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT                                                         0x0
#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR_MASK                                                           0x000000FFL
//NB_NBCFG0_NB_HEADER_W
#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE__SHIFT                                                             0x7
#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE_MASK                                                               0x00000080L
//NB_NBCFG0_NB_PCI_CTRL
#define NB_NBCFG0_NB_PCI_CTRL__PMEDis__SHIFT                                                                  0x4
#define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT                                                                 0x5
#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable__SHIFT                                                              0x17
#define NB_NBCFG0_NB_PCI_CTRL__HPDis__SHIFT                                                                   0x1a
#define NB_NBCFG0_NB_PCI_CTRL__PMEDis_MASK                                                                    0x00000010L
#define NB_NBCFG0_NB_PCI_CTRL__SErrDis_MASK                                                                   0x00000020L
#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable_MASK                                                                0x00800000L
#define NB_NBCFG0_NB_PCI_CTRL__HPDis_MASK                                                                     0x04000000L
//NB_NBCFG0_NB_ADAPTER_ID_W
#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                        0x10
#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
//NB_NBCFG0_NBCFG_SCRATCH_0
#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT                                                     0x0
#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK                                                       0xFFFFFFFFL
//NB_NBCFG0_NBCFG_SCRATCH_1
#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT                                                     0x0
#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK                                                       0xFFFFFFFFL
//NB_NBCFG0_NBCFG_SCRATCH_2
#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT                                                     0x0
#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK                                                       0xFFFFFFFFL
//NB_NBCFG0_NBCFG_SCRATCH_3
#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT                                                     0x0
#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK                                                       0xFFFFFFFFL
//NB_NBCFG0_NBCFG_SCRATCH_4
#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT                                                     0x0
#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK                                                       0xFFFFFFFFL
//NB_NBCFG0_NB_PCI_ARB
#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                 0x3
#define NB_NBCFG0_NB_PCI_ARB__PMEMode__SHIFT                                                                  0x8
#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff__SHIFT                                                               0x9
#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT                                                           0xa
#define NB_NBCFG0_NB_PCI_ARB__PMETarget__SHIFT                                                                0x10
#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE_MASK                                                                   0x00000008L
#define NB_NBCFG0_NB_PCI_ARB__PMEMode_MASK                                                                    0x00000100L
#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff_MASK                                                                 0x00000200L
#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus_MASK                                                             0x00000400L
#define NB_NBCFG0_NB_PCI_ARB__PMETarget_MASK                                                                  0x00FF0000L
//NB_NBCFG0_NB_DRAM_SLOT1_BASE
#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT                                                        0x17
#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK                                                          0xFF800000L
//NB_NBCFG0_NB_INDEX_DATA_MUTEX0
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT                                           0x0
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT                                    0x1f
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK                                             0x7FFFFFFFL
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK                                      0x80000000L
//NB_NBCFG0_NB_INDEX_DATA_MUTEX1
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT                                           0x0
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT                                    0x1f
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK                                             0x7FFFFFFFL
#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK                                      0x80000000L
//NB_NBCFG0_NB_VENDOR_ID_W
#define NB_NBCFG0_NB_VENDOR_ID_W__VENDOR_ID__SHIFT                                                            0x0
#define NB_NBCFG0_NB_VENDOR_ID_W__VENDOR_ID_MASK                                                              0xFFFFL
//NB_NBCFG0_NB_DEVICE_ID_W
#define NB_NBCFG0_NB_DEVICE_ID_W__DEVICE_ID__SHIFT                                                            0x0
#define NB_NBCFG0_NB_DEVICE_ID_W__DEVICE_ID_MASK                                                              0xFFFFL


// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
//FASTREG_APERTURE
#define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT                                                          0x0
#define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT                                                              0x10
#define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT                                                          0x1f
#define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK                                                            0x00000FFFL
#define FASTREG_APERTURE__FASTREG_NODE_ID_MASK                                                                0x000F0000L
#define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK                                                            0x80000000L


// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
//NB_CNTL
#define NB_CNTL__HWINIT_WR_LOCK__SHIFT                                                                        0x7
#define NB_CNTL__HWINIT_WR_LOCK_MASK                                                                          0x00000080L
//NB_SPARE1
#define NB_SPARE1__NB_SPARE1_RW__SHIFT                                                                        0x0
#define NB_SPARE1__NB_SPARE1_RW_MASK                                                                          0xFFFFFFFFL
//NB_SPARE2
#define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT                                                                    0x0
#define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT                                                                    0x1
#define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT                                                                    0x2
#define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT                                                                    0x3
#define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT                                                                    0x4
#define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT                                                                    0x5
#define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT                                                                    0x6
#define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT                                                                    0x7
#define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT                                                                    0x8
#define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT                                                                    0x9
#define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT                                                                   0xa
#define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT                                                                   0xb
#define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT                                                                   0xc
#define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT                                                                   0xd
#define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT                                                                   0xe
#define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT                                                                   0xf
#define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT                                                                   0x10
#define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT                                                                   0x11
#define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT                                                                   0x12
#define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT                                                                   0x13
#define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT                                                                   0x14
#define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT                                                                   0x15
#define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT                                                                   0x16
#define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT                                                                   0x17
#define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT                                                                   0x18
#define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT                                                                   0x19
#define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT                                                                   0x1a
#define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT                                                                   0x1b
#define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT                                                                   0x1c
#define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT                                                                   0x1d
#define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT                                                                   0x1e
#define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT                                                                   0x1f
#define NB_SPARE2__NB_SPARE2_RW1C_0_MASK                                                                      0x00000001L
#define NB_SPARE2__NB_SPARE2_RW1C_1_MASK                                                                      0x00000002L
#define NB_SPARE2__NB_SPARE2_RW1C_2_MASK                                                                      0x00000004L
#define NB_SPARE2__NB_SPARE2_RW1C_3_MASK                                                                      0x00000008L
#define NB_SPARE2__NB_SPARE2_RW1C_4_MASK                                                                      0x00000010L
#define NB_SPARE2__NB_SPARE2_RW1C_5_MASK                                                                      0x00000020L
#define NB_SPARE2__NB_SPARE2_RW1C_6_MASK                                                                      0x00000040L
#define NB_SPARE2__NB_SPARE2_RW1C_7_MASK                                                                      0x00000080L
#define NB_SPARE2__NB_SPARE2_RW1C_8_MASK                                                                      0x00000100L
#define NB_SPARE2__NB_SPARE2_RW1C_9_MASK                                                                      0x00000200L
#define NB_SPARE2__NB_SPARE2_RW1C_10_MASK                                                                     0x00000400L
#define NB_SPARE2__NB_SPARE2_RW1C_11_MASK                                                                     0x00000800L
#define NB_SPARE2__NB_SPARE2_RW1C_12_MASK                                                                     0x00001000L
#define NB_SPARE2__NB_SPARE2_RW1C_13_MASK                                                                     0x00002000L
#define NB_SPARE2__NB_SPARE2_RW1C_14_MASK                                                                     0x00004000L
#define NB_SPARE2__NB_SPARE2_RW1C_15_MASK                                                                     0x00008000L
#define NB_SPARE2__NB_SPARE2_RW1C_16_MASK                                                                     0x00010000L
#define NB_SPARE2__NB_SPARE2_RW1C_17_MASK                                                                     0x00020000L
#define NB_SPARE2__NB_SPARE2_RW1C_18_MASK                                                                     0x00040000L
#define NB_SPARE2__NB_SPARE2_RW1C_19_MASK                                                                     0x00080000L
#define NB_SPARE2__NB_SPARE2_RW1C_20_MASK                                                                     0x00100000L
#define NB_SPARE2__NB_SPARE2_RW1C_21_MASK                                                                     0x00200000L
#define NB_SPARE2__NB_SPARE2_RW1C_22_MASK                                                                     0x00400000L
#define NB_SPARE2__NB_SPARE2_RW1C_23_MASK                                                                     0x00800000L
#define NB_SPARE2__NB_SPARE2_RW1C_24_MASK                                                                     0x01000000L
#define NB_SPARE2__NB_SPARE2_RW1C_25_MASK                                                                     0x02000000L
#define NB_SPARE2__NB_SPARE2_RW1C_26_MASK                                                                     0x04000000L
#define NB_SPARE2__NB_SPARE2_RW1C_27_MASK                                                                     0x08000000L
#define NB_SPARE2__NB_SPARE2_RW1C_28_MASK                                                                     0x10000000L
#define NB_SPARE2__NB_SPARE2_RW1C_29_MASK                                                                     0x20000000L
#define NB_SPARE2__NB_SPARE2_RW1C_30_MASK                                                                     0x40000000L
#define NB_SPARE2__NB_SPARE2_RW1C_31_MASK                                                                     0x80000000L
//NB_REVID
#define NB_REVID__REVISION_ID__SHIFT                                                                          0x0
#define NB_REVID__REVISION_ID_MASK                                                                            0x000003FFL
//NBIO_LCLK_DS_MASK
#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT                                                                0x0
#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK                                                                  0xFFFFFFFFL
//NB_BUS_NUM_CNTL
#define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT                                                                    0x0
#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT                                                               0x8
#define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK                                                                      0x000000FFL
#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK                                                                 0x00000100L
//NB_MMIOBASE
#define NB_MMIOBASE__MMIOBASE__SHIFT                                                                          0x0
#define NB_MMIOBASE__MMIOBASE_MASK                                                                            0xFFFFFFFFL
//NB_MMIOLIMIT
#define NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                        0x0
#define NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                          0xFFFFFFFFL
//NB_LOWER_TOP_OF_DRAM2
#define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                                  0x0
#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                              0x17
#define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                                    0x00000001L
#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                                0xFF800000L
//NB_UPPER_TOP_OF_DRAM2
#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                              0x0
#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                                0x000001FFL
//NB_LOWER_DRAM2_BASE
#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT                                                          0x17
#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK                                                            0xFF800000L
//NB_UPPER_DRAM2_BASE
#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT                                                          0x0
#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK                                                            0x000001FFL
//SB_LOCATION
#define SB_LOCATION__SBlocated_Port__SHIFT                                                                    0x0
#define SB_LOCATION__SBlocated_Core__SHIFT                                                                    0x10
#define SB_LOCATION__SBlocated_Port_MASK                                                                      0x0000FFFFL
#define SB_LOCATION__SBlocated_Core_MASK                                                                      0xFFFF0000L
//SW_US_LOCATION
#define SW_US_LOCATION__SW_USlocated_Port__SHIFT                                                              0x0
#define SW_US_LOCATION__SW_USlocated_Core__SHIFT                                                              0x10
#define SW_US_LOCATION__SW_USlocated_Port_MASK                                                                0x0000FFFFL
#define SW_US_LOCATION__SW_USlocated_Core_MASK                                                                0xFFFF0000L
//SW_NMI_CNTL
#define SW_NMI_CNTL__SW_NMI_Status__SHIFT                                                                     0x0
#define SW_NMI_CNTL__SW_NMI_Status_MASK                                                                       0xFFFFFFFFL
//SW_SMI_CNTL
#define SW_SMI_CNTL__SW_SMI_Status__SHIFT                                                                     0x0
#define SW_SMI_CNTL__SW_SMI_Status_MASK                                                                       0xFFFFFFFFL
//SW_SCI_CNTL
#define SW_SCI_CNTL__SW_SCI_Status__SHIFT                                                                     0x0
#define SW_SCI_CNTL__SW_SCI_Status_MASK                                                                       0xFFFFFFFFL
//APML_SW_STATUS
#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT                                                                0x0
#define APML_SW_STATUS__APML_NMI_STATUS_MASK                                                                  0x00000001L
//SW_GIC_SPI_CNTL
#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT                                                         0x0
#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT                                                         0x8
#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT                                                         0x10
#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK                                                           0x000000FFL
#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK                                                           0x0000FF00L
#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK                                                           0x00FF0000L
//SW_SYNCFLOOD_CNTL
#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT                                                        0x0
#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT                                                           0x1
#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK                                                          0x00000001L
#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK                                                             0x00000002L
//NB_TOP_OF_DRAM3
#define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT                                                                    0x0
#define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT                                                                   0x1f
#define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK                                                                      0x3FFFFFFFL
#define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK                                                                     0x80000000L
//CAM_CONTROL
#define CAM_CONTROL__CAM_En__SHIFT                                                                            0x0
#define CAM_CONTROL__Op__SHIFT                                                                                0x1
#define CAM_CONTROL__AccessType__SHIFT                                                                        0x2
#define CAM_CONTROL__DataMatchEn__SHIFT                                                                       0x3
#define CAM_CONTROL__VC__SHIFT                                                                                0x4
#define CAM_CONTROL__CrossTrigger__SHIFT                                                                      0x8
#define CAM_CONTROL__CAM_En_MASK                                                                              0x00000001L
#define CAM_CONTROL__Op_MASK                                                                                  0x00000002L
#define CAM_CONTROL__AccessType_MASK                                                                          0x00000004L
#define CAM_CONTROL__DataMatchEn_MASK                                                                         0x00000008L
#define CAM_CONTROL__VC_MASK                                                                                  0x00000070L
#define CAM_CONTROL__CrossTrigger_MASK                                                                        0x00000F00L
//CAM_TARGET_INDEX_ADDR_BOTTOM
#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT                                                  0x0
#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK                                                    0xFFFFFFFFL
//CAM_TARGET_INDEX_ADDR_TOP
#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT                                                        0x0
#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK                                                          0xFFFFFFFFL
//CAM_TARGET_INDEX_DATA
#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT                                                               0x0
#define CAM_TARGET_INDEX_DATA__IndexData_MASK                                                                 0xFFFFFFFFL
//CAM_TARGET_INDEX_DATA_MASK
#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT                                                      0x0
#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK                                                        0xFFFFFFFFL
//CAM_TARGET_DATA_ADDR_BOTTOM
#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT                                                    0x0
#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK                                                      0xFFFFFFFFL
//CAM_TARGET_DATA_ADDR_TOP
#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT                                                          0x0
#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK                                                            0xFFFFFFFFL
//CAM_TARGET_DATA
#define CAM_TARGET_DATA__Data__SHIFT                                                                          0x0
#define CAM_TARGET_DATA__Data_MASK                                                                            0xFFFFFFFFL
//CAM_TARGET_DATA_MASK
#define CAM_TARGET_DATA_MASK__DataMask__SHIFT                                                                 0x0
#define CAM_TARGET_DATA_MASK__DataMask_MASK                                                                   0xFFFFFFFFL
//PCIE_VDM_NODE0_CTRL4
#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT                                                           0x0
#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT                                                          0x8
#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT                                                            0x1f
#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK                                                             0x000000FFL
#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK                                                            0x0000FF00L
#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK                                                              0x80000000L
//PCIE_VDM_CNTL2
#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT                                                                     0x0
#define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT                                                                    0x4
#define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT                                                                   0x5
#define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT                                                                 0x6
#define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT                                                                0xf
#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT                                                                   0x10
#define PCIE_VDM_CNTL2__VdmP2pMode_MASK                                                                       0x00000003L
#define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK                                                                      0x00000010L
#define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK                                                                     0x00000020L
#define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK                                                                   0x00000040L
#define PCIE_VDM_CNTL2__MCTPMasterValid_MASK                                                                  0x00008000L
#define PCIE_VDM_CNTL2__MCTPMasterID_MASK                                                                     0xFFFF0000L
//PCIE_VDM_CNTL3
#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT                                                               0xf
#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT                                                                  0x10
#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK                                                                 0x00008000L
#define PCIE_VDM_CNTL3__APMTPMasterID_MASK                                                                    0xFFFF0000L
//STALL_CONTROL_XBARPORT0_0
#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT0_1
#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT1_0
#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT1_1
#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT2_0
#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT2_1
#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT3_0
#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT3_1
#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT4_0
#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT4_1
#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT5_0
#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK                                                         0x30000000L
//STALL_CONTROL_XBARPORT5_1
#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT                                                       0x0
#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT                                                       0x4
#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT                                                       0x8
#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT                                                       0xc
#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT                                                       0x10
#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT                                                       0x14
#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT                                                       0x1c
#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK                                                         0x00000003L
#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK                                                         0x00000030L
#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK                                                         0x00000300L
#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK                                                         0x00003000L
#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK                                                         0x00030000L
#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK                                                         0x00300000L
#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK                                                         0x30000000L
//NB_DRAM3_BASE
#define NB_DRAM3_BASE__DRAM3_BASE__SHIFT                                                                      0x0
#define NB_DRAM3_BASE__DRAM3_BASE_MASK                                                                        0x3FFFFFFFL
//PSP_BASE_ADDR_LO
#define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT                                                                  0x0
#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT                                                                0x8
#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT                                                             0x14
#define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK                                                                    0x00000001L
#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK                                                                  0x00000100L
#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK                                                               0xFFF00000L
//PSP_BASE_ADDR_HI
#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT                                                             0x0
#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK                                                               0x0000FFFFL
//SMU_BASE_ADDR_LO
#define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT                                                                  0x0
#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT                                                                0x1
#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT                                                             0x14
#define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK                                                                    0x00000001L
#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK                                                                  0x00000002L
#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK                                                               0xFFF00000L
//SMU_BASE_ADDR_HI
#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT                                                             0x0
#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK                                                               0x0000FFFFL
//FASTREG_BASE_ADDR_LO
#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT                                                          0x0
#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT                                                        0x1
#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT                                                     0x14
#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK                                                            0x00000001L
#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK                                                          0x00000002L
#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK                                                       0xFFF00000L
//FASTREG_BASE_ADDR_HI
#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT                                                     0x0
#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK                                                       0x0000FFFFL
//FASTREGCNTL_BASE_ADDR_LO
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT                                                  0x0
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT                                                0x1
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT                                             0xc
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK                                                    0x00000001L
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK                                                  0x00000002L
#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK                                               0xFFFFF000L
//FASTREGCNTL_BASE_ADDR_HI
#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT                                             0x0
#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK                                               0x0000FFFFL
//MISC0_BASE_ADDR_LO
#define MISC0_BASE_ADDR_LO__MISC0_MMIO_EN__SHIFT                                                              0x0
#define MISC0_BASE_ADDR_LO__MISC0_MMIO_LOCK__SHIFT                                                            0x1
#define MISC0_BASE_ADDR_LO__MISC0_BASE_ADDR_LO__SHIFT                                                         0x14
#define MISC0_BASE_ADDR_LO__MISC0_MMIO_EN_MASK                                                                0x00000001L
#define MISC0_BASE_ADDR_LO__MISC0_MMIO_LOCK_MASK                                                              0x00000002L
#define MISC0_BASE_ADDR_LO__MISC0_BASE_ADDR_LO_MASK                                                           0xFFF00000L
//MISC0_BASE_ADDR_HI
#define MISC0_BASE_ADDR_HI__MISC0_BASE_ADDR_HI__SHIFT                                                         0x0
#define MISC0_BASE_ADDR_HI__MISC0_BASE_ADDR_HI_MASK                                                           0x0000FFFFL
//MISC1_BASE_ADDR_LO
#define MISC1_BASE_ADDR_LO__MISC1_MMIO_EN__SHIFT                                                              0x0
#define MISC1_BASE_ADDR_LO__MISC1_MMIO_LOCK__SHIFT                                                            0x1
#define MISC1_BASE_ADDR_LO__MISC1_BASE_ADDR_LO__SHIFT                                                         0x14
#define MISC1_BASE_ADDR_LO__MISC1_MMIO_EN_MASK                                                                0x00000001L
#define MISC1_BASE_ADDR_LO__MISC1_MMIO_LOCK_MASK                                                              0x00000002L
#define MISC1_BASE_ADDR_LO__MISC1_BASE_ADDR_LO_MASK                                                           0xFFF00000L
//MISC1_BASE_ADDR_HI
#define MISC1_BASE_ADDR_HI__MISC1_BASE_ADDR_HI__SHIFT                                                         0x0
#define MISC1_BASE_ADDR_HI__MISC1_BASE_ADDR_HI_MASK                                                           0x0000FFFFL
//MISC2_BASE_ADDR_LO
#define MISC2_BASE_ADDR_LO__MISC2_MMIO_EN__SHIFT                                                              0x0
#define MISC2_BASE_ADDR_LO__MISC2_MMIO_LOCK__SHIFT                                                            0x1
#define MISC2_BASE_ADDR_LO__MISC2_BASE_ADDR_LO__SHIFT                                                         0x14
#define MISC2_BASE_ADDR_LO__MISC2_MMIO_EN_MASK                                                                0x00000001L
#define MISC2_BASE_ADDR_LO__MISC2_MMIO_LOCK_MASK                                                              0x00000002L
#define MISC2_BASE_ADDR_LO__MISC2_BASE_ADDR_LO_MASK                                                           0xFFF00000L
//MISC2_BASE_ADDR_HI
#define MISC2_BASE_ADDR_HI__MISC2_BASE_ADDR_HI__SHIFT                                                         0x0
#define MISC2_BASE_ADDR_HI__MISC2_BASE_ADDR_HI_MASK                                                           0x0000FFFFL
//MISC3_BASE_ADDR_LO
#define MISC3_BASE_ADDR_LO__MISC3_MMIO_EN__SHIFT                                                              0x0
#define MISC3_BASE_ADDR_LO__MISC3_MMIO_LOCK__SHIFT                                                            0x1
#define MISC3_BASE_ADDR_LO__MISC3_BASE_ADDR_LO__SHIFT                                                         0x14
#define MISC3_BASE_ADDR_LO__MISC3_MMIO_EN_MASK                                                                0x00000001L
#define MISC3_BASE_ADDR_LO__MISC3_MMIO_LOCK_MASK                                                              0x00000002L
#define MISC3_BASE_ADDR_LO__MISC3_BASE_ADDR_LO_MASK                                                           0xFFF00000L
//MISC3_BASE_ADDR_HI
#define MISC3_BASE_ADDR_HI__MISC3_BASE_ADDR_HI__SHIFT                                                         0x0
#define MISC3_BASE_ADDR_HI__MISC3_BASE_ADDR_HI_MASK                                                           0x0000FFFFL
//SCRATCH_4
#define SCRATCH_4__SCRATCH_4__SHIFT                                                                           0x0
#define SCRATCH_4__SCRATCH_4_MASK                                                                             0xFFFFFFFFL
//SCRATCH_5
#define SCRATCH_5__SCRATCH_5__SHIFT                                                                           0x0
#define SCRATCH_5__SCRATCH_5_MASK                                                                             0xFFFFFFFFL
//SMU_BLOCK_CPU
#define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT                                                               0x0
#define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK                                                                 0x00000001L
//SMU_BLOCK_CPU_STATUS
#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT                                                       0x0
#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK                                                         0x00000001L
//TRAP_STATUS
#define TRAP_STATUS__TrapReqValid__SHIFT                                                                      0x0
#define TRAP_STATUS__TrapNumber__SHIFT                                                                        0x8
#define TRAP_STATUS__TrapReqValid_MASK                                                                        0x00000001L
#define TRAP_STATUS__TrapNumber_MASK                                                                          0x00000F00L
//TRAP_REQUEST0
#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT                                                                   0x2
#define TRAP_REQUEST0__TrapReqAddrLo_MASK                                                                     0xFFFFFFFCL
//TRAP_REQUEST1
#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT                                                                   0x0
#define TRAP_REQUEST1__TrapReqAddrHi_MASK                                                                     0xFFFFFFFFL
//TRAP_REQUEST2
#define TRAP_REQUEST2__TrapReqCmd__SHIFT                                                                      0x0
#define TRAP_REQUEST2__TrapAttr__SHIFT                                                                        0x8
#define TRAP_REQUEST2__TrapReqLen__SHIFT                                                                      0x10
#define TRAP_REQUEST2__TrapReqCmd_MASK                                                                        0x0000003FL
#define TRAP_REQUEST2__TrapAttr_MASK                                                                          0x0000FF00L
#define TRAP_REQUEST2__TrapReqLen_MASK                                                                        0x003F0000L
//TRAP_REQUEST3
#define TRAP_REQUEST3__TrapReqVC__SHIFT                                                                       0x0
#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT                                                               0x4
#define TRAP_REQUEST3__TrapReqChain__SHIFT                                                                    0x6
#define TRAP_REQUEST3__TrapReqIO__SHIFT                                                                       0x7
#define TRAP_REQUEST3__TrapReqPassPW__SHIFT                                                                   0x8
#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT                                                                0x9
#define TRAP_REQUEST3__TrapReqUnitID__SHIFT                                                                   0x10
#define TRAP_REQUEST3__TrapReqVC_MASK                                                                         0x00000007L
#define TRAP_REQUEST3__TrapReqBlockLevel_MASK                                                                 0x00000030L
#define TRAP_REQUEST3__TrapReqChain_MASK                                                                      0x00000040L
#define TRAP_REQUEST3__TrapReqIO_MASK                                                                         0x00000080L
#define TRAP_REQUEST3__TrapReqPassPW_MASK                                                                     0x00000100L
#define TRAP_REQUEST3__TrapReqRspPassPW_MASK                                                                  0x00000200L
#define TRAP_REQUEST3__TrapReqUnitID_MASK                                                                     0x003F0000L
//TRAP_REQUEST4
#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT                                                                 0x0
#define TRAP_REQUEST4__TrapReqSecLevel_MASK                                                                   0x0000000FL
//TRAP_REQUEST5
#define TRAP_REQUEST5__TrapReqDataVC__SHIFT                                                                   0x0
#define TRAP_REQUEST5__TrapReqDataErr__SHIFT                                                                  0x4
#define TRAP_REQUEST5__TrapReqDataParity__SHIFT                                                               0x8
#define TRAP_REQUEST5__TrapReqDataVC_MASK                                                                     0x00000007L
#define TRAP_REQUEST5__TrapReqDataErr_MASK                                                                    0x00000010L
#define TRAP_REQUEST5__TrapReqDataParity_MASK                                                                 0x0000FF00L
//TRAP_REQUEST_DATASTRB0
#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT                                                      0x0
#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK                                                        0xFFFFFFFFL
//TRAP_REQUEST_DATASTRB1
#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT                                                      0x0
#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK                                                        0xFFFFFFFFL
//TRAP_REQUEST_DATA0
#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA0__TrapReqData0_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA1
#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA1__TrapReqData1_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA2
#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA2__TrapReqData2_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA3
#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA3__TrapReqData3_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA4
#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA4__TrapReqData4_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA5
#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA5__TrapReqData5_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA6
#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA6__TrapReqData6_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA7
#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA7__TrapReqData7_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA8
#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA8__TrapReqData8_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA9
#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT                                                               0x0
#define TRAP_REQUEST_DATA9__TrapReqData9_MASK                                                                 0xFFFFFFFFL
//TRAP_REQUEST_DATA10
#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA10__TrapReqData10_MASK                                                               0xFFFFFFFFL
//TRAP_REQUEST_DATA11
#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA11__TrapReqData11_MASK                                                               0xFFFFFFFFL
//TRAP_REQUEST_DATA12
#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA12__TrapReqData12_MASK                                                               0xFFFFFFFFL
//TRAP_REQUEST_DATA13
#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA13__TrapReqData13_MASK                                                               0xFFFFFFFFL
//TRAP_REQUEST_DATA14
#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA14__TrapReqData14_MASK                                                               0xFFFFFFFFL
//TRAP_REQUEST_DATA15
#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT                                                             0x0
#define TRAP_REQUEST_DATA15__TrapReqData15_MASK                                                               0xFFFFFFFFL
//TRAP_RESPONSE_CONTROL
#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT                                                          0x0
#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT                                                      0x1
#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK                                                            0x00000001L
#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK                                                        0x00000002L
//TRAP_RESPONSE0
#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT                                                                  0x0
#define TRAP_RESPONSE0__TrapRspStatus__SHIFT                                                                  0x4
#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT                                                              0x10
#define TRAP_RESPONSE0__TrapRspPassPW_MASK                                                                    0x00000001L
#define TRAP_RESPONSE0__TrapRspStatus_MASK                                                                    0x000000F0L
#define TRAP_RESPONSE0__TrapRspDataStatus_MASK                                                                0x00FF0000L
//TRAP_RESPONSE_DATA0
#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA1
#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA2
#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA3
#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA4
#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA5
#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA6
#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA7
#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA8
#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA9
#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT                                                            0x0
#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK                                                              0xFFFFFFFFL
//TRAP_RESPONSE_DATA10
#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK                                                            0xFFFFFFFFL
//TRAP_RESPONSE_DATA11
#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK                                                            0xFFFFFFFFL
//TRAP_RESPONSE_DATA12
#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK                                                            0xFFFFFFFFL
//TRAP_RESPONSE_DATA13
#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK                                                            0xFFFFFFFFL
//TRAP_RESPONSE_DATA14
#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK                                                            0xFFFFFFFFL
//TRAP_RESPONSE_DATA15
#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT                                                          0x0
#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK                                                            0xFFFFFFFFL
//TRAP0_CONTROL0
#define TRAP0_CONTROL0__Trap0En__SHIFT                                                                        0x0
#define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT                                                                   0x3
#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT                                                              0x18
#define TRAP0_CONTROL0__Trap0En_MASK                                                                          0x00000001L
#define TRAP0_CONTROL0__Trap0SMUIntr_MASK                                                                     0x00000008L
#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK                                                                0x0F000000L
//TRAP0_ADDRESS_LO
#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT                                                                  0x2
#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP0_ADDRESS_HI
#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT                                                                  0x0
#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP0_COMMAND
#define TRAP0_COMMAND__Trap0Cmd0__SHIFT                                                                       0x0
#define TRAP0_COMMAND__Trap0Cmd1__SHIFT                                                                       0x8
#define TRAP0_COMMAND__Trap0Cmd0_MASK                                                                         0x0000003FL
#define TRAP0_COMMAND__Trap0Cmd1_MASK                                                                         0x00003F00L
//TRAP0_ADDRESS_LO_MASK
#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT                                                         0x2
#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP0_ADDRESS_HI_MASK
#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT                                                         0x0
#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP0_COMMAND_MASK
#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT                                                              0x0
#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT                                                              0x8
#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK                                                                0x00003F00L
//TRAP1_CONTROL0
#define TRAP1_CONTROL0__Trap1En__SHIFT                                                                        0x0
#define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT                                                                   0x3
#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT                                                              0x18
#define TRAP1_CONTROL0__Trap1En_MASK                                                                          0x00000001L
#define TRAP1_CONTROL0__Trap1SMUIntr_MASK                                                                     0x00000008L
#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK                                                                0x0F000000L
//TRAP1_ADDRESS_LO
#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT                                                                  0x2
#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP1_ADDRESS_HI
#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT                                                                  0x0
#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP1_COMMAND
#define TRAP1_COMMAND__Trap1Cmd0__SHIFT                                                                       0x0
#define TRAP1_COMMAND__Trap1Cmd1__SHIFT                                                                       0x8
#define TRAP1_COMMAND__Trap1Cmd0_MASK                                                                         0x0000003FL
#define TRAP1_COMMAND__Trap1Cmd1_MASK                                                                         0x00003F00L
//TRAP1_ADDRESS_LO_MASK
#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT                                                         0x2
#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP1_ADDRESS_HI_MASK
#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT                                                         0x0
#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP1_COMMAND_MASK
#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT                                                              0x0
#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT                                                              0x8
#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK                                                                0x00003F00L
//TRAP2_CONTROL0
#define TRAP2_CONTROL0__Trap2En__SHIFT                                                                        0x0
#define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT                                                                   0x3
#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT                                                              0x18
#define TRAP2_CONTROL0__Trap2En_MASK                                                                          0x00000001L
#define TRAP2_CONTROL0__Trap2SMUIntr_MASK                                                                     0x00000008L
#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK                                                                0x0F000000L
//TRAP2_ADDRESS_LO
#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT                                                                  0x2
#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP2_ADDRESS_HI
#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT                                                                  0x0
#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP2_COMMAND
#define TRAP2_COMMAND__Trap2Cmd0__SHIFT                                                                       0x0
#define TRAP2_COMMAND__Trap2Cmd1__SHIFT                                                                       0x8
#define TRAP2_COMMAND__Trap2Cmd0_MASK                                                                         0x0000003FL
#define TRAP2_COMMAND__Trap2Cmd1_MASK                                                                         0x00003F00L
//TRAP2_ADDRESS_LO_MASK
#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT                                                         0x2
#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP2_ADDRESS_HI_MASK
#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT                                                         0x0
#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP2_COMMAND_MASK
#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT                                                              0x0
#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT                                                              0x8
#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK                                                                0x00003F00L
//TRAP3_CONTROL0
#define TRAP3_CONTROL0__Trap3En__SHIFT                                                                        0x0
#define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT                                                                   0x3
#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT                                                              0x18
#define TRAP3_CONTROL0__Trap3En_MASK                                                                          0x00000001L
#define TRAP3_CONTROL0__Trap3SMUIntr_MASK                                                                     0x00000008L
#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK                                                                0x0F000000L
//TRAP3_ADDRESS_LO
#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT                                                                  0x2
#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP3_ADDRESS_HI
#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT                                                                  0x0
#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP3_COMMAND
#define TRAP3_COMMAND__Trap3Cmd0__SHIFT                                                                       0x0
#define TRAP3_COMMAND__Trap3Cmd1__SHIFT                                                                       0x8
#define TRAP3_COMMAND__Trap3Cmd0_MASK                                                                         0x0000003FL
#define TRAP3_COMMAND__Trap3Cmd1_MASK                                                                         0x00003F00L
//TRAP3_ADDRESS_LO_MASK
#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT                                                         0x2
#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP3_ADDRESS_HI_MASK
#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT                                                         0x0
#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP3_COMMAND_MASK
#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT                                                              0x0
#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT                                                              0x8
#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK                                                                0x00003F00L
//TRAP4_CONTROL0
#define TRAP4_CONTROL0__Trap4En__SHIFT                                                                        0x0
#define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT                                                                   0x3
#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT                                                              0x18
#define TRAP4_CONTROL0__Trap4En_MASK                                                                          0x00000001L
#define TRAP4_CONTROL0__Trap4SMUIntr_MASK                                                                     0x00000008L
#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK                                                                0x0F000000L
//TRAP4_ADDRESS_LO
#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT                                                                  0x2
#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP4_ADDRESS_HI
#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT                                                                  0x0
#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP4_COMMAND
#define TRAP4_COMMAND__Trap4Cmd0__SHIFT                                                                       0x0
#define TRAP4_COMMAND__Trap4Cmd1__SHIFT                                                                       0x8
#define TRAP4_COMMAND__Trap4Cmd0_MASK                                                                         0x0000003FL
#define TRAP4_COMMAND__Trap4Cmd1_MASK                                                                         0x00003F00L
//TRAP4_ADDRESS_LO_MASK
#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT                                                         0x2
#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP4_ADDRESS_HI_MASK
#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT                                                         0x0
#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP4_COMMAND_MASK
#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT                                                              0x0
#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT                                                              0x8
#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK                                                                0x00003F00L
//TRAP5_CONTROL0
#define TRAP5_CONTROL0__Trap5En__SHIFT                                                                        0x0
#define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT                                                                   0x3
#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT                                                              0x18
#define TRAP5_CONTROL0__Trap5En_MASK                                                                          0x00000001L
#define TRAP5_CONTROL0__Trap5SMUIntr_MASK                                                                     0x00000008L
#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK                                                                0x0F000000L
//TRAP5_ADDRESS_LO
#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT                                                                  0x2
#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP5_ADDRESS_HI
#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT                                                                  0x0
#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP5_COMMAND
#define TRAP5_COMMAND__Trap5Cmd0__SHIFT                                                                       0x0
#define TRAP5_COMMAND__Trap5Cmd1__SHIFT                                                                       0x8
#define TRAP5_COMMAND__Trap5Cmd0_MASK                                                                         0x0000003FL
#define TRAP5_COMMAND__Trap5Cmd1_MASK                                                                         0x00003F00L
//TRAP5_ADDRESS_LO_MASK
#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT                                                         0x2
#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP5_ADDRESS_HI_MASK
#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT                                                         0x0
#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP5_COMMAND_MASK
#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT                                                              0x0
#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT                                                              0x8
#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK                                                                0x00003F00L
//TRAP6_CONTROL0
#define TRAP6_CONTROL0__Trap6En__SHIFT                                                                        0x0
#define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT                                                                   0x3
#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT                                                              0x18
#define TRAP6_CONTROL0__Trap6En_MASK                                                                          0x00000001L
#define TRAP6_CONTROL0__Trap6SMUIntr_MASK                                                                     0x00000008L
#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK                                                                0x0F000000L
//TRAP6_ADDRESS_LO
#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT                                                                  0x2
#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP6_ADDRESS_HI
#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT                                                                  0x0
#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP6_COMMAND
#define TRAP6_COMMAND__Trap6Cmd0__SHIFT                                                                       0x0
#define TRAP6_COMMAND__Trap6Cmd1__SHIFT                                                                       0x8
#define TRAP6_COMMAND__Trap6Cmd0_MASK                                                                         0x0000003FL
#define TRAP6_COMMAND__Trap6Cmd1_MASK                                                                         0x00003F00L
//TRAP6_ADDRESS_LO_MASK
#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT                                                         0x2
#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP6_ADDRESS_HI_MASK
#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT                                                         0x0
#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP6_COMMAND_MASK
#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT                                                              0x0
#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT                                                              0x8
#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK                                                                0x00003F00L
//TRAP7_CONTROL0
#define TRAP7_CONTROL0__Trap7En__SHIFT                                                                        0x0
#define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT                                                                   0x3
#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT                                                              0x18
#define TRAP7_CONTROL0__Trap7En_MASK                                                                          0x00000001L
#define TRAP7_CONTROL0__Trap7SMUIntr_MASK                                                                     0x00000008L
#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK                                                                0x0F000000L
//TRAP7_ADDRESS_LO
#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT                                                                  0x2
#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP7_ADDRESS_HI
#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT                                                                  0x0
#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP7_COMMAND
#define TRAP7_COMMAND__Trap7Cmd0__SHIFT                                                                       0x0
#define TRAP7_COMMAND__Trap7Cmd1__SHIFT                                                                       0x8
#define TRAP7_COMMAND__Trap7Cmd0_MASK                                                                         0x0000003FL
#define TRAP7_COMMAND__Trap7Cmd1_MASK                                                                         0x00003F00L
//TRAP7_ADDRESS_LO_MASK
#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT                                                         0x2
#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP7_ADDRESS_HI_MASK
#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT                                                         0x0
#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP7_COMMAND_MASK
#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT                                                              0x0
#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT                                                              0x8
#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK                                                                0x00003F00L
//TRAP8_CONTROL0
#define TRAP8_CONTROL0__Trap8En__SHIFT                                                                        0x0
#define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT                                                                   0x3
#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT                                                              0x18
#define TRAP8_CONTROL0__Trap8En_MASK                                                                          0x00000001L
#define TRAP8_CONTROL0__Trap8SMUIntr_MASK                                                                     0x00000008L
#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK                                                                0x0F000000L
//TRAP8_ADDRESS_LO
#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT                                                                  0x2
#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP8_ADDRESS_HI
#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT                                                                  0x0
#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP8_COMMAND
#define TRAP8_COMMAND__Trap8Cmd0__SHIFT                                                                       0x0
#define TRAP8_COMMAND__Trap8Cmd1__SHIFT                                                                       0x8
#define TRAP8_COMMAND__Trap8Cmd0_MASK                                                                         0x0000003FL
#define TRAP8_COMMAND__Trap8Cmd1_MASK                                                                         0x00003F00L
//TRAP8_ADDRESS_LO_MASK
#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT                                                         0x2
#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP8_ADDRESS_HI_MASK
#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT                                                         0x0
#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP8_COMMAND_MASK
#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT                                                              0x0
#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT                                                              0x8
#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK                                                                0x00003F00L
//TRAP9_CONTROL0
#define TRAP9_CONTROL0__Trap9En__SHIFT                                                                        0x0
#define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT                                                                   0x3
#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT                                                              0x18
#define TRAP9_CONTROL0__Trap9En_MASK                                                                          0x00000001L
#define TRAP9_CONTROL0__Trap9SMUIntr_MASK                                                                     0x00000008L
#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK                                                                0x0F000000L
//TRAP9_ADDRESS_LO
#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT                                                                  0x2
#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK                                                                    0xFFFFFFFCL
//TRAP9_ADDRESS_HI
#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT                                                                  0x0
#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK                                                                    0xFFFFFFFFL
//TRAP9_COMMAND
#define TRAP9_COMMAND__Trap9Cmd0__SHIFT                                                                       0x0
#define TRAP9_COMMAND__Trap9Cmd1__SHIFT                                                                       0x8
#define TRAP9_COMMAND__Trap9Cmd0_MASK                                                                         0x0000003FL
#define TRAP9_COMMAND__Trap9Cmd1_MASK                                                                         0x00003F00L
//TRAP9_ADDRESS_LO_MASK
#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT                                                         0x2
#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK                                                           0xFFFFFFFCL
//TRAP9_ADDRESS_HI_MASK
#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT                                                         0x0
#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK                                                           0xFFFFFFFFL
//TRAP9_COMMAND_MASK
#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT                                                              0x0
#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT                                                              0x8
#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK                                                                0x0000003FL
#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK                                                                0x00003F00L
//TRAP10_CONTROL0
#define TRAP10_CONTROL0__Trap10En__SHIFT                                                                      0x0
#define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT                                                                 0x3
#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT                                                            0x18
#define TRAP10_CONTROL0__Trap10En_MASK                                                                        0x00000001L
#define TRAP10_CONTROL0__Trap10SMUIntr_MASK                                                                   0x00000008L
#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK                                                              0x0F000000L
//TRAP10_ADDRESS_LO
#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT                                                                0x2
#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP10_ADDRESS_HI
#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT                                                                0x0
#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP10_COMMAND
#define TRAP10_COMMAND__Trap10Cmd0__SHIFT                                                                     0x0
#define TRAP10_COMMAND__Trap10Cmd1__SHIFT                                                                     0x8
#define TRAP10_COMMAND__Trap10Cmd0_MASK                                                                       0x0000003FL
#define TRAP10_COMMAND__Trap10Cmd1_MASK                                                                       0x00003F00L
//TRAP10_ADDRESS_LO_MASK
#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT                                                       0x2
#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP10_ADDRESS_HI_MASK
#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT                                                       0x0
#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP10_COMMAND_MASK
#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT                                                            0x0
#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT                                                            0x8
#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK                                                              0x00003F00L
//TRAP11_CONTROL0
#define TRAP11_CONTROL0__Trap11En__SHIFT                                                                      0x0
#define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT                                                                 0x3
#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT                                                            0x18
#define TRAP11_CONTROL0__Trap11En_MASK                                                                        0x00000001L
#define TRAP11_CONTROL0__Trap11SMUIntr_MASK                                                                   0x00000008L
#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK                                                              0x0F000000L
//TRAP11_ADDRESS_LO
#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT                                                                0x2
#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP11_ADDRESS_HI
#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT                                                                0x0
#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP11_COMMAND
#define TRAP11_COMMAND__Trap11Cmd0__SHIFT                                                                     0x0
#define TRAP11_COMMAND__Trap11Cmd1__SHIFT                                                                     0x8
#define TRAP11_COMMAND__Trap11Cmd0_MASK                                                                       0x0000003FL
#define TRAP11_COMMAND__Trap11Cmd1_MASK                                                                       0x00003F00L
//TRAP11_ADDRESS_LO_MASK
#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT                                                       0x2
#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP11_ADDRESS_HI_MASK
#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT                                                       0x0
#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP11_COMMAND_MASK
#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT                                                            0x0
#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT                                                            0x8
#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK                                                              0x00003F00L
//TRAP12_CONTROL0
#define TRAP12_CONTROL0__Trap12En__SHIFT                                                                      0x0
#define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT                                                                 0x3
#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT                                                            0x18
#define TRAP12_CONTROL0__Trap12En_MASK                                                                        0x00000001L
#define TRAP12_CONTROL0__Trap12SMUIntr_MASK                                                                   0x00000008L
#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK                                                              0x0F000000L
//TRAP12_ADDRESS_LO
#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT                                                                0x2
#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP12_ADDRESS_HI
#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT                                                                0x0
#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP12_COMMAND
#define TRAP12_COMMAND__Trap12Cmd0__SHIFT                                                                     0x0
#define TRAP12_COMMAND__Trap12Cmd1__SHIFT                                                                     0x8
#define TRAP12_COMMAND__Trap12Cmd0_MASK                                                                       0x0000003FL
#define TRAP12_COMMAND__Trap12Cmd1_MASK                                                                       0x00003F00L
//TRAP12_ADDRESS_LO_MASK
#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT                                                       0x2
#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP12_ADDRESS_HI_MASK
#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT                                                       0x0
#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP12_COMMAND_MASK
#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT                                                            0x0
#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT                                                            0x8
#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK                                                              0x00003F00L
//TRAP13_CONTROL0
#define TRAP13_CONTROL0__Trap13En__SHIFT                                                                      0x0
#define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT                                                                 0x3
#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT                                                            0x18
#define TRAP13_CONTROL0__Trap13En_MASK                                                                        0x00000001L
#define TRAP13_CONTROL0__Trap13SMUIntr_MASK                                                                   0x00000008L
#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK                                                              0x0F000000L
//TRAP13_ADDRESS_LO
#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT                                                                0x2
#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP13_ADDRESS_HI
#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT                                                                0x0
#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP13_COMMAND
#define TRAP13_COMMAND__Trap13Cmd0__SHIFT                                                                     0x0
#define TRAP13_COMMAND__Trap13Cmd1__SHIFT                                                                     0x8
#define TRAP13_COMMAND__Trap13Cmd0_MASK                                                                       0x0000003FL
#define TRAP13_COMMAND__Trap13Cmd1_MASK                                                                       0x00003F00L
//TRAP13_ADDRESS_LO_MASK
#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT                                                       0x2
#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP13_ADDRESS_HI_MASK
#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT                                                       0x0
#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP13_COMMAND_MASK
#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT                                                            0x0
#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT                                                            0x8
#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK                                                              0x00003F00L
//TRAP14_CONTROL0
#define TRAP14_CONTROL0__Trap14En__SHIFT                                                                      0x0
#define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT                                                                 0x3
#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT                                                            0x18
#define TRAP14_CONTROL0__Trap14En_MASK                                                                        0x00000001L
#define TRAP14_CONTROL0__Trap14SMUIntr_MASK                                                                   0x00000008L
#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK                                                              0x0F000000L
//TRAP14_ADDRESS_LO
#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT                                                                0x2
#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP14_ADDRESS_HI
#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT                                                                0x0
#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP14_COMMAND
#define TRAP14_COMMAND__Trap14Cmd0__SHIFT                                                                     0x0
#define TRAP14_COMMAND__Trap14Cmd1__SHIFT                                                                     0x8
#define TRAP14_COMMAND__Trap14Cmd0_MASK                                                                       0x0000003FL
#define TRAP14_COMMAND__Trap14Cmd1_MASK                                                                       0x00003F00L
//TRAP14_ADDRESS_LO_MASK
#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT                                                       0x2
#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP14_ADDRESS_HI_MASK
#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT                                                       0x0
#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP14_COMMAND_MASK
#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT                                                            0x0
#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT                                                            0x8
#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK                                                              0x00003F00L
//TRAP15_CONTROL0
#define TRAP15_CONTROL0__Trap15En__SHIFT                                                                      0x0
#define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT                                                                 0x3
#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT                                                            0x18
#define TRAP15_CONTROL0__Trap15En_MASK                                                                        0x00000001L
#define TRAP15_CONTROL0__Trap15SMUIntr_MASK                                                                   0x00000008L
#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK                                                              0x0F000000L
//TRAP15_ADDRESS_LO
#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT                                                                0x2
#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK                                                                  0xFFFFFFFCL
//TRAP15_ADDRESS_HI
#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT                                                                0x0
#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK                                                                  0xFFFFFFFFL
//TRAP15_COMMAND
#define TRAP15_COMMAND__Trap15Cmd0__SHIFT                                                                     0x0
#define TRAP15_COMMAND__Trap15Cmd1__SHIFT                                                                     0x8
#define TRAP15_COMMAND__Trap15Cmd0_MASK                                                                       0x0000003FL
#define TRAP15_COMMAND__Trap15Cmd1_MASK                                                                       0x00003F00L
//TRAP15_ADDRESS_LO_MASK
#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT                                                       0x2
#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK                                                         0xFFFFFFFCL
//TRAP15_ADDRESS_HI_MASK
#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT                                                       0x0
#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK                                                         0xFFFFFFFFL
//TRAP15_COMMAND_MASK
#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT                                                            0x0
#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT                                                            0x8
#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK                                                              0x0000003FL
#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK                                                              0x00003F00L
//SB_COMMAND
#define SB_COMMAND__IO_ACCESS_EN__SHIFT                                                                       0x0
#define SB_COMMAND__MEM_ACCESS_EN__SHIFT                                                                      0x1
#define SB_COMMAND__BUS_MASTER_EN__SHIFT                                                                      0x2
#define SB_COMMAND__IO_ACCESS_EN_MASK                                                                         0x0001L
#define SB_COMMAND__MEM_ACCESS_EN_MASK                                                                        0x0002L
#define SB_COMMAND__BUS_MASTER_EN_MASK                                                                        0x0004L
//SB_SUB_BUS_NUMBER_LATENCY
#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                       0x8
#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                         0x10
#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                         0x0000FF00L
#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                           0x00FF0000L
//SB_IO_BASE_LIMIT
#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                      0x4
#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                     0xc
#define SB_IO_BASE_LIMIT__IO_BASE_MASK                                                                        0x00F0L
#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                       0xF000L
//SB_MEM_BASE_LIMIT
#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                              0x4
#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                             0x14
#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                                0x0000FFF0L
#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                               0xFFF00000L
//SB_PREF_BASE_LIMIT
#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                        0x4
#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                       0x14
#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                          0x0000FFF0L
#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                         0xFFF00000L
//SB_PREF_BASE_UPPER
#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                            0x0
#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                              0xFFFFFFFFL
//SB_PREF_LIMIT_UPPER
#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                          0x0
#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                            0xFFFFFFFFL
//SB_IO_BASE_LIMIT_HI
#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                             0x0
#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                            0x10
#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                               0x0000FFFFL
#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                              0xFFFF0000L
//SB_IRQ_BRIDGE_CNTL
#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                     0x2
#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                     0x3
#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                                    0x4
#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                       0x0004L
#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                       0x0008L
#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                      0x0010L
//SB_EXT_BRIDGE_CNTL
#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                              0x0
#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                                0x01L
//SB_PMI_STATUS_CNTL
#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                                0x0
#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK                                                                  0x03L
//SB_SLOT_CAP
#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                              0x7
#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                              0xf
#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                                0x00007F80L
#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                                0x00018000L
//SB_ROOT_CNTL
#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                       0x4
#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                         0x0010L
//SB_DEVICE_CNTL2
#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                             0x5
#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                               0x0020L
//USB_QoS_CNTL
#define USB_QoS_CNTL__UnitID0__SHIFT                                                                          0x0
#define USB_QoS_CNTL__UnitID0QoSPriority__SHIFT                                                               0x8
#define USB_QoS_CNTL__UnitID0Enable__SHIFT                                                                    0xc
#define USB_QoS_CNTL__UnitID1__SHIFT                                                                          0x10
#define USB_QoS_CNTL__UnitID1QoSPriority__SHIFT                                                               0x18
#define USB_QoS_CNTL__UnitID1Enable__SHIFT                                                                    0x1c
#define USB_QoS_CNTL__UnitID0_MASK                                                                            0x0000007FL
#define USB_QoS_CNTL__UnitID0QoSPriority_MASK                                                                 0x00000F00L
#define USB_QoS_CNTL__UnitID0Enable_MASK                                                                      0x00001000L
#define USB_QoS_CNTL__UnitID1_MASK                                                                            0x007F0000L
#define USB_QoS_CNTL__UnitID1QoSPriority_MASK                                                                 0x0F000000L
#define USB_QoS_CNTL__UnitID1Enable_MASK                                                                      0x10000000L
//MCA_SMN_INT_REQ_ADDR
#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT                                                         0x0
#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK                                                           0x000FFFFFL
//MCA_SMN_INT_MCM_ADDR
#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT                                                         0x0
#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK                                                           0x0000000FL
//MCA_SMN_INT_APERTUREID
#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT                                                     0x0
#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK                                                       0x00000FFFL
//MCA_SMN_INT_CONTROL
#define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT                                                           0x0
#define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK                                                             0x0000000FL


// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
//PARITY_CONTROL_0
#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT                                                          0x0
#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT                                                           0x10
#define PARITY_CONTROL_0__ParityCorrThreshold_MASK                                                            0x0000FFFFL
#define PARITY_CONTROL_0__ParityUCPThreshold_MASK                                                             0xFFFF0000L
//PARITY_CONTROL_1
#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT                                                         0x0
#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT                                                     0x8
#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT                                                            0xb
#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT                                                              0x10
#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT                                                          0x1e
#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT                                                      0x1f
#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK                                                           0x000000FFL
#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK                                                       0x00000100L
#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK                                                              0x0000F800L
#define PARITY_CONTROL_1__ParityErrGenCmd_MASK                                                                0x000F0000L
#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK                                                            0x40000000L
#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK                                                        0x80000000L
//PARITY_SEVERITY_CONTROL_UNCORR_0
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT                                       0x0
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT                                       0x2
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT                                       0x4
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT                                       0x6
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT                                       0x8
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT                                       0xa
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT                                       0xc
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT                                       0xe
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT                                       0x10
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK                                         0x00000003L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK                                         0x0000000CL
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK                                         0x00000030L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK                                         0x000000C0L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK                                         0x00000300L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK                                         0x00000C00L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK                                         0x00003000L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK                                         0x0000C000L
#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK                                         0x00030000L
//PARITY_SEVERITY_CONTROL_CORR_0
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT                                           0x0
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT                                           0x2
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT                                           0x4
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT                                           0x6
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT                                           0x8
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT                                           0xa
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT                                           0xc
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT                                           0xe
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT                                           0x10
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK                                             0x00000003L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK                                             0x0000000CL
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK                                             0x00000030L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK                                             0x000000C0L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK                                             0x00000300L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK                                             0x00000C00L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK                                             0x00003000L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK                                             0x0000C000L
#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK                                             0x00030000L
//PARITY_SEVERITY_CONTROL_UCP_0
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT                                             0x0
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT                                             0x2
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT                                             0x4
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT                                             0x6
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT                                             0x8
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT                                             0xa
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT                                             0xc
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT                                             0xe
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT                                             0x10
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK                                               0x00000003L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK                                               0x0000000CL
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK                                               0x00000030L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK                                               0x000000C0L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK                                               0x00000300L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK                                               0x00000C00L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK                                               0x00003000L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK                                               0x0000C000L
#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK                                               0x00030000L
//MISC_SEVERITY_CONTROL
#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT                                                          0x4
#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT                                                        0x6
#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK                                                            0x00000030L
#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK                                                          0x000000C0L
//MISC_RAS_CONTROL
#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT                                                         0x2
#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT                                                          0x3
#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT                                                           0x9
#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT                                                             0xa
#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT                                                             0xb
#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT                                                                  0xc
#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT                                                                  0xd
#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT                                                                  0xe
#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT                                                                    0xf
#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT                                                                    0x10
#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT                                                                    0x11
#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK                                                           0x00000004L
#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK                                                            0x00000008L
#define MISC_RAS_CONTROL__InterruptOutputDis_MASK                                                             0x00000200L
#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK                                                               0x00000400L
#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK                                                               0x00000800L
#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK                                                                    0x00001000L
#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK                                                                    0x00002000L
#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK                                                                    0x00004000L
#define MISC_RAS_CONTROL__SW_SCI_En_MASK                                                                      0x00008000L
#define MISC_RAS_CONTROL__SW_SMI_En_MASK                                                                      0x00010000L
#define MISC_RAS_CONTROL__SW_NMI_En_MASK                                                                      0x00020000L
//RAS_SCRATCH_0
#define RAS_SCRATCH_0__SCRATCH_0__SHIFT                                                                       0x0
#define RAS_SCRATCH_0__SCRATCH_0_MASK                                                                         0xFFFFFFFFL
//RAS_SCRATCH_1
#define RAS_SCRATCH_1__SCRATCH_1__SHIFT                                                                       0x0
#define RAS_SCRATCH_1__SCRATCH_1_MASK                                                                         0xFFFFFFFFL
//SYNCFLOOD_STATUS
#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT                                                         0x0
#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT                                                            0x1
#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT                                                             0x2
#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT                                                         0x4
#define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT                                                             0x5
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT                                                     0x8
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT                                                     0x9
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT                                                    0xa
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT                                                    0xb
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT                                                    0xc
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT                                                    0xd
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT                                                    0xe
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT                                                    0xf
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT                                                    0x10
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT                                                    0x11
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT                                                    0x12
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT                                                    0x13
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT                                                    0x14
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT                                                    0x15
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT                                                    0x16
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT                                                    0x17
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT                                                    0x18
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT                                                    0x19
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT                                                    0x1a
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT                                                    0x1b
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT                                                    0x1c
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT                                                    0x1d
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT                                                    0x1e
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT                                                    0x1f
#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK                                                           0x00000001L
#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK                                                              0x00000002L
#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK                                                               0x00000004L
#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK                                                           0x00000010L
#define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK                                                               0x00000020L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK                                                       0x00000100L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK                                                       0x00000200L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK                                                      0x00000400L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK                                                      0x00000800L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK                                                      0x00001000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK                                                      0x00002000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK                                                      0x00004000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK                                                      0x00008000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK                                                      0x00010000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK                                                      0x00020000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK                                                      0x00040000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK                                                      0x00080000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK                                                      0x00100000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK                                                      0x00200000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK                                                      0x00400000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK                                                      0x00800000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK                                                      0x01000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK                                                      0x02000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK                                                      0x04000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK                                                      0x08000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK                                                      0x10000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK                                                      0x20000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK                                                      0x40000000L
#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK                                                      0x80000000L
//NMI_STATUS
#define NMI_STATUS__NMIFromPin__SHIFT                                                                         0x0
#define NMI_STATUS__NMIFromPin_MASK                                                                           0x00000001L
//INTERNAL_POISON_STATUS
#define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT                                                      0x0
#define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT                                                      0x1
#define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT                                                      0x2
#define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT                                                      0x3
#define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT                                                      0x4
#define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT                                                      0x5
#define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT                                                      0x6
#define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT                                                      0x7
#define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK                                                        0x00000001L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK                                                        0x00000002L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK                                                        0x00000004L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK                                                        0x00000008L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK                                                        0x00000010L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK                                                        0x00000020L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK                                                        0x00000040L
#define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK                                                        0x00000080L
//INTERNAL_POISON_MASK
#define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT                                                            0x0
#define INTERNAL_POISON_MASK__IntPoisonMask_MASK                                                              0x000000FFL
//EGRESS_POISON_STATUS_LO
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT                                                0x0
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT                                                0x1
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT                                                0x2
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT                                                0x3
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT                                                0x4
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT                                                0x5
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT                                                0x6
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT                                                0x7
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT                                                0x8
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT                                                0x9
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT                                               0xa
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT                                               0xb
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT                                               0xc
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT                                               0xd
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT                                               0xe
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT                                               0xf
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT                                               0x10
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT                                               0x11
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT                                               0x12
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT                                               0x13
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT                                               0x14
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT                                               0x15
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT                                               0x16
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT                                               0x17
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT                                               0x18
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT                                               0x19
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT                                               0x1a
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT                                               0x1b
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT                                               0x1c
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT                                               0x1d
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT                                               0x1e
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT                                               0x1f
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK                                                  0x00000001L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK                                                  0x00000002L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK                                                  0x00000004L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK                                                  0x00000008L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK                                                  0x00000010L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK                                                  0x00000020L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK                                                  0x00000040L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK                                                  0x00000080L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK                                                  0x00000100L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK                                                  0x00000200L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK                                                 0x00000400L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK                                                 0x00000800L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK                                                 0x00001000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK                                                 0x00002000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK                                                 0x00004000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK                                                 0x00008000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK                                                 0x00010000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK                                                 0x00020000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK                                                 0x00040000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK                                                 0x00080000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK                                                 0x00100000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK                                                 0x00200000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK                                                 0x00400000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK                                                 0x00800000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK                                                 0x01000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK                                                 0x02000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK                                                 0x04000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK                                                 0x08000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK                                                 0x10000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK                                                 0x20000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK                                                 0x40000000L
#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK                                                 0x80000000L
//EGRESS_POISON_STATUS_HI
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT                                                0x0
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT                                                0x1
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT                                                0x2
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT                                                0x3
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT                                                0x4
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT                                                0x5
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT                                                0x6
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT                                                0x7
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT                                                0x8
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT                                                0x9
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT                                               0xa
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT                                               0xb
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT                                               0xc
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT                                               0xd
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT                                               0xe
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT                                               0xf
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT                                               0x10
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT                                               0x11
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT                                               0x12
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT                                               0x13
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT                                               0x14
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT                                               0x15
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT                                               0x16
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT                                               0x17
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT                                               0x18
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT                                               0x19
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT                                               0x1a
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT                                               0x1b
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT                                               0x1c
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT                                               0x1d
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT                                               0x1e
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT                                               0x1f
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK                                                  0x00000001L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK                                                  0x00000002L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK                                                  0x00000004L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK                                                  0x00000008L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK                                                  0x00000010L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK                                                  0x00000020L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK                                                  0x00000040L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK                                                  0x00000080L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK                                                  0x00000100L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK                                                  0x00000200L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK                                                 0x00000400L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK                                                 0x00000800L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK                                                 0x00001000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK                                                 0x00002000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK                                                 0x00004000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK                                                 0x00008000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK                                                 0x00010000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK                                                 0x00020000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK                                                 0x00040000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK                                                 0x00080000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK                                                 0x00100000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK                                                 0x00200000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK                                                 0x00400000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK                                                 0x00800000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK                                                 0x01000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK                                                 0x02000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK                                                 0x04000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK                                                 0x08000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK                                                 0x10000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK                                                 0x20000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK                                                 0x40000000L
#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK                                                 0x80000000L
//EGRESS_POISON_MASK_LO
#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT                                                      0x0
#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK                                                        0xFFFFFFFFL
//EGRESS_POISON_MASK_HI
#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT                                                      0x0
#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK                                                        0xFFFFFFFFL
//EGRESS_POISON_SEVERITY_DOWN
#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT                                          0x0
#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK                                            0xFFFFFFFFL
//EGRESS_POISON_SEVERITY_UPPER
#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT                                        0x0
#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK                                          0xFFFFFFFFL
//APML_STATUS
#define APML_STATUS__APML_Corr__SHIFT                                                                         0x0
#define APML_STATUS__APML_NonFatal__SHIFT                                                                     0x1
#define APML_STATUS__APML_Fatal__SHIFT                                                                        0x2
#define APML_STATUS__APML_Serr__SHIFT                                                                         0x3
#define APML_STATUS__APML_IntPoisonErr__SHIFT                                                                 0x4
#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT                                                            0x5
#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT                                                            0x6
#define APML_STATUS__APML_Corr_MASK                                                                           0x00000001L
#define APML_STATUS__APML_NonFatal_MASK                                                                       0x00000002L
#define APML_STATUS__APML_Fatal_MASK                                                                          0x00000004L
#define APML_STATUS__APML_Serr_MASK                                                                           0x00000008L
#define APML_STATUS__APML_IntPoisonErr_MASK                                                                   0x00000010L
#define APML_STATUS__APML_EgressPoisonErrLo_MASK                                                              0x00000020L
#define APML_STATUS__APML_EgressPoisonErrHi_MASK                                                              0x00000040L
//APML_CONTROL
#define APML_CONTROL__APML_NMI_En__SHIFT                                                                      0x0
#define APML_CONTROL__APML_SyncFlood_En__SHIFT                                                                0x1
#define APML_CONTROL__APML_OutputDis__SHIFT                                                                   0x8
#define APML_CONTROL__APML_NMI_En_MASK                                                                        0x00000001L
#define APML_CONTROL__APML_SyncFlood_En_MASK                                                                  0x00000002L
#define APML_CONTROL__APML_OutputDis_MASK                                                                     0x00000100L
//APML_TRIGGER
#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT                                                                 0x0
#define APML_TRIGGER__APML_NMI_TRIGGER_MASK                                                                   0x00000001L


// addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec
//PSP_INTERNAL_POISON_STATUS
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT                                               0x0
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT                                               0x1
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT                                               0x2
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT                                               0x3
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT                                               0x4
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT                                               0x5
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT                                               0x6
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT                                               0x7
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK                                                 0x00000001L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK                                                 0x00000002L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK                                                 0x00000004L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK                                                 0x00000008L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK                                                 0x00000010L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK                                                 0x00000020L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK                                                 0x00000040L
#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK                                                 0x00000080L
//PSP_EGRESS_POISON_STATUS_LO
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT                                         0x0
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT                                         0x1
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT                                         0x2
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT                                         0x3
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT                                         0x4
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT                                         0x5
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT                                         0x6
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT                                         0x7
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT                                         0x8
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT                                         0x9
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT                                        0xa
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT                                        0xb
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT                                        0xc
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT                                        0xd
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT                                        0xe
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT                                        0xf
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT                                        0x10
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT                                        0x11
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT                                        0x12
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT                                        0x13
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT                                        0x14
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT                                        0x15
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT                                        0x16
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT                                        0x17
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT                                        0x18
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT                                        0x19
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT                                        0x1a
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT                                        0x1b
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT                                        0x1c
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT                                        0x1d
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT                                        0x1e
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT                                        0x1f
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK                                           0x00000001L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK                                           0x00000002L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK                                           0x00000004L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK                                           0x00000008L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK                                           0x00000010L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK                                           0x00000020L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK                                           0x00000040L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK                                           0x00000080L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK                                           0x00000100L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK                                           0x00000200L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK                                          0x00000400L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK                                          0x00000800L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK                                          0x00001000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK                                          0x00002000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK                                          0x00004000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK                                          0x00008000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK                                          0x00010000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK                                          0x00020000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK                                          0x00040000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK                                          0x00080000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK                                          0x00100000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK                                          0x00200000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK                                          0x00400000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK                                          0x00800000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK                                          0x01000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK                                          0x02000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK                                          0x04000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK                                          0x08000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK                                          0x10000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK                                          0x20000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK                                          0x40000000L
#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK                                          0x80000000L
//PSP_EGRESS_POISON_STATUS_HI
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT                                         0x0
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT                                         0x1
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT                                         0x2
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT                                         0x3
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT                                         0x4
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT                                         0x5
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT                                         0x6
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT                                         0x7
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT                                         0x8
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT                                         0x9
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT                                        0xa
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT                                        0xb
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT                                        0xc
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT                                        0xd
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT                                        0xe
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT                                        0xf
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT                                        0x10
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT                                        0x11
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT                                        0x12
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT                                        0x13
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT                                        0x14
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT                                        0x15
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT                                        0x16
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT                                        0x17
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT                                        0x18
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT                                        0x19
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT                                        0x1a
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT                                        0x1b
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT                                        0x1c
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT                                        0x1d
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT                                        0x1e
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT                                        0x1f
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK                                           0x00000001L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK                                           0x00000002L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK                                           0x00000004L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK                                           0x00000008L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK                                           0x00000010L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK                                           0x00000020L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK                                           0x00000040L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK                                           0x00000080L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK                                           0x00000100L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK                                           0x00000200L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK                                          0x00000400L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK                                          0x00000800L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK                                          0x00001000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK                                          0x00002000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK                                          0x00004000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK                                          0x00008000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK                                          0x00010000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK                                          0x00020000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK                                          0x00040000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK                                          0x00080000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK                                          0x00100000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK                                          0x00200000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK                                          0x00400000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK                                          0x00800000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK                                          0x01000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK                                          0x02000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK                                          0x04000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK                                          0x08000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK                                          0x10000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK                                          0x20000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK                                          0x40000000L
#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK                                          0x80000000L


// addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp
//NB_INTSBDEVINDCFG0_STEERING_CNTL
#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT                                                0x0
#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT                                                0x8
#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK                                                  0x00000001L
#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK                                                  0x0000FF00L
//NB_INTSBDEVINDCFG0_SW_LATENCY
#define NB_INTSBDEVINDCFG0_SW_LATENCY__SwitchLatency__SHIFT                                                   0x0
#define NB_INTSBDEVINDCFG0_SW_LATENCY__SwitchLatency_MASK                                                     0x000003FFL


// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec
//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX
#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT                                               0x0
#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK                                                 0xFFFFFFFFL
//NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA
#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT                                                 0x0
#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec
//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX
#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT                                               0x0
#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK                                                 0xFFFFFFFFL
//NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA
#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT                                                 0x0
#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec
//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX
#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT                                               0x0
#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK                                                 0xFFFFFFFFL
//NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA
#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT                                                 0x0
#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_iohub_iommu_l2a_l2acfg
//L2_PERF_CNTL_0
#define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT                                                                   0x0
#define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT                                                                   0x8
#define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT                                                              0x10
#define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT                                                              0x18
#define L2_PERF_CNTL_0__L2PerfEvent0_MASK                                                                     0x000000FFL
#define L2_PERF_CNTL_0__L2PerfEvent1_MASK                                                                     0x0000FF00L
#define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK                                                                0x00FF0000L
#define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK                                                                0xFF000000L
//L2_PERF_COUNT_0
#define L2_PERF_COUNT_0__L2PerfCount0__SHIFT                                                                  0x0
#define L2_PERF_COUNT_0__L2PerfCount0_MASK                                                                    0xFFFFFFFFL
//L2_PERF_COUNT_1
#define L2_PERF_COUNT_1__L2PerfCount1__SHIFT                                                                  0x0
#define L2_PERF_COUNT_1__L2PerfCount1_MASK                                                                    0xFFFFFFFFL
//L2_PERF_CNTL_1
#define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT                                                                   0x0
#define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT                                                                   0x8
#define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT                                                              0x10
#define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT                                                              0x18
#define L2_PERF_CNTL_1__L2PerfEvent2_MASK                                                                     0x000000FFL
#define L2_PERF_CNTL_1__L2PerfEvent3_MASK                                                                     0x0000FF00L
#define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK                                                                0x00FF0000L
#define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK                                                                0xFF000000L
//L2_PERF_COUNT_2
#define L2_PERF_COUNT_2__L2PerfCount2__SHIFT                                                                  0x0
#define L2_PERF_COUNT_2__L2PerfCount2_MASK                                                                    0xFFFFFFFFL
//L2_PERF_COUNT_3
#define L2_PERF_COUNT_3__L2PerfCount3__SHIFT                                                                  0x0
#define L2_PERF_COUNT_3__L2PerfCount3_MASK                                                                    0xFFFFFFFFL
//L2_STATUS_0
#define L2_STATUS_0__L2STATUS0__SHIFT                                                                         0x0
#define L2_STATUS_0__L2STATUS0_MASK                                                                           0xFFFFFFFFL
//L2_CONTROL_0
#define L2_CONTROL_0__AllowL1CacheVZero__SHIFT                                                                0x1
#define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT                                                               0x2
#define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT                                                              0x3
#define L2_CONTROL_0__L1CacheATSRsp_Enable__SHIFT                                                             0x4
#define L2_CONTROL_0__L1CacheATSRsp_L1ID__SHIFT                                                               0x5
#define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT                                                             0xa
#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT                                                           0xb
#define L2_CONTROL_0__Allow_nonats_u_bit__SHIFT                                                               0xc
#define L2_CONTROL_0__DTE_I_MASK_ENABLE__SHIFT                                                                0xd
#define L2_CONTROL_0__DTE_I_MASK_L1ID__SHIFT                                                                  0xe
#define L2_CONTROL_0__FLTCMBPriority__SHIFT                                                                   0x12
#define L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT                                                       0x13
#define L2_CONTROL_0__IFifoBurstLength__SHIFT                                                                 0x14
#define L2_CONTROL_0__IFifoClientPriority__SHIFT                                                              0x18
#define L2_CONTROL_0__AllowL1CacheVZero_MASK                                                                  0x00000002L
#define L2_CONTROL_0__AllowL1CacheATSRsp_MASK                                                                 0x00000004L
#define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK                                                                0x00000008L
#define L2_CONTROL_0__L1CacheATSRsp_Enable_MASK                                                               0x00000010L
#define L2_CONTROL_0__L1CacheATSRsp_L1ID_MASK                                                                 0x000000E0L
#define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK                                                               0x00000400L
#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK                                                             0x00000800L
#define L2_CONTROL_0__Allow_nonats_u_bit_MASK                                                                 0x00001000L
#define L2_CONTROL_0__DTE_I_MASK_ENABLE_MASK                                                                  0x00002000L
#define L2_CONTROL_0__DTE_I_MASK_L1ID_MASK                                                                    0x0001C000L
#define L2_CONTROL_0__FLTCMBPriority_MASK                                                                     0x00040000L
#define L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK                                                         0x00080000L
#define L2_CONTROL_0__IFifoBurstLength_MASK                                                                   0x00F00000L
#define L2_CONTROL_0__IFifoClientPriority_MASK                                                                0xFF000000L
//L2_CONTROL_1
#define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT                                                              0x0
#define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT                                                            0x8
#define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT                                                               0x10
#define L2_CONTROL_1__PerfThreshold__SHIFT                                                                    0x18
#define L2_CONTROL_1__SeqInvBurstLimitInv_MASK                                                                0x000000FFL
#define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK                                                              0x0000FF00L
#define L2_CONTROL_1__SeqInvBurstLimitEn_MASK                                                                 0x00010000L
#define L2_CONTROL_1__PerfThreshold_MASK                                                                      0xFF000000L
//L2_DTC_CONTROL
#define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT                                                                0x3
#define L2_DTC_CONTROL__DTCParityEn__SHIFT                                                                    0x4
#define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT                                                             0x8
#define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT                                                              0xa
#define L2_DTC_CONTROL__DTCBypass__SHIFT                                                                      0xd
#define L2_DTC_CONTROL__DTCParitySupport__SHIFT                                                               0xf
#define L2_DTC_CONTROL__DTCWays__SHIFT                                                                        0x10
#define L2_DTC_CONTROL__DTCEntries__SHIFT                                                                     0x1c
#define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK                                                                  0x00000008L
#define L2_DTC_CONTROL__DTCParityEn_MASK                                                                      0x00000010L
#define L2_DTC_CONTROL__DTCInvalidationSel_MASK                                                               0x00000300L
#define L2_DTC_CONTROL__DTCSoftInvalidate_MASK                                                                0x00000400L
#define L2_DTC_CONTROL__DTCBypass_MASK                                                                        0x00002000L
#define L2_DTC_CONTROL__DTCParitySupport_MASK                                                                 0x00008000L
#define L2_DTC_CONTROL__DTCWays_MASK                                                                          0x00FF0000L
#define L2_DTC_CONTROL__DTCEntries_MASK                                                                       0xF0000000L
//L2_DTC_HASH_CONTROL
#define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT                                                            0x10
#define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK                                                              0xFFFF0000L
//L2_DTC_WAY_CONTROL
#define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT                                                              0x0
#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT                                                        0x10
#define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK                                                                0x0000FFFFL
#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK                                                          0xFFFF0000L
//L2_ITC_CONTROL
#define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT                                                                0x3
#define L2_ITC_CONTROL__ITCParityEn__SHIFT                                                                    0x4
#define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT                                                             0x8
#define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT                                                              0xa
#define L2_ITC_CONTROL__ITCBypass__SHIFT                                                                      0xd
#define L2_ITC_CONTROL__ITCParitySupport__SHIFT                                                               0xf
#define L2_ITC_CONTROL__ITCWays__SHIFT                                                                        0x10
#define L2_ITC_CONTROL__ITCEntries__SHIFT                                                                     0x1c
#define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK                                                                  0x00000008L
#define L2_ITC_CONTROL__ITCParityEn_MASK                                                                      0x00000010L
#define L2_ITC_CONTROL__ITCInvalidationSel_MASK                                                               0x00000300L
#define L2_ITC_CONTROL__ITCSoftInvalidate_MASK                                                                0x00000400L
#define L2_ITC_CONTROL__ITCBypass_MASK                                                                        0x00002000L
#define L2_ITC_CONTROL__ITCParitySupport_MASK                                                                 0x00008000L
#define L2_ITC_CONTROL__ITCWays_MASK                                                                          0x00FF0000L
#define L2_ITC_CONTROL__ITCEntries_MASK                                                                       0xF0000000L
//L2_ITC_HASH_CONTROL
#define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT                                                            0x10
#define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK                                                              0xFFFF0000L
//L2_ITC_WAY_CONTROL
#define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT                                                              0x0
#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT                                                        0x10
#define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK                                                                0x0000FFFFL
#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK                                                          0xFFFF0000L
//L2_PTC_A_CONTROL
#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT                                                     0x1
#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT                                                   0x2
#define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT                                                             0x3
#define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT                                                                 0x4
#define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT                                                          0x8
#define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT                                                           0xa
#define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT                                                                   0xb
#define L2_PTC_A_CONTROL__PTCABypass__SHIFT                                                                   0xd
#define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT                                                            0xf
#define L2_PTC_A_CONTROL__PTCAWays__SHIFT                                                                     0x10
#define L2_PTC_A_CONTROL__PTCAEntries__SHIFT                                                                  0x1c
#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK                                                       0x00000002L
#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK                                                     0x00000004L
#define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK                                                               0x00000008L
#define L2_PTC_A_CONTROL__PTCAParityEn_MASK                                                                   0x00000010L
#define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK                                                            0x00000300L
#define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK                                                             0x00000400L
#define L2_PTC_A_CONTROL__PTCA2MMode_MASK                                                                     0x00000800L
#define L2_PTC_A_CONTROL__PTCABypass_MASK                                                                     0x00002000L
#define L2_PTC_A_CONTROL__PTCAParitySupport_MASK                                                              0x00008000L
#define L2_PTC_A_CONTROL__PTCAWays_MASK                                                                       0x00FF0000L
#define L2_PTC_A_CONTROL__PTCAEntries_MASK                                                                    0xF0000000L
//L2_PTC_A_HASH_CONTROL
#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT                                                         0x10
#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK                                                           0xFFFF0000L
//L2_PTC_A_WAY_CONTROL
#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT                                                           0x0
#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT                                                     0x10
#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK                                                             0x0000FFFFL
#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK                                                       0xFFFF0000L
//L2_CREDIT_CONTROL_2
#define L2_CREDIT_CONTROL_2__QUEUECredits__SHIFT                                                              0x0
#define L2_CREDIT_CONTROL_2__QUEUEOverride__SHIFT                                                             0x7
#define L2_CREDIT_CONTROL_2__FLTCMBCredits__SHIFT                                                             0x8
#define L2_CREDIT_CONTROL_2__FLTCMBOverride__SHIFT                                                            0xf
#define L2_CREDIT_CONTROL_2__FCELCredits__SHIFT                                                               0x10
#define L2_CREDIT_CONTROL_2__FCELOverride__SHIFT                                                              0x17
#define L2_CREDIT_CONTROL_2__PPR_logger_credits__SHIFT                                                        0x18
#define L2_CREDIT_CONTROL_2__QUEUECredits_MASK                                                                0x0000003FL
#define L2_CREDIT_CONTROL_2__QUEUEOverride_MASK                                                               0x00000080L
#define L2_CREDIT_CONTROL_2__FLTCMBCredits_MASK                                                               0x00003F00L
#define L2_CREDIT_CONTROL_2__FLTCMBOverride_MASK                                                              0x00008000L
#define L2_CREDIT_CONTROL_2__FCELCredits_MASK                                                                 0x003F0000L
#define L2_CREDIT_CONTROL_2__FCELOverride_MASK                                                                0x00800000L
#define L2_CREDIT_CONTROL_2__PPR_logger_credits_MASK                                                          0x0F000000L
//L2A_UPDATE_FILTER_CNTL
#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT                                               0x0
#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT                                            0x1
#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK                                                 0x00000001L
#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK                                              0x0000001EL
//L2_ERR_RULE_CONTROL_3
#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT                                                            0x0
#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT                                                         0x4
#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK                                                              0x00000001L
#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK                                                           0xFFFFFFF0L
//L2_ERR_RULE_CONTROL_4
#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT                                                         0x0
#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK                                                           0xFFFFFFFFL
//L2_ERR_RULE_CONTROL_5
#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT                                                         0x0
#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK                                                           0xFFFFFFFFL
//L2_L2A_PGSIZE_CONTROL
#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT                                                       0x0
#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT                                                      0x8
#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT                                                     0x11
#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK                                                         0x0000007FL
#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK                                                        0x00007F00L
#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK                                                       0x000E0000L
//L2_L2A_MEMPWR_GATE_1
#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN__SHIFT                                                             0x0
#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN__SHIFT                                                             0x1
#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN__SHIFT                                                             0x2
#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL__SHIFT                                                   0x4
#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN_MASK                                                               0x00000001L
#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN_MASK                                                               0x00000002L
#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN_MASK                                                               0x00000004L
#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL_MASK                                                     0x00000010L
//L2_L2A_MEMPWR_GATE_2
#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres__SHIFT                                                          0x0
#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres_MASK                                                            0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_3
#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres__SHIFT                                                          0x0
#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres_MASK                                                            0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_4
#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres__SHIFT                                                          0x0
#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres_MASK                                                            0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_5
#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt__SHIFT                                               0x0
#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt_MASK                                                 0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_6
#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt__SHIFT                                              0x0
#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt_MASK                                                0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_7
#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt__SHIFT                                               0x0
#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt_MASK                                                 0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_8
#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt__SHIFT                                              0x0
#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt_MASK                                                0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_9
#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt__SHIFT                                               0x0
#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt_MASK                                                 0xFFFFFFFFL
//L2_L2A_MEMPWR_GATE_10
#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt__SHIFT                                             0x0
#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt_MASK                                               0xFFFFFFFFL
//L2_ECO_CNTRL_0
#define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT                                                                       0x0
#define L2_ECO_CNTRL_0__L2_ECO_0_MASK                                                                         0xFFFFFFFFL


// addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec
//FEATURES_ENABLE
#define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT                                                              0x2
#define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT                                                          0x4
#define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT                                                           0x5
#define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT                                                         0x8
#define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT                                                            0x9
#define FEATURES_ENABLE__Ioapic_id_ext_en_MASK                                                                0x00000004L
#define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK                                                            0x00000010L
#define FEATURES_ENABLE__Ioapic_secondary_en_MASK                                                             0x00000020L
#define FEATURES_ENABLE__Ioapic_processor_mode_MASK                                                           0x00000100L
#define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK                                                              0x00000200L


// addressBlock: nbio_pcie0_pciedir
//PCIE_USB4_TXAL_CNTL1
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TX_CREDITS__SHIFT                                                      0x0
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_PERST_EN__SHIFT                                      0x8
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_IGNORE_PERST_ON_PE__SHIFT                                         0x9
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_SAVE_OS_DATA__SHIFT                                               0xa
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP2_EN__SHIFT                                                   0xb
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_CLKSW_WAIT_EN__SHIFT                                              0xc
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_PRELOAD_FIX_DIS__SHIFT                                            0xd
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_RESET__SHIFT                                         0x10
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TEARDOWN_FIX_DIS__SHIFT                                           0x11
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_WAIT_FOR_TXAL_FLUSH_DIS__SHIFT                                         0x12
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP_REQ_HOLD_OLD__SHIFT                                          0x13
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_HP_HALT_FIX_DIS__SHIFT                                                 0x14
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_FLUSH_DISC_DIS__SHIFT                                             0x15
#define PCIE_USB4_TXAL_CNTL1__TXAL_REQ_DROP_ON_RESET_DIS__SHIFT                                               0x16
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TPI_FLUSH_DIS__SHIFT                                              0x17
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TX_CREDITS_MASK                                                        0x000000FFL
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_PERST_EN_MASK                                        0x00000100L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_IGNORE_PERST_ON_PE_MASK                                           0x00000200L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_SAVE_OS_DATA_MASK                                                 0x00000400L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP2_EN_MASK                                                     0x00000800L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_CLKSW_WAIT_EN_MASK                                                0x00001000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_PRELOAD_FIX_DIS_MASK                                              0x00002000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_REQ_FLUSH_ON_RESET_MASK                                           0x00010000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TEARDOWN_FIX_DIS_MASK                                             0x00020000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_WAIT_FOR_TXAL_FLUSH_DIS_MASK                                           0x00040000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_DLLP_REQ_HOLD_OLD_MASK                                            0x00080000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_HP_HALT_FIX_DIS_MASK                                                   0x00100000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_FLUSH_DISC_DIS_MASK                                               0x00200000L
#define PCIE_USB4_TXAL_CNTL1__TXAL_REQ_DROP_ON_RESET_DIS_MASK                                                 0x00400000L
#define PCIE_USB4_TXAL_CNTL1__PCIE_USB_TXAL_TPI_FLUSH_DIS_MASK                                                0x00800000L
//PCIE_USB4_RXAL_CNTL1
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP_TLP_DECODE_EN__SHIFT                                         0x0
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_EMPTY_EN__SHIFT                                         0x1
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_IDLE_EN__SHIFT                                          0x2
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_TPI_RESET__SHIFT                                    0x3
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_PATH_ENABLE__SHIFT                                  0x4
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_CHK_PASS__SHIFT                                             0x8
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_SUPPID_PASS__SHIFT                                          0x9
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_PDF_PASS__SHIFT                                             0xa
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_LEN_PASS__SHIFT                                             0xb
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP2_EN__SHIFT                                                   0xc
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_PDF_ERR_EN__SHIFT                                                 0xd
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FLUSH_ON_PE_EN__SHIFT                                             0xe
#define PCIE_USB4_RXAL_CNTL1__USB_62_164_FIX_DIS__SHIFT                                                       0xf
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP_TLP_DECODE_EN_MASK                                           0x00000001L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_EMPTY_EN_MASK                                           0x00000002L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXEI_WAIT_RXAL_IDLE_EN_MASK                                            0x00000004L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_TPI_RESET_MASK                                      0x00000008L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_IDLE_WAIT_FOR_PATH_ENABLE_MASK                                    0x00000010L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_CHK_PASS_MASK                                               0x00000100L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_SUPPID_PASS_MASK                                            0x00000200L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_PDF_PASS_MASK                                               0x00000400L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FORCE_LEN_PASS_MASK                                               0x00000800L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_DLLP2_EN_MASK                                                     0x00001000L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_PDF_ERR_EN_MASK                                                   0x00002000L
#define PCIE_USB4_RXAL_CNTL1__PCIE_USB_RXAL_FLUSH_ON_PE_EN_MASK                                               0x00004000L
#define PCIE_USB4_RXAL_CNTL1__USB_62_164_FIX_DIS_MASK                                                         0x00008000L
//PCIE_USB4_AL_CNTL1
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_IDLE_IGNORE_EN__SHIFT                                           0x2
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_IDLE_IGNORE_EN__SHIFT                                           0x3
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_IDLE_IGNORE_EN__SHIFT                                             0x4
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_GATE_EN__SHIFT                                                  0x5
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_GATE_EN__SHIFT                                                  0x6
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_GATE_EN__SHIFT                                                    0x7
#define PCIE_USB4_AL_CNTL1__PCIE_USB_IGNORE_HW_PATH_ENABLE__SHIFT                                             0x9
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_IGNORE_CLK_SWITCH_EN__SHIFT                                           0xa
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_OVERRIDE_EN__SHIFT                                                 0xb
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_PCIE_CIO_RST_REQ_VALUE__SHIFT                                      0xc
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_CIO_PCIE_RST_RDY_VALUE__SHIFT                                      0xd
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_READY_VALUE__SHIFT                                                 0xe
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_PATH_EN_DIS__SHIFT                                              0xf
#define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_OVERRIDE_EN__SHIFT                                                 0x10
#define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_BLOCK_IN_TUNNEL_DISABLE_EN__SHIFT                                  0x11
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_DISC_IN_SLEEP__SHIFT                                               0x12
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_L23__SHIFT                                                   0x13
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_PE_DIS__SHIFT                                                0x14
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_TXCLK_UNGATE_DIS__SHIFT                                               0x15
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_RECONFIG_ON_PE__SHIFT                                              0x17
#define PCIE_USB4_AL_CNTL1__PCIE_USB_FORCE_AL_RECONFIG_ACK__SHIFT                                             0x18
#define PCIE_USB4_AL_CNTL1__PCIE_USB_RECONFIG_IGNORE_AL__SHIFT                                                0x19
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_RECONFIG_EN__SHIFT                                              0x1a
#define PCIE_USB4_AL_CNTL1__PCIE_USB_PARTIAL_DISC_EN__SHIFT                                                   0x1b
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_LOW_CHECK_DIS__SHIFT                                            0x1c
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_MNTR_WAKE_REQ_DIS__SHIFT                                              0x1d
#define PCIE_USB4_AL_CNTL1__PCIE_USB_BYPASS_PCS_HOLD__SHIFT                                                   0x1e
#define PCIE_USB4_AL_CNTL1__PCIE_CIO_PART_CONN_EN__SHIFT                                                      0x1f
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_IDLE_IGNORE_EN_MASK                                             0x00000004L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_IDLE_IGNORE_EN_MASK                                             0x00000008L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_IDLE_IGNORE_EN_MASK                                               0x00000010L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_TXAL_GATE_EN_MASK                                                    0x00000020L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_RXAL_GATE_EN_MASK                                                    0x00000040L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_Z10_AL_GATE_EN_MASK                                                      0x00000080L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_IGNORE_HW_PATH_ENABLE_MASK                                               0x00000200L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_IGNORE_CLK_SWITCH_EN_MASK                                             0x00000400L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_OVERRIDE_EN_MASK                                                   0x00000800L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_PCIE_CIO_RST_REQ_VALUE_MASK                                        0x00001000L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_CIO_PCIE_RST_RDY_VALUE_MASK                                        0x00002000L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_READY_VALUE_MASK                                                   0x00004000L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_PATH_EN_DIS_MASK                                                0x00008000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_OVERRIDE_EN_MASK                                                   0x00010000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_HW_PE_BLOCK_IN_TUNNEL_DISABLE_EN_MASK                                    0x00020000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_DISC_IN_SLEEP_MASK                                                 0x00040000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_L23_MASK                                                     0x00080000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_PG_IN_PE_DIS_MASK                                                  0x00100000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_TXCLK_UNGATE_DIS_MASK                                                 0x00200000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_ALLOW_RECONFIG_ON_PE_MASK                                                0x00800000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_FORCE_AL_RECONFIG_ACK_MASK                                               0x01000000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_RECONFIG_IGNORE_AL_MASK                                                  0x02000000L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_RECONFIG_EN_MASK                                                0x04000000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_PARTIAL_DISC_EN_MASK                                                     0x08000000L
#define PCIE_USB4_AL_CNTL1__PCIE_TPI_RESET_ON_LOW_CHECK_DIS_MASK                                              0x10000000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_AL_MNTR_WAKE_REQ_DIS_MASK                                                0x20000000L
#define PCIE_USB4_AL_CNTL1__PCIE_USB_BYPASS_PCS_HOLD_MASK                                                     0x40000000L
#define PCIE_USB4_AL_CNTL1__PCIE_CIO_PART_CONN_EN_MASK                                                        0x80000000L
//PCIE_USB4_AL_CNTL2
#define PCIE_USB4_AL_CNTL2__PCIE_USB_AL_PG_IGNORE_SIDEBAND__SHIFT                                             0x0
#define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_HT_CHECK_AL_DIS__SHIFT                                                0x8
#define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_IGNORE_HT__SHIFT                                                      0x9
#define PCIE_USB4_AL_CNTL2__PCIE_AL_TPI_RESET_HANDSHAKE_DIS__SHIFT                                            0xa
#define PCIE_USB4_AL_CNTL2__PCIE_AL_RXAL_RESET_HANDSHAKE_DIS__SHIFT                                           0xb
#define PCIE_USB4_AL_CNTL2__PCIE_AL_TXAL_RESET_HANDSHAKE_DIS__SHIFT                                           0xc
#define PCIE_USB4_AL_CNTL2__PCIE_TPI_RESET_BLOCK_TXAL_EN__SHIFT                                               0xe
#define PCIE_USB4_AL_CNTL2__PCIE_TXAL_LOCAL_RESET_EN__SHIFT                                                   0xf
#define PCIE_USB4_AL_CNTL2__PCIE_TXAL_PERST_INACT_INIT_BY_TPIRST_EN__SHIFT                                    0x10
#define PCIE_USB4_AL_CNTL2__PCIE_USB4_ALL_CLKREQ_IDLE_NODELAY_AL_TEARDOWN_COMPLETE_EN__SHIFT                  0x11
#define PCIE_USB4_AL_CNTL2__PCIE_USB_AL_PG_IGNORE_SIDEBAND_MASK                                               0x000000FFL
#define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_HT_CHECK_AL_DIS_MASK                                                  0x00000100L
#define PCIE_USB4_AL_CNTL2__PCIE_USB_PG_IGNORE_HT_MASK                                                        0x00000200L
#define PCIE_USB4_AL_CNTL2__PCIE_AL_TPI_RESET_HANDSHAKE_DIS_MASK                                              0x00000400L
#define PCIE_USB4_AL_CNTL2__PCIE_AL_RXAL_RESET_HANDSHAKE_DIS_MASK                                             0x00000800L
#define PCIE_USB4_AL_CNTL2__PCIE_AL_TXAL_RESET_HANDSHAKE_DIS_MASK                                             0x00001000L
#define PCIE_USB4_AL_CNTL2__PCIE_TPI_RESET_BLOCK_TXAL_EN_MASK                                                 0x00004000L
#define PCIE_USB4_AL_CNTL2__PCIE_TXAL_LOCAL_RESET_EN_MASK                                                     0x00008000L
#define PCIE_USB4_AL_CNTL2__PCIE_TXAL_PERST_INACT_INIT_BY_TPIRST_EN_MASK                                      0x00010000L
#define PCIE_USB4_AL_CNTL2__PCIE_USB4_ALL_CLKREQ_IDLE_NODELAY_AL_TEARDOWN_COMPLETE_EN_MASK                    0x00020000L
//PCIE_USB4_AL_HYSTERESIS
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_RESET_HYSTERESIS__SHIFT                                             0x0
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_INIT_HYSTERESIS__SHIFT                                              0x8
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_TEARDOWN_HYSTERESIS__SHIFT                                          0x10
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_RESET_HYSTERESIS_MASK                                               0x000000FFL
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_INIT_HYSTERESIS_MASK                                                0x0000FF00L
#define PCIE_USB4_AL_HYSTERESIS__PCIE_CIO_TEARDOWN_HYSTERESIS_MASK                                            0x00FF0000L
//PCIE_USB4_AL_HYSTERESIS_2
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_RESET_HYSTERESIS__SHIFT                                      0x8
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_TXAL_IDLE_HYSTERESIS__SHIFT                                       0x10
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_IDLE_HYSTERESIS__SHIFT                                       0x18
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_RESET_HYSTERESIS_MASK                                        0x0000FF00L
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_TXAL_IDLE_HYSTERESIS_MASK                                         0x00FF0000L
#define PCIE_USB4_AL_HYSTERESIS_2__PCIE_USB_RXAL_IDLE_HYSTERESIS_MASK                                         0xFF000000L
//PCIE_USB4_ERR_CNTL5
#define PCIE_USB4_ERR_CNTL5__PCIE_USB_RXAL_ERR_RECORD_MODE__SHIFT                                             0x0
#define PCIE_USB4_ERR_CNTL5__PCIE_USB_RXAL_ERR_RECORD_MODE_MASK                                               0x00000001L
//PCIE_USB4_LC_CNTL1
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE__SHIFT                                            0x0
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE_MASK                                              0x00000001L
//BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK                                    0x00000001L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK                                   0x00000002L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK                                  0x00000020L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK                                  0x00000040L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK                                  0x00000080L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK                                 0x00000100L
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK                                            0x00010000L
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK                                  0x00000001L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK                               0x00000008L
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT                     0x8
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT                     0x9
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT                          0xb
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT                     0xd
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT                            0xf
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT                          0x10
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT                          0x11
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT                     0x14
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT                     0x15
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT                             0x18
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                       0x19
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT                0x1b
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT                0x1c
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT                  0x1e
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK                       0x00000100L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK                       0x00000600L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK                            0x00001800L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK                       0x00006000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK                              0x00008000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK                            0x00010000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK                            0x000E0000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK                       0x00100000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK                       0x00E00000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK                               0x01000000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                         0x06000000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK                  0x08000000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK                  0x30000000L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK                    0xC0000000L

// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
//BIF_CFG_DEV0_RC0_VENDOR_ID
#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV0_RC0_DEVICE_ID
#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV0_RC0_COMMAND
#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
//BIF_CFG_DEV0_RC0_STATUS
#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
//BIF_CFG_DEV0_RC0_REVISION_ID
#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
//BIF_CFG_DEV0_RC0_PROG_INTERFACE
#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
//BIF_CFG_DEV0_RC0_SUB_CLASS
#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
//BIF_CFG_DEV0_RC0_BASE_CLASS
#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
//BIF_CFG_DEV0_RC0_CACHE_LINE
#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
//BIF_CFG_DEV0_RC0_LATENCY
#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
//BIF_CFG_DEV0_RC0_HEADER
#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
//BIF_CFG_DEV0_RC0_BIST
#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
//BIF_CFG_DEV0_RC0_BASE_ADDR_1
#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_BASE_ADDR_2
#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
//BIF_CFG_DEV0_RC0_SECONDARY_STATUS
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER
#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER
#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_RC0_CAP_PTR
#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_INTERRUPT_LINE
#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
//BIF_CFG_DEV0_RC0_INTERRUPT_PIN
#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
//BIF_CFG_DEV0_RC0_PMI_CAP_LIST
#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV0_RC0_PMI_CAP
#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_RC0_PCIE_CAP
#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
//BIF_CFG_DEV0_RC0_DEVICE_CAP
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
//BIF_CFG_DEV0_RC0_DEVICE_CNTL
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
//BIF_CFG_DEV0_RC0_DEVICE_STATUS
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
//BIF_CFG_DEV0_RC0_LINK_CAP
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
//BIF_CFG_DEV0_RC0_LINK_CNTL
#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                       0x2
#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                         0x0004L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
//BIF_CFG_DEV0_RC0_LINK_STATUS
#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
//BIF_CFG_DEV0_RC0_SLOT_CAP
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
//BIF_CFG_DEV0_RC0_SLOT_CNTL
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
//BIF_CFG_DEV0_RC0_SLOT_STATUS
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
//BIF_CFG_DEV0_RC0_ROOT_CNTL
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
//BIF_CFG_DEV0_RC0_ROOT_CAP
#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
//BIF_CFG_DEV0_RC0_ROOT_STATUS
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
//BIF_CFG_DEV0_RC0_DEVICE_CAP2
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
//BIF_CFG_DEV0_RC0_DEVICE_CNTL2
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
//BIF_CFG_DEV0_RC0_DEVICE_STATUS2
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
//BIF_CFG_DEV0_RC0_LINK_CAP2
#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                           0x9
#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                             0x0000FE00L
#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
//BIF_CFG_DEV0_RC0_LINK_CNTL2
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
//BIF_CFG_DEV0_RC0_LINK_STATUS2
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
//BIF_CFG_DEV0_RC0_SLOT_CAP2
#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_SLOT_CNTL2
#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
//BIF_CFG_DEV0_RC0_SLOT_STATUS2
#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_RC0_MSI_CAP_LIST
#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_MSI_MSG_DATA
#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
//BIF_CFG_DEV0_RC0_SSID_CAP_LIST
#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV0_RC0_SSID_CAP
#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
//BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_RC0_MSI_MAP_CAP
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                           0x5
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                            0x6
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                             0x00000020L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                              0x00000040L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                      0x9
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                        0x0000FE00L
//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_RC0_LINK_CAP_16GT
#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV0_RC0_RTR_DATA1
#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT                                                         0x0
#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT                                                          0xc
#define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID__SHIFT                                                              0x1f
#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK                                                           0x00000FFFL
#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK                                                            0x00FFF000L
#define BIF_CFG_DEV0_RC0_RTR_DATA1__VALID_MASK                                                                0x80000000L
//BIF_CFG_DEV0_RC0_RTR_DATA2
#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT                                                           0x0
#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK                                                             0x00000FFFL
#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK                                                         0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_COMMAND
#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF0_0_STATUS
#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF0_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_0_LATENCY
#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_0_HEADER
#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_0_BIST
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_0_PMI_CAP
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF0_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                     0x0000FE00L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                   0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                     0x0080L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF0_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_COMMAND
#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF1_0_STATUS
#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF1_0_REVISION_ID
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF1_0_LATENCY
#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_0_HEADER
#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF1_0_BIST
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_CAP_PTR
#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_0_PMI_CAP
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF1_0_LINK_CAP
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MASK
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                     0x0000FE00L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                   0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                     0x0080L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
//BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF1_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
//BIF_CFG_DEV0_EPF2_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF2_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF2_0_COMMAND
#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF2_0_STATUS
#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF2_0_REVISION_ID
#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF2_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF2_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF2_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF2_0_LATENCY
#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF2_0_HEADER
#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF2_0_BIST
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_CAP_PTR
#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF2_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF2_0_PMI_CAP
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF2_0_SBRN
#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF2_0_FLADJ
#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF2_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF2_0_LINK_CAP
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF2_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF2_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF2_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_MASK
#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF2_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF2_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF2_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF2_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF2_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
//BIF_CFG_DEV0_EPF3_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF3_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF3_0_COMMAND
#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF3_0_STATUS
#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF3_0_REVISION_ID
#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF3_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF3_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF3_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF3_0_LATENCY
#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF3_0_HEADER
#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF3_0_BIST
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_CAP_PTR
#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF3_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF3_0_PMI_CAP
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF3_0_SBRN
#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF3_0_FLADJ
#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF3_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF3_0_LINK_CAP
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF3_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF3_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF3_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_MASK
#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF3_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF3_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF3_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF3_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF3_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
//BIF_CFG_DEV0_EPF4_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF4_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF4_0_COMMAND
#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF4_0_STATUS
#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF4_0_REVISION_ID
#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF4_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF4_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF4_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF4_0_LATENCY
#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF4_0_HEADER
#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF4_0_BIST
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_CAP_PTR
#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF4_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF4_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF4_0_PMI_CAP
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF4_0_SBRN
#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF4_0_FLADJ
#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF4_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF4_0_LINK_CAP
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF4_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF4_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF4_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF4_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF4_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_MASK
#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF4_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF4_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF4_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF4_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF4_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF4_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF4_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
//BIF_CFG_DEV0_EPF5_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF5_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF5_0_COMMAND
#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF5_0_STATUS
#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF5_0_REVISION_ID
#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF5_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF5_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF5_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF5_0_LATENCY
#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF5_0_HEADER
#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF5_0_BIST
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_CAP_PTR
#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF5_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF5_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF5_0_PMI_CAP
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF5_0_SBRN
#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF5_0_FLADJ
#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF5_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF5_0_LINK_CAP
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF5_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF5_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF5_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF5_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF5_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_MASK
#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF5_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF5_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF5_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF5_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF5_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF5_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF5_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
//BIF_CFG_DEV0_EPF6_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF6_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF6_0_COMMAND
#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF6_0_STATUS
#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF6_0_REVISION_ID
#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF6_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF6_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF6_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF6_0_LATENCY
#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF6_0_HEADER
#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF6_0_BIST
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_CAP_PTR
#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF6_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF6_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF6_0_PMI_CAP
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF6_0_SBRN
#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF6_0_FLADJ
#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF6_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF6_0_LINK_CAP
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF6_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF6_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF6_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF6_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF6_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_MASK
#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF6_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF6_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF6_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF6_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF6_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF6_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF6_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
//BIF_CFG_DEV0_EPF7_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF7_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF7_0_COMMAND
#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF7_0_STATUS
#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV0_EPF7_0_REVISION_ID
#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF7_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF7_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF7_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF7_0_LATENCY
#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF7_0_HEADER
#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF7_0_BIST
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_CAP_PTR
#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF7_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF7_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF7_0_PMI_CAP
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF7_0_SBRN
#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV0_EPF7_0_FLADJ
#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD
#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF7_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV0_EPF7_0_LINK_CAP
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF7_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV0_EPF7_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF7_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV0_EPF7_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF7_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_MASK
#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF7_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF7_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF7_0_SATA_CAP_0
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF7_0_SATA_CAP_1
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF7_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF7_0_RTR_DATA1
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV0_EPF7_0_RTR_DATA2
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV0_EPF7_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
//BIF_CFG_DEV1_RC0_VENDOR_ID
#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV1_RC0_DEVICE_ID
#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV1_RC0_COMMAND
#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
//BIF_CFG_DEV1_RC0_STATUS
#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
//BIF_CFG_DEV1_RC0_REVISION_ID
#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
//BIF_CFG_DEV1_RC0_PROG_INTERFACE
#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
//BIF_CFG_DEV1_RC0_SUB_CLASS
#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
//BIF_CFG_DEV1_RC0_BASE_CLASS
#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
//BIF_CFG_DEV1_RC0_CACHE_LINE
#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
//BIF_CFG_DEV1_RC0_LATENCY
#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
//BIF_CFG_DEV1_RC0_HEADER
#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
//BIF_CFG_DEV1_RC0_BIST
#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
//BIF_CFG_DEV1_RC0_BASE_ADDR_1
#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_BASE_ADDR_2
#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
//BIF_CFG_DEV1_RC0_SECONDARY_STATUS
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
//BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
//BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
//BIF_CFG_DEV1_RC0_PREF_BASE_UPPER
#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER
#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
//BIF_CFG_DEV1_RC0_CAP_PTR
#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
//BIF_CFG_DEV1_RC0_ROM_BASE_ADDR
#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_INTERRUPT_LINE
#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
//BIF_CFG_DEV1_RC0_INTERRUPT_PIN
#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
//BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
//BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
//BIF_CFG_DEV1_RC0_PMI_CAP_LIST
#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV1_RC0_PMI_CAP
#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
//BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
//BIF_CFG_DEV1_RC0_PCIE_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_RC0_PCIE_CAP
#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
//BIF_CFG_DEV1_RC0_DEVICE_CAP
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
//BIF_CFG_DEV1_RC0_DEVICE_CNTL
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
//BIF_CFG_DEV1_RC0_DEVICE_STATUS
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
//BIF_CFG_DEV1_RC0_LINK_CAP
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
//BIF_CFG_DEV1_RC0_LINK_CNTL
#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                       0x2
#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                         0x0004L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
//BIF_CFG_DEV1_RC0_LINK_STATUS
#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
//BIF_CFG_DEV1_RC0_SLOT_CAP
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
//BIF_CFG_DEV1_RC0_SLOT_CNTL
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
//BIF_CFG_DEV1_RC0_SLOT_STATUS
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
//BIF_CFG_DEV1_RC0_ROOT_CNTL
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
//BIF_CFG_DEV1_RC0_ROOT_CAP
#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
//BIF_CFG_DEV1_RC0_ROOT_STATUS
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
//BIF_CFG_DEV1_RC0_DEVICE_CAP2
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
//BIF_CFG_DEV1_RC0_DEVICE_CNTL2
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
//BIF_CFG_DEV1_RC0_DEVICE_STATUS2
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
//BIF_CFG_DEV1_RC0_LINK_CAP2
#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                           0x9
#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                             0x0000FE00L
#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
//BIF_CFG_DEV1_RC0_LINK_CNTL2
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
//BIF_CFG_DEV1_RC0_LINK_STATUS2
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
//BIF_CFG_DEV1_RC0_SLOT_CAP2
#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_SLOT_CNTL2
#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
//BIF_CFG_DEV1_RC0_SLOT_STATUS2
#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
//BIF_CFG_DEV1_RC0_MSI_CAP_LIST
#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV1_RC0_MSI_MSG_CNTL
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_MSI_MSG_DATA
#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
//BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
//BIF_CFG_DEV1_RC0_SSID_CAP_LIST
#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV1_RC0_SSID_CAP
#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
//BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV1_RC0_MSI_MAP_CAP
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                           0x5
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                            0x6
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                             0x00000020L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                              0x00000040L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
//BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                      0x9
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                        0x0000FE00L
//BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
//BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV1_RC0_PCIE_ACS_CAP
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
//BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
//BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
//BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_RC0_LINK_CAP_16GT
#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_LINK_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV1_RC0_LINK_STATUS_16GT
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
//BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
//BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
//BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV1_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV1_RC0_RTR_DATA1
#define BIF_CFG_DEV1_RC0_RTR_DATA1__RESET_TIME__SHIFT                                                         0x0
#define BIF_CFG_DEV1_RC0_RTR_DATA1__DLUP_TIME__SHIFT                                                          0xc
#define BIF_CFG_DEV1_RC0_RTR_DATA1__VALID__SHIFT                                                              0x1f
#define BIF_CFG_DEV1_RC0_RTR_DATA1__RESET_TIME_MASK                                                           0x00000FFFL
#define BIF_CFG_DEV1_RC0_RTR_DATA1__DLUP_TIME_MASK                                                            0x00FFF000L
#define BIF_CFG_DEV1_RC0_RTR_DATA1__VALID_MASK                                                                0x80000000L
//BIF_CFG_DEV1_RC0_RTR_DATA2
#define BIF_CFG_DEV1_RC0_RTR_DATA2__FLR_TIME__SHIFT                                                           0x0
#define BIF_CFG_DEV1_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV1_RC0_RTR_DATA2__FLR_TIME_MASK                                                             0x00000FFFL
#define BIF_CFG_DEV1_RC0_RTR_DATA2__D3HOTD0_TIME_MASK                                                         0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
//BIF_CFG_DEV1_EPF0_0_VENDOR_ID
#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF0_0_DEVICE_ID
#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF0_0_COMMAND
#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV1_EPF0_0_STATUS
#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV1_EPF0_0_REVISION_ID
#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE
#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV1_EPF0_0_SUB_CLASS
#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF0_0_BASE_CLASS
#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV1_EPF0_0_CACHE_LINE
#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV1_EPF0_0_LATENCY
#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV1_EPF0_0_HEADER
#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV1_EPF0_0_BIST
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR
#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_CAP_PTR
#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE
#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN
#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF0_0_MIN_GRANT
#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF0_0_MAX_LATENCY
#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV1_EPF0_0_PMI_CAP
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV1_EPF0_0_SBRN
#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV1_EPF0_0_FLADJ
#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD
#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV1_EPF0_0_PCIE_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV1_EPF0_0_LINK_CAP
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV1_EPF0_0_LINK_CNTL
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV1_EPF0_0_LINK_STATUS
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV1_EPF0_0_LINK_CAP2
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV1_EPF0_0_LINK_CNTL2
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV1_EPF0_0_LINK_STATUS2
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_MASK
#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_MASK_64
#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_PENDING
#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64
#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV1_EPF0_0_MSIX_TABLE
#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV1_EPF0_0_MSIX_PBA
#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV1_EPF0_0_SATA_CAP_0
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV1_EPF0_0_SATA_CAP_1
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                   0x9
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                     0x0000FE00L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
//BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
//BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
//BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF0_0_RTR_DATA1
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV1_EPF0_0_RTR_DATA2
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV1_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
//BIF_CFG_DEV1_EPF1_0_VENDOR_ID
#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF1_0_DEVICE_ID
#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV1_EPF1_0_COMMAND
#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV1_EPF1_0_STATUS
#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV1_EPF1_0_REVISION_ID
#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE
#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV1_EPF1_0_SUB_CLASS
#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF1_0_BASE_CLASS
#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV1_EPF1_0_CACHE_LINE
#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV1_EPF1_0_LATENCY
#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV1_EPF1_0_HEADER
#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV1_EPF1_0_BIST
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR
#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_CAP_PTR
#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE
#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN
#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV1_EPF1_0_MIN_GRANT
#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV1_EPF1_0_MAX_LATENCY
#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV1_EPF1_0_PMI_CAP
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV1_EPF1_0_SBRN
#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV1_EPF1_0_FLADJ
#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD
#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV1_EPF1_0_PCIE_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV1_EPF1_0_LINK_CAP
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV1_EPF1_0_LINK_CNTL
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV1_EPF1_0_LINK_STATUS
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV1_EPF1_0_LINK_CAP2
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV1_EPF1_0_LINK_CNTL2
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV1_EPF1_0_LINK_STATUS2
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_MASK
#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_MASK_64
#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_PENDING
#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64
#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV1_EPF1_0_MSIX_TABLE
#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV1_EPF1_0_MSIX_PBA
#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV1_EPF1_0_SATA_CAP_0
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV1_EPF1_0_SATA_CAP_1
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_STATUS
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
//BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
#define BIF_CFG_DEV1_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
//BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV1_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV1_EPF1_0_RTR_DATA1
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV1_EPF1_0_RTR_DATA2
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV1_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
//BIF_CFG_DEV2_RC0_VENDOR_ID
#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV2_RC0_DEVICE_ID
#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
//BIF_CFG_DEV2_RC0_COMMAND
#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
//BIF_CFG_DEV2_RC0_STATUS
#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
//BIF_CFG_DEV2_RC0_REVISION_ID
#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
//BIF_CFG_DEV2_RC0_PROG_INTERFACE
#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
//BIF_CFG_DEV2_RC0_SUB_CLASS
#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
//BIF_CFG_DEV2_RC0_BASE_CLASS
#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
//BIF_CFG_DEV2_RC0_CACHE_LINE
#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
//BIF_CFG_DEV2_RC0_LATENCY
#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
//BIF_CFG_DEV2_RC0_HEADER
#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
//BIF_CFG_DEV2_RC0_BIST
#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
//BIF_CFG_DEV2_RC0_BASE_ADDR_1
#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_BASE_ADDR_2
#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
//BIF_CFG_DEV2_RC0_SECONDARY_STATUS
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
//BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
//BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
//BIF_CFG_DEV2_RC0_PREF_BASE_UPPER
#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER
#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
//BIF_CFG_DEV2_RC0_CAP_PTR
#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
//BIF_CFG_DEV2_RC0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_INTERRUPT_LINE
#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
//BIF_CFG_DEV2_RC0_INTERRUPT_PIN
#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
//BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
//BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL
#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
//BIF_CFG_DEV2_RC0_PMI_CAP_LIST
#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV2_RC0_PMI_CAP
#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
//BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
//BIF_CFG_DEV2_RC0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_RC0_PCIE_CAP
#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
//BIF_CFG_DEV2_RC0_DEVICE_CAP
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
//BIF_CFG_DEV2_RC0_DEVICE_CNTL
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
//BIF_CFG_DEV2_RC0_DEVICE_STATUS
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
//BIF_CFG_DEV2_RC0_LINK_CAP
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
//BIF_CFG_DEV2_RC0_LINK_CNTL
#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                       0x2
#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                         0x0004L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
//BIF_CFG_DEV2_RC0_LINK_STATUS
#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
//BIF_CFG_DEV2_RC0_SLOT_CAP
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
//BIF_CFG_DEV2_RC0_SLOT_CNTL
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
//BIF_CFG_DEV2_RC0_SLOT_STATUS
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
//BIF_CFG_DEV2_RC0_ROOT_CNTL
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
//BIF_CFG_DEV2_RC0_ROOT_CAP
#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
//BIF_CFG_DEV2_RC0_ROOT_STATUS
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
//BIF_CFG_DEV2_RC0_DEVICE_CAP2
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
//BIF_CFG_DEV2_RC0_DEVICE_CNTL2
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
//BIF_CFG_DEV2_RC0_DEVICE_STATUS2
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
//BIF_CFG_DEV2_RC0_LINK_CAP2
#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                           0x9
#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                             0x0000FE00L
#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
//BIF_CFG_DEV2_RC0_LINK_CNTL2
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
//BIF_CFG_DEV2_RC0_LINK_STATUS2
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
//BIF_CFG_DEV2_RC0_SLOT_CAP2
#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_SLOT_CNTL2
#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
//BIF_CFG_DEV2_RC0_SLOT_STATUS2
#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
//BIF_CFG_DEV2_RC0_MSI_CAP_LIST
#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
//BIF_CFG_DEV2_RC0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_MSI_MSG_DATA
#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
//BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
//BIF_CFG_DEV2_RC0_SSID_CAP_LIST
#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
//BIF_CFG_DEV2_RC0_SSID_CAP
#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
//BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_RC0_MSI_MAP_CAP
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                           0x5
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                            0x6
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                             0x00000020L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                              0x00000040L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
//BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID
#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                      0x9
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                        0x0000FE00L
//BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
//BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
//BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV2_RC0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
//BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
//BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
//BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_RC0_LINK_CAP_16GT
#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_LINK_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV2_RC0_LINK_STATUS_16GT
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
//BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
//BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
//BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
//BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
//BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
//BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
//BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
//BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
#define BIF_CFG_DEV2_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
//BIF_CFG_DEV2_RC0_RTR_DATA1
#define BIF_CFG_DEV2_RC0_RTR_DATA1__RESET_TIME__SHIFT                                                         0x0
#define BIF_CFG_DEV2_RC0_RTR_DATA1__DLUP_TIME__SHIFT                                                          0xc
#define BIF_CFG_DEV2_RC0_RTR_DATA1__VALID__SHIFT                                                              0x1f
#define BIF_CFG_DEV2_RC0_RTR_DATA1__RESET_TIME_MASK                                                           0x00000FFFL
#define BIF_CFG_DEV2_RC0_RTR_DATA1__DLUP_TIME_MASK                                                            0x00FFF000L
#define BIF_CFG_DEV2_RC0_RTR_DATA1__VALID_MASK                                                                0x80000000L
//BIF_CFG_DEV2_RC0_RTR_DATA2
#define BIF_CFG_DEV2_RC0_RTR_DATA2__FLR_TIME__SHIFT                                                           0x0
#define BIF_CFG_DEV2_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_RC0_RTR_DATA2__FLR_TIME_MASK                                                             0x00000FFFL
#define BIF_CFG_DEV2_RC0_RTR_DATA2__D3HOTD0_TIME_MASK                                                         0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
//BIF_CFG_DEV2_EPF0_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF0_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF0_0_COMMAND
#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF0_0_STATUS
#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF0_0_REVISION_ID
#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF0_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF0_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF0_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF0_0_LATENCY
#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF0_0_HEADER
#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF0_0_BIST
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_CAP_PTR
#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF0_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF0_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF0_0_PMI_CAP
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF0_0_SBRN
#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV2_EPF0_0_FLADJ
#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF0_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF0_0_LINK_CAP
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF0_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF0_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF0_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF0_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF0_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_MASK
#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF0_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF0_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF0_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF0_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                   0x9
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                     0x0000FE00L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
//BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
//BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
//BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
//BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
//BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
//BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF0_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF0_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
//BIF_CFG_DEV2_EPF1_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF1_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF1_0_COMMAND
#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF1_0_STATUS
#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF1_0_REVISION_ID
#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF1_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF1_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF1_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF1_0_LATENCY
#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF1_0_HEADER
#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF1_0_BIST
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_CAP_PTR
#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF1_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF1_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF1_0_PMI_CAP
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF1_0_SBRN
#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV2_EPF1_0_FLADJ
#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF1_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF1_0_LINK_CAP
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF1_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF1_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF1_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF1_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF1_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_MASK
#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF1_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF1_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF1_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF1_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF1_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF1_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF1_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF1_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
//BIF_CFG_DEV2_EPF2_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF2_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF2_0_COMMAND
#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF2_0_STATUS
#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF2_0_REVISION_ID
#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF2_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF2_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF2_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF2_0_LATENCY
#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF2_0_HEADER
#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF2_0_BIST
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_CAP_PTR
#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF2_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF2_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF2_0_PMI_CAP
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF2_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF2_0_LINK_CAP
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF2_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF2_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF2_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF2_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF2_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_MASK
#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF2_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF2_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF2_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF2_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF2_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF2_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF2_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF2_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf3_bifcfgdecp
//BIF_CFG_DEV2_EPF3_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF3_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF3_0_COMMAND
#define BIF_CFG_DEV2_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF3_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF3_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF3_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF3_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF3_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF3_0_STATUS
#define BIF_CFG_DEV2_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF3_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF3_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF3_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF3_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF3_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF3_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF3_0_REVISION_ID
#define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF3_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF3_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF3_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF3_0_LATENCY
#define BIF_CFG_DEV2_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF3_0_HEADER
#define BIF_CFG_DEV2_EPF3_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF3_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF3_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF3_0_BIST
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF3_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_CAP_PTR
#define BIF_CFG_DEV2_EPF3_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF3_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF3_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF3_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF3_0_PMI_CAP
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF3_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF3_0_SBRN
#define BIF_CFG_DEV2_EPF3_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF3_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV2_EPF3_0_FLADJ
#define BIF_CFG_DEV2_EPF3_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV2_EPF3_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV2_EPF3_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV2_EPF3_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV2_EPF3_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF3_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF3_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF3_0_LINK_CAP
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF3_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF3_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF3_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF3_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF3_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_MASK
#define BIF_CFG_DEV2_EPF3_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF3_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF3_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF3_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF3_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF3_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF3_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF3_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF3_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf4_bifcfgdecp
//BIF_CFG_DEV2_EPF4_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF4_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF4_0_COMMAND
#define BIF_CFG_DEV2_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF4_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF4_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF4_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF4_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF4_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF4_0_STATUS
#define BIF_CFG_DEV2_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF4_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF4_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF4_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF4_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF4_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF4_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF4_0_REVISION_ID
#define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF4_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF4_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF4_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF4_0_LATENCY
#define BIF_CFG_DEV2_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF4_0_HEADER
#define BIF_CFG_DEV2_EPF4_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF4_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF4_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF4_0_BIST
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF4_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_CAP_PTR
#define BIF_CFG_DEV2_EPF4_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF4_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF4_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF4_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF4_0_PMI_CAP
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF4_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF4_0_SBRN
#define BIF_CFG_DEV2_EPF4_0_SBRN__SBRN__SHIFT                                                                 0x0
#define BIF_CFG_DEV2_EPF4_0_SBRN__SBRN_MASK                                                                   0xFFL
//BIF_CFG_DEV2_EPF4_0_FLADJ
#define BIF_CFG_DEV2_EPF4_0_FLADJ__FLADJ__SHIFT                                                               0x0
#define BIF_CFG_DEV2_EPF4_0_FLADJ__NFC__SHIFT                                                                 0x6
#define BIF_CFG_DEV2_EPF4_0_FLADJ__FLADJ_MASK                                                                 0x3FL
#define BIF_CFG_DEV2_EPF4_0_FLADJ__NFC_MASK                                                                   0x40L
//BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD
#define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
#define BIF_CFG_DEV2_EPF4_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF4_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF4_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF4_0_LINK_CAP
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF4_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF4_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF4_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF4_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF4_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_MASK
#define BIF_CFG_DEV2_EPF4_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF4_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF4_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF4_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF4_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF4_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF4_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF4_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF4_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf5_bifcfgdecp
//BIF_CFG_DEV2_EPF5_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF5_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF5_0_COMMAND
#define BIF_CFG_DEV2_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF5_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF5_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF5_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF5_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF5_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF5_0_STATUS
#define BIF_CFG_DEV2_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF5_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF5_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF5_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF5_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF5_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF5_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF5_0_REVISION_ID
#define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF5_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF5_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF5_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF5_0_LATENCY
#define BIF_CFG_DEV2_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF5_0_HEADER
#define BIF_CFG_DEV2_EPF5_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF5_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF5_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF5_0_BIST
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF5_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_CAP_PTR
#define BIF_CFG_DEV2_EPF5_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF5_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF5_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF5_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF5_0_PMI_CAP
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF5_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF5_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF5_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF5_0_LINK_CAP
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF5_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF5_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF5_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF5_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF5_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_MASK
#define BIF_CFG_DEV2_EPF5_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF5_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF5_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF5_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF5_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF5_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF5_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF5_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF5_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_bif_cfg_dev2_epf6_bifcfgdecp
//BIF_CFG_DEV2_EPF6_0_VENDOR_ID
#define BIF_CFG_DEV2_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF6_0_DEVICE_ID
#define BIF_CFG_DEV2_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV2_EPF6_0_COMMAND
#define BIF_CFG_DEV2_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV2_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV2_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV2_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV2_EPF6_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV2_EPF6_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV2_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV2_EPF6_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV2_EPF6_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV2_EPF6_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV2_EPF6_0_STATUS
#define BIF_CFG_DEV2_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF6_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV2_EPF6_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
#define BIF_CFG_DEV2_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV2_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
#define BIF_CFG_DEV2_EPF6_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF6_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV2_EPF6_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
#define BIF_CFG_DEV2_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV2_EPF6_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV2_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV2_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
//BIF_CFG_DEV2_EPF6_0_REVISION_ID
#define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV2_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE
#define BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF6_0_SUB_CLASS
#define BIF_CFG_DEV2_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF6_0_BASE_CLASS
#define BIF_CFG_DEV2_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF6_0_CACHE_LINE
#define BIF_CFG_DEV2_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV2_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV2_EPF6_0_LATENCY
#define BIF_CFG_DEV2_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV2_EPF6_0_HEADER
#define BIF_CFG_DEV2_EPF6_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV2_EPF6_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV2_EPF6_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV2_EPF6_0_BIST
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV2_EPF6_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_ADAPTER_ID
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR
#define BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_CAP_PTR
#define BIF_CFG_DEV2_EPF6_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF6_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
//BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE
#define BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN
#define BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV2_EPF6_0_MIN_GRANT
#define BIF_CFG_DEV2_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV2_EPF6_0_MAX_LATENCY
#define BIF_CFG_DEV2_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV2_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF6_0_PMI_CAP
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV2_EPF6_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV2_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF6_0_PCIE_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV2_EPF6_0_DEVICE_CAP
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
//BIF_CFG_DEV2_EPF6_0_LINK_CAP
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV2_EPF6_0_LINK_CNTL
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
//BIF_CFG_DEV2_EPF6_0_LINK_STATUS
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
//BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV2_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV2_EPF6_0_LINK_CAP2
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
#define BIF_CFG_DEV2_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
//BIF_CFG_DEV2_EPF6_0_LINK_CNTL2
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV2_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV2_EPF6_0_LINK_STATUS2
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
#define BIF_CFG_DEV2_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
//BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV2_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
//BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA
#define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_MASK
#define BIF_CFG_DEV2_EPF6_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64
#define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_MASK_64
#define BIF_CFG_DEV2_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_PENDING
#define BIF_CFG_DEV2_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64
#define BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV2_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV2_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV2_EPF6_0_MSIX_TABLE
#define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV2_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV2_EPF6_0_MSIX_PBA
#define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV2_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV2_EPF6_0_SATA_CAP_0
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT                                                         0x0
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT                                                       0x8
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT                                             0x14
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__CAP_ID_MASK                                                           0x000000FFL
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK                                                         0x0000FF00L
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK                                               0x00F00000L
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF6_0_SATA_CAP_1
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT                                            0x4
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT                                             0x18
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK                                                 0x0000000FL
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK                                              0x00FFFFF0L
#define BIF_CFG_DEV2_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK                                               0xFF000000L
//BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT                                                  0x2
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK                                                0x00000003L
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK                                                    0x00000FFCL
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK                                                0xFFFFF000L
//BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT                                                    0x0
#define BIF_CFG_DEV2_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
//BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
//BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
//BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
//BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
//BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
//BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
//BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV2_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV2_EPF6_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV2_EPF6_0_RTR_DATA1
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__VALID__SHIFT                                                           0x1f
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA1__VALID_MASK                                                             0x80000000L
//BIF_CFG_DEV2_EPF6_0_RTR_DATA2
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
#define BIF_CFG_DEV2_EPF6_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L


// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
//RCC_EP_DEV0_0_EP_PCIE_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV0_0_DN_PCIE_CNTL
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC
//RCC_EP_DEV1_EP_PCIE_SCRATCH
#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                      0x0
#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                        0xFFFFFFFFL
//RCC_EP_DEV1_EP_PCIE_CNTL
#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                    0x7
#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                              0x8
#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                 0x1e
#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                      0x00000080L
#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                0x00000100L
#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                   0x40000000L
//RCC_EP_DEV1_EP_PCIE_INT_CNTL
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                  0x0
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                             0x1
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                                 0x2
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                              0x3
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                  0x4
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                           0x6
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                    0x00000001L
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                               0x00000002L
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                   0x00000004L
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                                0x00000008L
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                    0x00000010L
#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                             0x00000040L
//RCC_EP_DEV1_EP_PCIE_INT_STATUS
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                            0x0
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                       0x1
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                           0x2
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                        0x3
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                            0x4
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                     0x6
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                  0x7
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                              0x00000001L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                         0x00000002L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                             0x00000004L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                          0x00000008L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                              0x00000010L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                       0x00000040L
#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                    0x00000080L
//RCC_EP_DEV1_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                     0x0
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                       0x00000001L
//RCC_EP_DEV1_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                0x7
#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                  0x00000080L
//RCC_EP_DEV1_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                         0x0
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                    0x1
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                    0x2
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                    0x3
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                    0x4
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                           0x00000001L
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                      0x00000002L
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                      0x00000004L
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                      0x00000008L
#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                      0x00000010L
//RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                        0x0
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                         0x3
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                        0x6
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                       0x7
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                        0xa
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                       0xd
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                                 0xe
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                   0xf
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                              0x10
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                     0x11
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                          0x00000007L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                           0x00000038L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                          0x00000040L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                         0x00000380L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                          0x00001C00L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                         0x00002000L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                   0x00004000L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                     0x00008000L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                                0x00010000L
#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                       0x00020000L
//RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0xFFL
//RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                               0x0
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                           0x8
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                                 0x001FL
#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                             0x0100L
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV1_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                             0x0
#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                               0x1FL
//RCC_EP_DEV1_EP_PCIEP_RESERVED
#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                  0x0
#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                    0xFFFFFFFFL
//RCC_EP_DEV1_EP_PCIE_TX_CNTL
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                   0xa
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                    0xc
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                     0x18
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                     0x19
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                     0x1a
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                     0x00000C00L
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                      0x00003000L
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                       0x01000000L
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                       0x02000000L
#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                       0x04000000L
//RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                  0x0
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                    0x3
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                       0x8
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                    0x00000007L
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                      0x000000F8L
#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                         0x0000FF00L
//RCC_EP_DEV1_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                0x0
#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                         0x11
#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                  0x00000001L
#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                           0x00020000L
//RCC_EP_DEV1_EP_PCIE_RX_CNTL
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                         0x8
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                  0x9
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                           0x14
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                         0x15
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                           0x16
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                        0x18
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                            0x19
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                        0x1a
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                           0x00000100L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                    0x00000200L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                             0x00100000L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                           0x00200000L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                             0x00400000L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                          0x01000000L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                              0x02000000L
#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                          0x04000000L
//RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC
//RCC_DWN_DEV1_DN_PCIE_RESERVED
#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                   0x0
#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV1_DN_PCIE_SCRATCH
#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                     0x0
#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                       0xFFFFFFFFL
//RCC_DWN_DEV1_DN_PCIE_CNTL
#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                      0x0
#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                                0x7
#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                0x1e
#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                        0x00000001L
#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                  0x00000080L
#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                  0x40000000L
//RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                  0x19
#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                    0x06000000L
//RCC_DWN_DEV1_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                 0x1c
#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                   0x70000000L
//RCC_DWN_DEV1_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                               0x7
#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                     0x8
#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                 0x00000080L
#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                       0x00000100L
//RCC_DWN_DEV1_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                        0x0
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                   0x1
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                   0x2
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                   0x3
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                   0x4
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                          0x00000001L
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                     0x00000002L
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                     0x00000004L
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                     0x00000008L
#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                     0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC
//RCC_DWNP_DEV1_PCIE_ERR_CNTL
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                 0x0
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                          0x11
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                                 0x12
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                             0x13
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                                0x14
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                   0x00000001L
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                            0x00020000L
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                   0x00040000L
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                               0x00080000L
#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                  0x00100000L
//RCC_DWNP_DEV1_PCIE_RX_CNTL
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                          0x8
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                                0x9
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                            0x14
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                       0x15
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                             0x1b
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                            0x00000100L
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                  0x00000200L
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                              0x00100000L
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                         0x00200000L
#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                               0x08000000L
//RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV1_PCIE_LC_CNTL2
#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                                 0x0
#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                       0x1b
#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                   0x00000001L
#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                         0x08000000L
//RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                       0x0
#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                         0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC
//RCC_EP_DEV2_EP_PCIE_SCRATCH
#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                      0x0
#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                        0xFFFFFFFFL
//RCC_EP_DEV2_EP_PCIE_CNTL
#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                    0x7
#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                              0x8
#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                 0x1e
#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                      0x00000080L
#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                0x00000100L
#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                   0x40000000L
//RCC_EP_DEV2_EP_PCIE_INT_CNTL
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                  0x0
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                             0x1
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                                 0x2
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                              0x3
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                  0x4
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                           0x6
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                    0x00000001L
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                               0x00000002L
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                   0x00000004L
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                                0x00000008L
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                    0x00000010L
#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                             0x00000040L
//RCC_EP_DEV2_EP_PCIE_INT_STATUS
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                            0x0
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                       0x1
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                           0x2
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                        0x3
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                            0x4
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                     0x6
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                  0x7
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                              0x00000001L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                         0x00000002L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                             0x00000004L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                          0x00000008L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                              0x00000010L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                       0x00000040L
#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                    0x00000080L
//RCC_EP_DEV2_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                     0x0
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                       0x00000001L
//RCC_EP_DEV2_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                0x7
#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                  0x00000080L
//RCC_EP_DEV2_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                         0x0
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                    0x1
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                    0x2
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                    0x3
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                    0x4
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                           0x00000001L
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                      0x00000002L
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                      0x00000004L
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                      0x00000008L
#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                      0x00000010L
//RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                        0x0
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                         0x3
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                        0x6
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                       0x7
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                        0xa
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                       0xd
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                                 0xe
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                   0xf
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                              0x10
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                     0x11
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                          0x00000007L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                           0x00000038L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                          0x00000040L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                         0x00000380L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                          0x00001C00L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                         0x00002000L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                   0x00004000L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                     0x00008000L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                                0x00010000L
#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                       0x00020000L
//RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
//RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0xFFL
//RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                               0x0
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                           0x8
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                                 0x001FL
#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                             0x0100L
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
//RCC_EP_DEV2_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                             0x0
#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                               0x1FL
//RCC_EP_DEV2_EP_PCIEP_RESERVED
#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                  0x0
#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                    0xFFFFFFFFL
//RCC_EP_DEV2_EP_PCIE_TX_CNTL
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                   0xa
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                    0xc
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                     0x18
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                     0x19
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                     0x1a
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                     0x00000C00L
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                      0x00003000L
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                       0x01000000L
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                       0x02000000L
#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                       0x04000000L
//RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                  0x0
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                    0x3
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                       0x8
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                    0x00000007L
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                      0x000000F8L
#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                         0x0000FF00L
//RCC_EP_DEV2_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                0x0
#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                         0x11
#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                  0x00000001L
#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                           0x00020000L
//RCC_EP_DEV2_EP_PCIE_RX_CNTL
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                         0x8
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                  0x9
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                           0x14
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                         0x15
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                           0x16
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                        0x18
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                            0x19
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                        0x1a
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                           0x00000100L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                    0x00000200L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                             0x00100000L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                           0x00200000L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                             0x00400000L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                          0x01000000L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                              0x02000000L
#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                          0x04000000L
//RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC
//RCC_DWN_DEV2_DN_PCIE_RESERVED
#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                   0x0
#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV2_DN_PCIE_SCRATCH
#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                     0x0
#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                       0xFFFFFFFFL
//RCC_DWN_DEV2_DN_PCIE_CNTL
#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                      0x0
#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                                0x7
#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                0x1e
#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                        0x00000001L
#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                  0x00000080L
#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                  0x40000000L
//RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                  0x19
#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                    0x06000000L
//RCC_DWN_DEV2_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                 0x1c
#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                   0x70000000L
//RCC_DWN_DEV2_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                               0x7
#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                     0x8
#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                 0x00000080L
#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                       0x00000100L
//RCC_DWN_DEV2_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                        0x0
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                   0x1
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                   0x2
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                   0x3
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                   0x4
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                          0x00000001L
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                     0x00000002L
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                     0x00000004L
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                     0x00000008L
#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                     0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC
//RCC_DWNP_DEV2_PCIE_ERR_CNTL
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                 0x0
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                          0x11
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                                 0x12
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                             0x13
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                                0x14
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                   0x00000001L
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                            0x00020000L
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                   0x00040000L
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                               0x00080000L
#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                  0x00100000L
//RCC_DWNP_DEV2_PCIE_RX_CNTL
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                          0x8
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                                0x9
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                            0x14
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                       0x15
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                             0x1b
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                            0x00000100L
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                  0x00000200L
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                              0x00100000L
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                         0x00200000L
#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                               0x08000000L
//RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV2_PCIE_LC_CNTL2
#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                                 0x0
#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                       0x1b
#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                   0x00000001L
#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                         0x08000000L
//RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                       0x0
#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                         0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
//HARD_RST_CTRL
#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT                                                                 0x0
#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT                                                          0x1
#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT                                                                 0x2
#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT                                                          0x3
#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT                                                                   0x4
#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT                                                            0x5
#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT                                                                   0x6
#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT                                                            0x7
#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                               0x9
#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                               0xa
#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT                                                              0x1d
#define HARD_RST_CTRL__CORE_RST_EN__SHIFT                                                                     0x1f
#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK                                                                   0x00000001L
#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK                                                            0x00000002L
#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK                                                                   0x00000004L
#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK                                                            0x00000008L
#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK                                                                     0x00000010L
#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK                                                              0x00000020L
#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK                                                                     0x00000040L
#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK                                                              0x00000080L
#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                                 0x00000200L
#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK                                                                 0x00000400L
#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK                                                                0x20000000L
#define HARD_RST_CTRL__CORE_RST_EN_MASK                                                                       0x80000000L
//SELF_SOFT_RST
#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT                                                                   0x0
#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT                                                            0x1
#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT                                                                   0x2
#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT                                                            0x3
#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT                                                                     0x4
#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT                                                              0x5
#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT                                                                     0x6
#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT                                                              0x7
#define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT                                                                   0x8
#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT                                                            0x9
#define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT                                                                   0xa
#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT                                                            0xb
#define SELF_SOFT_RST__EP1_CFG_RST__SHIFT                                                                     0xc
#define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT                                                              0xd
#define SELF_SOFT_RST__EP1_PRV_RST__SHIFT                                                                     0xe
#define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT                                                              0xf
#define SELF_SOFT_RST__DSPT2_CFG_RST__SHIFT                                                                   0x10
#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST__SHIFT                                                            0x11
#define SELF_SOFT_RST__DSPT2_PRV_RST__SHIFT                                                                   0x12
#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST__SHIFT                                                            0x13
#define SELF_SOFT_RST__EP2_CFG_RST__SHIFT                                                                     0x14
#define SELF_SOFT_RST__EP2_CFG_STICKY_RST__SHIFT                                                              0x15
#define SELF_SOFT_RST__EP2_PRV_RST__SHIFT                                                                     0x16
#define SELF_SOFT_RST__EP2_PRV_STICKY_RST__SHIFT                                                              0x17
#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT                                                               0x18
#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT                                                               0x19
#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT                                                               0x1a
#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT                                                               0x1b
#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT                                                                 0x1d
#define SELF_SOFT_RST__CORE_RST__SHIFT                                                                        0x1f
#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK                                                                     0x00000001L
#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK                                                              0x00000002L
#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK                                                                     0x00000004L
#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK                                                              0x00000008L
#define SELF_SOFT_RST__EP0_CFG_RST_MASK                                                                       0x00000010L
#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK                                                                0x00000020L
#define SELF_SOFT_RST__EP0_PRV_RST_MASK                                                                       0x00000040L
#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK                                                                0x00000080L
#define SELF_SOFT_RST__DSPT1_CFG_RST_MASK                                                                     0x00000100L
#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK                                                              0x00000200L
#define SELF_SOFT_RST__DSPT1_PRV_RST_MASK                                                                     0x00000400L
#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK                                                              0x00000800L
#define SELF_SOFT_RST__EP1_CFG_RST_MASK                                                                       0x00001000L
#define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK                                                                0x00002000L
#define SELF_SOFT_RST__EP1_PRV_RST_MASK                                                                       0x00004000L
#define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK                                                                0x00008000L
#define SELF_SOFT_RST__DSPT2_CFG_RST_MASK                                                                     0x00010000L
#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST_MASK                                                              0x00020000L
#define SELF_SOFT_RST__DSPT2_PRV_RST_MASK                                                                     0x00040000L
#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST_MASK                                                              0x00080000L
#define SELF_SOFT_RST__EP2_CFG_RST_MASK                                                                       0x00100000L
#define SELF_SOFT_RST__EP2_CFG_STICKY_RST_MASK                                                                0x00200000L
#define SELF_SOFT_RST__EP2_PRV_RST_MASK                                                                       0x00400000L
#define SELF_SOFT_RST__EP2_PRV_STICKY_RST_MASK                                                                0x00800000L
#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK                                                                 0x01000000L
#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK                                                                 0x02000000L
#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK                                                                 0x04000000L
#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK                                                                 0x08000000L
#define SELF_SOFT_RST__CORE_STICKY_RST_MASK                                                                   0x20000000L
#define SELF_SOFT_RST__CORE_RST_MASK                                                                          0x80000000L
//BIF_GFX_DRV_VPU_RST
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT                                                      0x0
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT                                              0x1
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT                                               0x2
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT                                                      0x3
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT                                               0x4
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT                                                      0x5
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT                                               0x6
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT                                                      0x7
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK                                                        0x00000001L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK                                                0x00000002L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK                                                 0x00000004L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK                                                        0x00000008L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK                                                 0x00000010L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK                                                        0x00000020L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK                                                 0x00000040L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK                                                        0x00000080L
//BIF_RST_MISC_CTRL
#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT                                                    0x0
#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT                                                                0x2
#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT                                                            0x4
#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT                                                     0x5
#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT                                                      0x6
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT                                                          0x9
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT                                                       0xa
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT                                                           0xd
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT                                                          0xf
#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT                                              0x11
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT                                                       0x17
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT                                                    0x18
#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK                                                      0x00000001L
#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK                                                                  0x0000000CL
#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK                                                              0x00000010L
#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK                                                       0x00000020L
#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK                                                        0x00000040L
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK                                                            0x00000200L
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK                                                         0x00001C00L
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK                                                             0x00006000L
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK                                                            0x00018000L
#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK                                                0x000E0000L
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK                                                         0x00800000L
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK                                                      0x03000000L
//BIF_RST_MISC_CTRL2
#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x10
#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x11
#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT                                                   0x12
#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT                                                   0x13
#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE__SHIFT                                                   0x14
#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT                                                         0x1f
#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK                                                      0x00010000L
#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK                                                      0x00020000L
#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK                                                     0x00040000L
#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK                                                     0x00080000L
#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE_MASK                                                     0x00100000L
#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK                                                           0x80000000L
//BIF_RST_MISC_CTRL3
#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT                                                                0x0
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT                                                        0x4
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT                                                           0x6
#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK                                                                  0x0000000FL
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK                                                          0x00000030L
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK                                                             0x00000040L
//DEV0_PF0_FLR_RST_CTRL
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF1_FLR_RST_CTRL
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF2_FLR_RST_CTRL
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF3_FLR_RST_CTRL
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF4_FLR_RST_CTRL
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF5_FLR_RST_CTRL
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF6_FLR_RST_CTRL
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF7_FLR_RST_CTRL
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//BIF_INST_RESET_INTR_STS
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT                                               0x0
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x1
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT                                                 0x2
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT                                                 0x3
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT                                                 0x4
#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT                                               0x8
#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x9
#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS__SHIFT                                               0xa
#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0xb
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK                                                 0x00000001L
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000002L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK                                                   0x00000004L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK                                                   0x00000008L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK                                                   0x00000010L
#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK                                                 0x00000100L
#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000200L
#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS_MASK                                                 0x00000400L
#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000800L
//BIF_PF_FLR_INTR_STS
#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT                                                     0x0
#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT                                                     0x1
#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT                                                     0x2
#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT                                                     0x3
#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT                                                     0x4
#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT                                                     0x5
#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT                                                     0x6
#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT                                                     0x7
#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT                                                     0x8
#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT                                                     0x9
#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS__SHIFT                                                     0x10
#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS__SHIFT                                                     0x11
#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS__SHIFT                                                     0x12
#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS__SHIFT                                                     0x13
#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS__SHIFT                                                     0x14
#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS__SHIFT                                                     0x15
#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS__SHIFT                                                     0x16
#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK                                                       0x00000001L
#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK                                                       0x00000002L
#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK                                                       0x00000004L
#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK                                                       0x00000008L
#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK                                                       0x00000010L
#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK                                                       0x00000020L
#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK                                                       0x00000040L
#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK                                                       0x00000080L
#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK                                                       0x00000100L
#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK                                                       0x00000200L
#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS_MASK                                                       0x00010000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS_MASK                                                       0x00020000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS_MASK                                                       0x00040000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS_MASK                                                       0x00080000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS_MASK                                                       0x00100000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS_MASK                                                       0x00200000L
#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS_MASK                                                       0x00400000L
//BIF_D3HOTD0_INTR_STS
#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x0
#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x1
#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT                                                0x2
#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT                                                0x3
#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT                                                0x4
#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT                                                0x5
#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT                                                0x6
#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT                                                0x7
#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x8
#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x9
#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x10
#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x11
#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS__SHIFT                                                0x12
#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS__SHIFT                                                0x13
#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS__SHIFT                                                0x14
#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS__SHIFT                                                0x15
#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS__SHIFT                                                0x16
#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000001L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000002L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00000004L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00000008L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00000010L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00000020L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00000040L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK                                                  0x00000080L
#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000100L
#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000200L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00010000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00020000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00040000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00080000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00100000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00200000L
#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00400000L
//BIF_POWER_INTR_STS
#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x0
#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x1
#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x2
#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT                                                      0x10
#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT                                                      0x11
#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS__SHIFT                                                      0x12
#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000001L
#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000002L
#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000004L
#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK                                                        0x00010000L
#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK                                                        0x00020000L
#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS_MASK                                                        0x00040000L
//BIF_PF_DSTATE_INTR_STS
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT                                               0x0
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT                                               0x1
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT                                               0x2
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT                                               0x3
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT                                               0x4
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT                                               0x5
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT                                               0x6
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT                                               0x7
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT                                               0x8
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT                                               0x9
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT                                               0xa
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT                                               0xb
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT                                               0xc
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT                                               0xd
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT                                               0xe
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT                                               0xf
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS__SHIFT                                               0x10
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS__SHIFT                                               0x11
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS__SHIFT                                               0x12
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS__SHIFT                                               0x13
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS__SHIFT                                               0x14
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS__SHIFT                                               0x15
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS__SHIFT                                               0x16
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS__SHIFT                                               0x17
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK                                                 0x00000001L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK                                                 0x00000002L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK                                                 0x00000004L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK                                                 0x00000008L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK                                                 0x00000010L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK                                                 0x00000020L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK                                                 0x00000040L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK                                                 0x00000080L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK                                                 0x00000100L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK                                                 0x00000200L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK                                                 0x00000400L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK                                                 0x00000800L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK                                                 0x00001000L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK                                                 0x00002000L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK                                                 0x00004000L
#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK                                                 0x00008000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS_MASK                                                 0x00010000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS_MASK                                                 0x00020000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS_MASK                                                 0x00040000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS_MASK                                                 0x00080000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS_MASK                                                 0x00100000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS_MASK                                                 0x00200000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS_MASK                                                 0x00400000L
#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS_MASK                                                 0x00800000L
//SELF_SOFT_RST_2
#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT                                                                 0x0
#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT                                                          0x1
#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT                                                                 0x2
#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT                                                          0x3
#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT                                                                   0x4
#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT                                                            0x5
#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT                                                                   0x6
#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT                                                            0x7
#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT                                                           0x18
#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK                                                                   0x00000001L
#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK                                                            0x00000002L
#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK                                                                   0x00000004L
#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK                                                            0x00000008L
#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK                                                                     0x00000010L
#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK                                                              0x00000020L
#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK                                                                     0x00000040L
#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK                                                              0x00000080L
#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK                                                             0x01000000L
//BIF_INST_RESET_INTR_MASK
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT                                             0x0
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x1
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT                                               0x2
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT                                               0x3
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT                                               0x4
#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT                                             0x8
#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x9
#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK__SHIFT                                             0xa
#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0xb
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK                                               0x00000001L
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000002L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK                                                 0x00000004L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK                                                 0x00000008L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK                                                 0x00000010L
#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK                                               0x00000100L
#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000200L
#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK_MASK                                               0x00000400L
#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000800L
//BIF_PF_FLR_INTR_MASK
#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT                                                   0x0
#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT                                                   0x1
#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT                                                   0x2
#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT                                                   0x3
#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT                                                   0x4
#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT                                                   0x5
#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT                                                   0x6
#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT                                                   0x7
#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT                                                   0x8
#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT                                                   0x9
#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK__SHIFT                                                   0x10
#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK__SHIFT                                                   0x11
#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK__SHIFT                                                   0x12
#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK__SHIFT                                                   0x13
#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK__SHIFT                                                   0x14
#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK__SHIFT                                                   0x15
#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK__SHIFT                                                   0x16
#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK                                                     0x00000001L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK                                                     0x00000002L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK                                                     0x00000004L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK                                                     0x00000008L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK                                                     0x00000010L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK                                                     0x00000020L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK                                                     0x00000040L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK                                                     0x00000080L
#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK                                                     0x00000100L
#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK                                                     0x00000200L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK_MASK                                                     0x00010000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK_MASK                                                     0x00020000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK_MASK                                                     0x00040000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK_MASK                                                     0x00080000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK_MASK                                                     0x00100000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK_MASK                                                     0x00200000L
#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK_MASK                                                     0x00400000L
//BIF_D3HOTD0_INTR_MASK
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x0
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x1
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0x2
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0x3
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0x4
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0x5
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0x6
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT                                              0x7
#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x8
#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x9
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x10
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x11
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0x12
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0x13
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0x14
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0x15
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0x16
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000001L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000002L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00000004L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00000008L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00000010L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00000020L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00000040L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK                                                0x00000080L
#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000100L
#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000200L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00010000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00020000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00040000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00080000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00100000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00200000L
#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00400000L
//BIF_POWER_INTR_MASK
#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x0
#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x1
#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x2
#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT                                                    0x10
#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT                                                    0x11
#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK__SHIFT                                                    0x12
#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000001L
#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000002L
#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000004L
#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK                                                      0x00010000L
#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK                                                      0x00020000L
#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK_MASK                                                      0x00040000L
//BIF_PF_DSTATE_INTR_MASK
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT                                             0x0
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT                                             0x1
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT                                             0x2
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT                                             0x3
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT                                             0x4
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT                                             0x5
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT                                             0x6
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT                                             0x7
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT                                             0x8
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT                                             0x9
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT                                             0xa
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT                                             0xb
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT                                             0xc
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT                                             0xd
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT                                             0xe
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT                                             0xf
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK__SHIFT                                             0x10
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK__SHIFT                                             0x11
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK__SHIFT                                             0x12
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK__SHIFT                                             0x13
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK__SHIFT                                             0x14
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK__SHIFT                                             0x15
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK__SHIFT                                             0x16
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK__SHIFT                                             0x17
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK                                               0x00000001L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK                                               0x00000002L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK                                               0x00000004L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK                                               0x00000008L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK                                               0x00000010L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK                                               0x00000020L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK                                               0x00000040L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK                                               0x00000080L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK                                               0x00000100L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK                                               0x00000200L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK                                               0x00000400L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK                                               0x00000800L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK                                               0x00001000L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK                                               0x00002000L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK                                               0x00004000L
#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK                                               0x00008000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK_MASK                                               0x00010000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK_MASK                                               0x00020000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK_MASK                                               0x00040000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK_MASK                                               0x00080000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK_MASK                                               0x00100000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK_MASK                                               0x00200000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK_MASK                                               0x00400000L
#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK_MASK                                               0x00800000L
//BIF_PF_FLR_RST
#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                               0x0
#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                               0x1
#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT                                                               0x2
#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT                                                               0x3
#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT                                                               0x4
#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT                                                               0x5
#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT                                                               0x6
#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT                                                               0x7
#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT                                                               0x8
#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT                                                               0x9
#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT                                                               0x10
#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT                                                               0x11
#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT                                                               0x12
#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST__SHIFT                                                               0x13
#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST__SHIFT                                                               0x14
#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST__SHIFT                                                               0x15
#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST__SHIFT                                                               0x16
#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                 0x00000001L
#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                 0x00000002L
#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK                                                                 0x00000004L
#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK                                                                 0x00000008L
#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK                                                                 0x00000010L
#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK                                                                 0x00000020L
#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK                                                                 0x00000040L
#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK                                                                 0x00000080L
#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK                                                                 0x00000100L
#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK                                                                 0x00000200L
#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK                                                                 0x00010000L
#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK                                                                 0x00020000L
#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK                                                                 0x00040000L
#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST_MASK                                                                 0x00080000L
#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST_MASK                                                                 0x00100000L
#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST_MASK                                                                 0x00200000L
#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST_MASK                                                                 0x00400000L
//BIF_DEV0_PF0_DSTATE_VALUE
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF1_DSTATE_VALUE
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF2_DSTATE_VALUE
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF3_DSTATE_VALUE
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF4_DSTATE_VALUE
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF5_DSTATE_VALUE
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF6_DSTATE_VALUE
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF7_DSTATE_VALUE
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//DEV0_PF0_D3HOTD0_RST_CTRL
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF1_D3HOTD0_RST_CTRL
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF2_D3HOTD0_RST_CTRL
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF3_D3HOTD0_RST_CTRL
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF4_D3HOTD0_RST_CTRL
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF5_D3HOTD0_RST_CTRL
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF6_D3HOTD0_RST_CTRL
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF7_D3HOTD0_RST_CTRL
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV1_PF0_FLR_RST_CTRL
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV1_PF1_FLR_RST_CTRL
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV1_PF1_FLR_RST_CTRL__VF_CFG_EN__SHIFT                                                               0x5
#define DEV1_PF1_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT                                                        0x6
#define DEV1_PF1_FLR_RST_CTRL__VF_PRV_EN__SHIFT                                                               0x7
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT                                                          0x8
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT                                                  0x9
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT                                                   0xa
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT                                                          0xb
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT                                                   0xc
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT                                                            0xd
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT                                                     0xe
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT                                                            0xf
#define DEV1_PF1_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT                                                            0x10
#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT                                                   0x1f
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV1_PF1_FLR_RST_CTRL__VF_CFG_EN_MASK                                                                 0x00000020L
#define DEV1_PF1_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK                                                          0x00000040L
#define DEV1_PF1_FLR_RST_CTRL__VF_PRV_EN_MASK                                                                 0x00000080L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK                                                            0x00000100L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK                                                    0x00000200L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK                                                     0x00000400L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK                                                            0x00000800L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK                                                     0x00001000L
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_EN_MASK                                                              0x00002000L
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK                                                       0x00004000L
#define DEV1_PF1_FLR_RST_CTRL__VF_VF_PRV_EN_MASK                                                              0x00008000L
#define DEV1_PF1_FLR_RST_CTRL__FLR_TWICE_EN_MASK                                                              0x00010000L
#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
#define DEV1_PF1_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK                                                     0x80000000L
//BIF_DEV1_PF0_DSTATE_VALUE
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV1_PF1_DSTATE_VALUE
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//DEV1_PF0_D3HOTD0_RST_CTRL
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV1_PF1_D3HOTD0_RST_CTRL
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF0_FLR_RST_CTRL
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF1_FLR_RST_CTRL
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF2_FLR_RST_CTRL
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF3_FLR_RST_CTRL
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF4_FLR_RST_CTRL
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF5_FLR_RST_CTRL
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV2_PF6_FLR_RST_CTRL
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//BIF_DEV2_PF0_DSTATE_VALUE
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF1_DSTATE_VALUE
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF2_DSTATE_VALUE
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF3_DSTATE_VALUE
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF4_DSTATE_VALUE
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF5_DSTATE_VALUE
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV2_PF6_DSTATE_VALUE
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//DEV2_PF0_D3HOTD0_RST_CTRL
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF1_D3HOTD0_RST_CTRL
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF2_D3HOTD0_RST_CTRL
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF3_D3HOTD0_RST_CTRL
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF4_D3HOTD0_RST_CTRL
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF5_D3HOTD0_RST_CTRL
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV2_PF6_D3HOTD0_RST_CTRL
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//BIF_PORT0_DSTATE_VALUE
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT                                                 0x0
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT                                                 0x10
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
//BIF_PORT1_DSTATE_VALUE
#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT                                                 0x0
#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT                                                 0x10
#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
//BIF_PORT2_DSTATE_VALUE
#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE__SHIFT                                                 0x0
#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE__SHIFT                                                 0x10
#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE_MASK                                                   0x00030000L


// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
//MISC_SCRATCH
#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT                                                                    0x0
#define MISC_SCRATCH__MISC_SCRATCH0_MASK                                                                      0xFFFFFFFFL
//INTR_LINE_POLARITY
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT                                                    0x0
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT                                                    0x8
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2__SHIFT                                                    0x10
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK                                                      0x000000FFL
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK                                                      0x0000FF00L
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2_MASK                                                      0x00FF0000L
//INTR_LINE_ENABLE
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT                                                        0x0
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT                                                        0x8
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2__SHIFT                                                        0x10
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK                                                          0x000000FFL
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK                                                          0x0000FF00L
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2_MASK                                                          0x00FF0000L
//OUTSTANDING_VC_ALLOC
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x0
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x2
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT                                                0x4
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT                                                0x6
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT                                                0x8
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT                                                0xa
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT                                                0xc
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT                                                0xe
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT                                                     0x10
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x18
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x1a
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT                                                     0x1c
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK                                                  0x00000003L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0000000CL
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK                                                  0x00000030L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK                                                  0x000000C0L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK                                                  0x00000300L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK                                                  0x00000C00L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK                                                  0x00003000L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK                                                  0x0000C000L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK                                                       0x000F0000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK                                                  0x03000000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0C000000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK                                                       0xF0000000L
//BIFC_MISC_CTRL0
#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT                                                    0x0
#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT                                                     0x1
#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT                                                           0x4
#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT                                                     0x8
#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT                                                            0x9
#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT                                                        0xa
#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT                                                   0xb
#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT                                                   0xc
#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT                                                     0x10
#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT                                                     0x11
#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT                                               0x12
#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT                                                              0x13
#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT                                                         0x14
#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT                                                            0x15
#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT                                                         0x16
#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT                                                      0x18
#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT                                                               0x1a
#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT                                                       0x1b
#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT                                                              0x1c
#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT                                                     0x1e
#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT                                                            0x1f
#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK                                                      0x00000001L
#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK                                                       0x00000006L
#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK                                                             0x000000F0L
#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK                                                       0x00000100L
#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK                                                              0x00000200L
#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK                                                          0x00000400L
#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK                                                     0x00000800L
#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK                                                     0x00001000L
#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK                                                       0x00010000L
#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK                                                       0x00020000L
#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK                                                 0x00040000L
#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK                                                                0x00080000L
#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK                                                           0x00100000L
#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK                                                              0x00200000L
#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK                                                           0x00400000L
#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK                                                        0x01000000L
#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK                                                                 0x04000000L
#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK                                                         0x08000000L
#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK                                                                0x10000000L
#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK                                                       0x40000000L
#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK                                                              0x80000000L
//BIFC_MISC_CTRL1
#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT                                                    0x0
#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT                                                         0x1
#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT                                                         0x2
#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT                                                    0x3
#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT                                                      0x4
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT                                           0x5
#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT                                                          0x6
#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT                                                        0x7
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT                                                      0x8
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT                                                  0xa
#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT                                                        0xc
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT                                                 0xd
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT                                           0xe
#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT                                                              0xf
#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT                                                       0x10
#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT                                                       0x11
#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT                                                       0x12
#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT                                                       0x13
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT                                           0x14
#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT                                                  0x17
#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT                                                      0x18
#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT                                                    0x19
#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT                                                      0x1a
#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT                                                    0x1b
#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT                                       0x1c
#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT                                                                 0x1d
#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT                                                          0x1e
#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK                                                      0x00000001L
#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK                                                           0x00000002L
#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK                                                           0x00000004L
#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK                                                      0x00000008L
#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK                                                        0x00000010L
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK                                             0x00000020L
#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK                                                            0x00000040L
#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK                                                          0x00000080L
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK                                                        0x00000300L
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK                                                    0x00000C00L
#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK                                                          0x00001000L
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK                                                   0x00002000L
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK                                             0x00004000L
#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK                                                                0x00008000L
#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK                                                         0x00010000L
#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK                                                         0x00020000L
#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK                                                         0x00040000L
#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK                                                         0x00080000L
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK                                             0x00100000L
#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK                                                    0x00800000L
#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK                                                        0x01000000L
#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK                                                      0x02000000L
#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK                                                        0x04000000L
#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK                                                      0x08000000L
#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK                                         0x10000000L
#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK                                                                   0x20000000L
#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK                                                            0xC0000000L
//BIFC_LC_TIMER_CTRL
#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT                                                      0x0
#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT                                                        0x10
#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK                                                        0x0000FFFFL
#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK                                                          0xFFFF0000L
//BIFC_RCCBIH_BME_ERR_LOG0
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                            0x0
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                            0x1
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                            0x2
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                            0x3
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                            0x4
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                            0x5
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                            0x6
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                            0x7
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT                                            0x8
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT                                            0x9
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                      0x10
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                      0x11
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                      0x12
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                      0x13
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                      0x14
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                      0x15
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                      0x16
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                      0x17
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT                                      0x18
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT                                      0x19
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                              0x00000001L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                              0x00000002L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                              0x00000004L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                              0x00000008L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                              0x00000010L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                              0x00000020L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                              0x00000040L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                              0x00000080L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0_MASK                                              0x00000100L
#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1_MASK                                              0x00000200L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                        0x00010000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                        0x00020000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                        0x00040000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                        0x00080000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                        0x00100000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                        0x00200000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                        0x00400000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                        0x00800000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK                                        0x01000000L
#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK                                        0x02000000L
//BIFC_RCCBIH_BME_ERR_LOG1
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT                                            0x0
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT                                            0x1
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT                                            0x2
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F3__SHIFT                                            0x3
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F4__SHIFT                                            0x4
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F5__SHIFT                                            0x5
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F6__SHIFT                                            0x6
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT                                      0x10
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT                                      0x11
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT                                      0x12
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F3__SHIFT                                      0x13
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F4__SHIFT                                      0x14
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F5__SHIFT                                      0x15
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F6__SHIFT                                      0x16
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0_MASK                                              0x00000001L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1_MASK                                              0x00000002L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2_MASK                                              0x00000004L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F3_MASK                                              0x00000008L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F4_MASK                                              0x00000010L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F5_MASK                                              0x00000020L
#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F6_MASK                                              0x00000040L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0_MASK                                        0x00010000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1_MASK                                        0x00020000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2_MASK                                        0x00040000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F3_MASK                                        0x00080000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F4_MASK                                        0x00100000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F5_MASK                                        0x00200000L
#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F6_MASK                                        0x00400000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6__SHIFT                                      0x4
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6__SHIFT                                   0xe
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7__SHIFT                                      0x14
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7__SHIFT                                   0x1e
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6_MASK                                        0x00000030L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6_MASK                                     0x0000C000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7_MASK                                        0x00300000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7_MASK                                     0x30000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7_MASK                                     0xC0000000L
//BIFC_DMA_ATTR_CNTL2_DEV0
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT                               0x0
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT                               0x4
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT                               0x8
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT                               0xc
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT                               0x10
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT                               0x14
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT                               0x18
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT                               0x1c
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK                                 0x00000001L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK                                 0x00000010L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK                                 0x00000100L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK                                 0x00001000L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK                                 0x00010000L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK                                 0x00100000L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK                                 0x01000000L
#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK                                 0x10000000L
//BIFC_DMA_ATTR_CNTL2_DEV1
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0__SHIFT                               0x0
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1__SHIFT                               0x4
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2__SHIFT                               0x8
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3__SHIFT                               0xc
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4__SHIFT                               0x10
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5__SHIFT                               0x14
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6__SHIFT                               0x18
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7__SHIFT                               0x1c
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0_MASK                                 0x00000001L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1_MASK                                 0x00000010L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2_MASK                                 0x00000100L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3_MASK                                 0x00001000L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4_MASK                                 0x00010000L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5_MASK                                 0x00100000L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6_MASK                                 0x01000000L
#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7_MASK                                 0x10000000L
//BIFC_DMA_ATTR_CNTL2_DEV2
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0__SHIFT                               0x0
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1__SHIFT                               0x4
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2__SHIFT                               0x8
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3__SHIFT                               0xc
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4__SHIFT                               0x10
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5__SHIFT                               0x14
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6__SHIFT                               0x18
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7__SHIFT                               0x1c
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0_MASK                                 0x00000001L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1_MASK                                 0x00000010L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2_MASK                                 0x00000100L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3_MASK                                 0x00001000L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4_MASK                                 0x00010000L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5_MASK                                 0x00100000L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6_MASK                                 0x01000000L
#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7_MASK                                 0x10000000L
//BIFC_MISC_CTRL2
#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT                                                        0x10
#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT                                               0x11
#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK                                                          0x00010000L
#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK                                                 0x00020000L
//BME_DUMMY_CNTL_0
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT                                                     0x0
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT                                                     0x2
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT                                                     0x4
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT                                                     0x6
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT                                                     0x8
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT                                                     0xa
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT                                                     0xc
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT                                                     0xe
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT                                                     0x10
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT                                                     0x12
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT                                                     0x14
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT                                                     0x16
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT                                                     0x18
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT                                                     0x1a
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT                                                     0x1c
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT                                                     0x1e
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK                                                       0x00000003L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK                                                       0x0000000CL
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK                                                       0x00000030L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK                                                       0x000000C0L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK                                                       0x00000300L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK                                                       0x00000C00L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK                                                       0x00003000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK                                                       0x0000C000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK                                                       0x00030000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK                                                       0x000C0000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK                                                       0x00300000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK                                                       0x00C00000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK                                                       0x03000000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK                                                       0x0C000000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK                                                       0x30000000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK                                                       0xC0000000L
//BME_DUMMY_CNTL_1
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0__SHIFT                                                     0x0
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1__SHIFT                                                     0x2
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2__SHIFT                                                     0x4
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3__SHIFT                                                     0x6
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4__SHIFT                                                     0x8
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5__SHIFT                                                     0xa
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6__SHIFT                                                     0xc
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7__SHIFT                                                     0xe
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0_MASK                                                       0x00000003L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1_MASK                                                       0x0000000CL
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2_MASK                                                       0x00000030L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3_MASK                                                       0x000000C0L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4_MASK                                                       0x00000300L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5_MASK                                                       0x00000C00L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6_MASK                                                       0x00003000L
#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7_MASK                                                       0x0000C000L
//BIFC_THT_CNTL
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT                                                         0x0
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT                                                         0x4
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT                                                         0x8
#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT                                                             0x10
#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT                                                 0x18
#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT                                               0x19
#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT                                                 0x1a
#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT                                               0x1b
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK                                                           0x0000000FL
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK                                                           0x000000F0L
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK                                                           0x00000F00L
#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK                                                               0x00010000L
#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK                                                   0x01000000L
#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK                                                 0x02000000L
#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK                                                   0x04000000L
#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK                                                 0x08000000L
//BIFC_HSTARB_CNTL
#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT                                                                  0x0
#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT                                                               0x8
#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK                                                                    0x00000003L
#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK                                                                 0x00000100L
//BIFC_GSI_CNTL
#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT                                                            0x0
#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT                                                            0x2
#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT                                                         0x5
#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT                                                      0x6
#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT                                                    0x7
#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT                                                   0x8
#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT                                                      0x9
#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT                                                            0xa
#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT                                                            0xc
#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT                                               0xe
#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT                                                       0xf
#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT                                                                0x10
#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT                                                       0x11
#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT                                                              0x1b
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT                                                    0x1c
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT                                                   0x1d
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT                                                      0x1e
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT                                                        0x1f
#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK                                                              0x00000003L
#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK                                                              0x0000001CL
#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK                                                           0x00000020L
#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK                                                        0x00000040L
#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK                                                      0x00000080L
#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK                                                     0x00000100L
#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK                                                        0x00000200L
#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK                                                              0x00000C00L
#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK                                                              0x00003000L
#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK                                                 0x00004000L
#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK                                                         0x00008000L
#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK                                                                  0x00010000L
#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK                                                         0x00020000L
#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK                                                                0x08000000L
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK                                                      0x10000000L
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK                                                     0x20000000L
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK                                                        0x40000000L
#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK                                                          0x80000000L
//BIFC_PCIEFUNC_CNTL
#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT                                                0x0
#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT                                             0x10
#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK                                                  0x0000FFFFL
#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK                                               0x00010000L
//BIFC_PASID_CHECK_DIS
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT                                                  0x0
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT                                                  0x1
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT                                                  0x2
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT                                                  0x3
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4__SHIFT                                                  0x4
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5__SHIFT                                                  0x5
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6__SHIFT                                                  0x6
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7__SHIFT                                                  0x7
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0__SHIFT                                                  0x8
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1__SHIFT                                                  0x9
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0__SHIFT                                                  0x10
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1__SHIFT                                                  0x11
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2__SHIFT                                                  0x12
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F3__SHIFT                                                  0x13
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F4__SHIFT                                                  0x14
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F5__SHIFT                                                  0x15
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F6__SHIFT                                                  0x16
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK                                                    0x00000001L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK                                                    0x00000002L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK                                                    0x00000004L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK                                                    0x00000008L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4_MASK                                                    0x00000010L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5_MASK                                                    0x00000020L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6_MASK                                                    0x00000040L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7_MASK                                                    0x00000080L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0_MASK                                                    0x00000100L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1_MASK                                                    0x00000200L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0_MASK                                                    0x00010000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1_MASK                                                    0x00020000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2_MASK                                                    0x00040000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F3_MASK                                                    0x00080000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F4_MASK                                                    0x00100000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F5_MASK                                                    0x00200000L
#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F6_MASK                                                    0x00400000L
//BIFC_SDP_CNTL_0
#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x0
#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x8
#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x10
#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x18
#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK                                                       0x000000FFL
#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK                                                       0x0000FF00L
#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK                                                   0x00FF0000L
#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK                                                   0xFF000000L
//BIFC_SDP_CNTL_1
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT                                                            0x0
#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT                                                            0x1
#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT                                                        0x2
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT                                                        0x3
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                               0x4
#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT                                                         0x5
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                           0x7
#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT                                                       0x8
#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT                                           0x1e
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_WAKEUP_BY_USB_EARLY_WAKEUP_EN__SHIFT                                     0x1f
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK                                                              0x00000001L
#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK                                                              0x00000002L
#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK                                                          0x00000004L
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK                                                          0x00000008L
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                                 0x00000010L
#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK                                                           0x00000020L
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                             0x00000080L
#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK                                                         0x00000100L
#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK                                             0x40000000L
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_WAKEUP_BY_USB_EARLY_WAKEUP_EN_MASK                                       0x80000000L
//BIFC_PASID_STS
#define BIFC_PASID_STS__PASID_STS__SHIFT                                                                      0x0
#define BIFC_PASID_STS__PASID_STS_MASK                                                                        0x0000000FL
//BIFC_ATHUB_ACT_CNTL
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT                                                0x0
#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT                                           0x3
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT                                                0x8
#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT                                                   0x9
#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT                                                   0xa
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT                                          0xb
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK                                                  0x00000007L
#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK                                             0x00000038L
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK                                                  0x00000100L
#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK                                                     0x00000200L
#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK                                                     0x00000400L
#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK                                            0x00000800L
//BIFC_PERF_CNTL_0
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT                                                          0x0
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT                                                          0x1
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT                                                       0x8
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT                                                       0x9
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT                                                         0x10
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT                                                         0x18
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK                                                            0x00000001L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK                                                            0x00000002L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK                                                         0x00000100L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK                                                         0x00000200L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK                                                           0x007F0000L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK                                                           0x7F000000L
//BIFC_PERF_CNTL_1
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT                                                           0x0
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT                                                           0x1
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT                                                        0x4
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT                                                        0x5
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT                                                          0x8
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT                                                          0x10
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK                                                             0x00000001L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK                                                             0x00000002L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK                                                          0x00000010L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK                                                          0x00000020L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK                                                            0x0000FF00L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK                                                            0x01FF0000L
//BIFC_PERF_CNT_MMIO_RD_L32BIT
#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT                                    0x0
#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK                                      0xFFFFFFFFL
//BIFC_PERF_CNT_MMIO_WR_L32BIT
#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT                                    0x0
#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK                                      0xFFFFFFFFL
//BIFC_PERF_CNT_DMA_RD_L32BIT
#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT                                      0x0
#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK                                        0xFFFFFFFFL
//BIFC_PERF_CNT_DMA_WR_L32BIT
#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT                                      0x0
#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK                                        0xFFFFFFFFL
//NBIF_REGIF_ERRSET_CTRL
#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                         0x0
#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                           0x00000001L
//BIFC_SDP_CNTL_2
#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT                                                    0x0
#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT                                                  0x8
#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x10
#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x18
#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK                                                      0x000000FFL
#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK                                                    0x00000F00L
#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x000F0000L
#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x0F000000L
//NBIF_PGMST_CTRL
#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT                                                        0x0
#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT                                                                0x8
#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT                                                    0xa
#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT                                                        0xe
#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK                                                          0x000000FFL
#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK                                                                  0x00000100L
#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK                                                      0x00003C00L
#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK                                                          0x0000C000L
//NBIF_PGSLV_CTRL
#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT                                                      0x0
#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK                                                        0x0000001FL
//NBIF_PG_MISC_CTRL
#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT                                                        0xa
#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT                                                           0xd
#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT                                                        0xe
#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT                                                           0x10
#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT                                             0x18
#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT                                                   0x1e
#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT                                                   0x1f
#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK                                                          0x00000400L
#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK                                                             0x00002000L
#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK                                                          0x00004000L
#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK                                                             0x00010000L
#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK                                               0x3F000000L
#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK                                                     0x40000000L
#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK                                                     0x80000000L
//NBIF_HST_MISC_CTRL
#define NBIF_HST_MISC_CTRL__ACP_NP_OSTD_LIMIT__SHIFT                                                          0x0
#define NBIF_HST_MISC_CTRL__ACP_NP_OSTD_LIMIT_MASK                                                            0x000000FFL
//SMN_MST_EP_CNTL3
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT                                                0x0
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT                                                0x1
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT                                                0x2
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT                                                0x3
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT                                                0x4
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT                                                0x5
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT                                                0x6
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT                                                0x7
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT                                                0x8
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT                                                0x9
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT                                                0xa
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT                                                0xb
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT                                                0xc
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT                                                0xd
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT                                                0xe
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT                                                0xf
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0__SHIFT                                                0x10
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1__SHIFT                                                0x11
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2__SHIFT                                                0x12
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3__SHIFT                                                0x13
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4__SHIFT                                                0x14
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5__SHIFT                                                0x15
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6__SHIFT                                                0x16
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7__SHIFT                                                0x17
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK                                                  0x00000100L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK                                                  0x00000200L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK                                                  0x00000400L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK                                                  0x00000800L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK                                                  0x00001000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK                                                  0x00002000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK                                                  0x00004000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK                                                  0x00008000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0_MASK                                                  0x00010000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1_MASK                                                  0x00020000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2_MASK                                                  0x00040000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3_MASK                                                  0x00080000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4_MASK                                                  0x00100000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5_MASK                                                  0x00200000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6_MASK                                                  0x00400000L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7_MASK                                                  0x00800000L
//SMN_MST_EP_CNTL4
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT                                                0x0
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT                                                0x1
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT                                                0x2
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT                                                0x3
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT                                                0x4
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT                                                0x5
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT                                                0x6
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT                                                0x7
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT                                                0x8
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT                                                0x9
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT                                                0xa
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT                                                0xb
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT                                                0xc
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT                                                0xd
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT                                                0xe
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT                                                0xf
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0__SHIFT                                                0x10
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1__SHIFT                                                0x11
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2__SHIFT                                                0x12
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3__SHIFT                                                0x13
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4__SHIFT                                                0x14
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5__SHIFT                                                0x15
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6__SHIFT                                                0x16
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7__SHIFT                                                0x17
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK                                                  0x00000100L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK                                                  0x00000200L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK                                                  0x00000400L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK                                                  0x00000800L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK                                                  0x00001000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK                                                  0x00002000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK                                                  0x00004000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK                                                  0x00008000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0_MASK                                                  0x00010000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1_MASK                                                  0x00020000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2_MASK                                                  0x00040000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3_MASK                                                  0x00080000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4_MASK                                                  0x00100000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5_MASK                                                  0x00200000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6_MASK                                                  0x00400000L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7_MASK                                                  0x00800000L
//SMN_MST_CNTL1
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT                                                    0x0
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT                                               0x10
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT                                               0x11
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2__SHIFT                                               0x12
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK                                                      0x00000001L
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK                                                 0x00010000L
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK                                                 0x00020000L
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2_MASK                                                 0x00040000L
//SMN_MST_EP_CNTL5
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT                                         0x0
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT                                         0x1
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT                                         0x2
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT                                         0x3
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT                                         0x4
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT                                         0x5
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT                                         0x6
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT                                         0x7
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT                                         0x8
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT                                         0x9
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT                                         0xa
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT                                         0xb
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT                                         0xc
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT                                         0xd
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT                                         0xe
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT                                         0xf
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0__SHIFT                                         0x10
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1__SHIFT                                         0x11
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2__SHIFT                                         0x12
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3__SHIFT                                         0x13
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4__SHIFT                                         0x14
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5__SHIFT                                         0x15
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6__SHIFT                                         0x16
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7__SHIFT                                         0x17
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK                                           0x00000001L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK                                           0x00000002L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK                                           0x00000004L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK                                           0x00000008L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK                                           0x00000010L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK                                           0x00000020L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK                                           0x00000040L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK                                           0x00000080L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK                                           0x00000100L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK                                           0x00000200L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK                                           0x00000400L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK                                           0x00000800L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK                                           0x00001000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK                                           0x00002000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK                                           0x00004000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK                                           0x00008000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0_MASK                                           0x00010000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1_MASK                                           0x00020000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2_MASK                                           0x00040000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3_MASK                                           0x00080000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4_MASK                                           0x00100000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5_MASK                                           0x00200000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6_MASK                                           0x00400000L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7_MASK                                           0x00800000L
//BIF_SELFRING_BUFFER_VID
#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT                                                  0x0
#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT                                                    0x8
#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT                                          0x10
#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK                                                    0x000000FFL
#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK                                                      0x0000FF00L
#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK                                            0x00FF0000L
//BIF_SELFRING_VECTOR_CNTL
#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT                                                0x0
#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT                                                      0x1
#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK                                                  0x00000001L
#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK                                                        0x00000002L
//NBIF_INTX_DSTATE_MISC_CNTL
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT                                      0x0
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT                                      0x1
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT                                    0x2
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT                                         0x3
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT                                         0x4
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT                                                     0x5
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT                                                     0x6
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT                                                   0x7
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK                                        0x00000001L
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK                                        0x00000002L
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK                                      0x00000004L
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK                                           0x00000008L
#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK                                           0x00000010L
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK                                                       0x00000020L
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK                                                       0x00000040L
#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK                                                     0x00000080L
//NBIF_PENDING_MISC_CNTL
#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT                                                   0x0
#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT                                                   0x1
#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK                                                     0x00000001L
#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK                                                     0x00000002L
//BIF_GMI_WRR_WEIGHT
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT                                               0x1d
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT                                                       0x1e
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT                                                  0x1f
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK                                                 0x20000000L
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK                                                         0x40000000L
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK                                                    0x80000000L
//BIF_GMI_WRR_WEIGHT2
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT                                                     0x0
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT                                                     0x8
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT                                                     0x10
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT                                                     0x18
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK                                                       0x000000FFL
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK                                                       0x0000FF00L
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK                                                       0x00FF0000L
#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK                                                       0xFF000000L
//BIF_GMI_WRR_WEIGHT3
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT                                                     0x0
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT                                                     0x8
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT                                                     0x10
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT                                                     0x18
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK                                                       0x000000FFL
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK                                                       0x0000FF00L
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK                                                       0x00FF0000L
#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK                                                       0xFF000000L
//NBIF_PWRBRK_REQUEST
#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT                                                       0x0
#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK                                                         0x00000001L
//BIF_DMA_MP4_ERR_LOG
//BIF_PASID_ERR_LOG
//BIF_PASID_ERR_CLR
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT                                                       0x0
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT                                                       0x1
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT                                                       0x2
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT                                                       0x3
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4__SHIFT                                                       0x4
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5__SHIFT                                                       0x5
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6__SHIFT                                                       0x6
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7__SHIFT                                                       0x7
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0__SHIFT                                                       0x8
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1__SHIFT                                                       0x9
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0__SHIFT                                                       0x10
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1__SHIFT                                                       0x11
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2__SHIFT                                                       0x12
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F3__SHIFT                                                       0x13
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F4__SHIFT                                                       0x14
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F5__SHIFT                                                       0x15
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F6__SHIFT                                                       0x16
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK                                                         0x00000001L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK                                                         0x00000002L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK                                                         0x00000004L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK                                                         0x00000008L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4_MASK                                                         0x00000010L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5_MASK                                                         0x00000020L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6_MASK                                                         0x00000040L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7_MASK                                                         0x00000080L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0_MASK                                                         0x00000100L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1_MASK                                                         0x00000200L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0_MASK                                                         0x00010000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1_MASK                                                         0x00020000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2_MASK                                                         0x00040000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F3_MASK                                                         0x00080000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F4_MASK                                                         0x00100000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F5_MASK                                                         0x00200000L
#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F6_MASK                                                         0x00400000L
//OBFF_EMU_CFG
#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN__SHIFT                                                                 0x0
#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN_MASK                                                                   0x00000001L
//EP0_INTR_URGENT_CAP
#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE__SHIFT                                                   0x4
#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE__SHIFT                                                   0x6
#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE__SHIFT                                                   0x8
#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE__SHIFT                                                   0xa
#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE__SHIFT                                                   0xc
#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE__SHIFT                                                   0xe
#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE_MASK                                                     0x00000030L
#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE_MASK                                                     0x000000C0L
#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE_MASK                                                     0x00000300L
#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE_MASK                                                     0x00000C00L
#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE_MASK                                                     0x00003000L
#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE_MASK                                                     0x0000C000L
//EP1_INTR_URGENT_CAP
#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
//EP2_INTR_URGENT_CAP
#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE__SHIFT                                                   0x4
#define EP2_INTR_URGENT_CAP__EP2_F3_INTR_URGENT_MODE__SHIFT                                                   0x6
#define EP2_INTR_URGENT_CAP__EP2_F4_INTR_URGENT_MODE__SHIFT                                                   0x8
#define EP2_INTR_URGENT_CAP__EP2_F5_INTR_URGENT_MODE__SHIFT                                                   0xa
#define EP2_INTR_URGENT_CAP__EP2_F6_INTR_URGENT_MODE__SHIFT                                                   0xc
#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE_MASK                                                     0x00000030L
#define EP2_INTR_URGENT_CAP__EP2_F3_INTR_URGENT_MODE_MASK                                                     0x000000C0L
#define EP2_INTR_URGENT_CAP__EP2_F4_INTR_URGENT_MODE_MASK                                                     0x00000300L
#define EP2_INTR_URGENT_CAP__EP2_F5_INTR_URGENT_MODE_MASK                                                     0x00000C00L
#define EP2_INTR_URGENT_CAP__EP2_F6_INTR_URGENT_MODE_MASK                                                     0x00003000L
//EP_PEND_BLOCK_MSK
#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK__SHIFT                                                       0x0
#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK__SHIFT                                                       0x1
#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK__SHIFT                                                       0x2
#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK__SHIFT                                                       0x3
#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK__SHIFT                                                       0x4
#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK__SHIFT                                                       0x5
#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK__SHIFT                                                       0x6
#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK__SHIFT                                                       0x7
#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK__SHIFT                                                       0x8
#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK__SHIFT                                                       0x9
#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK__SHIFT                                                       0x10
#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK__SHIFT                                                       0x11
#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK__SHIFT                                                       0x12
#define EP_PEND_BLOCK_MSK__EP2_F3_PEND_BLOCK_MSK__SHIFT                                                       0x13
#define EP_PEND_BLOCK_MSK__EP2_F4_PEND_BLOCK_MSK__SHIFT                                                       0x14
#define EP_PEND_BLOCK_MSK__EP2_F5_PEND_BLOCK_MSK__SHIFT                                                       0x15
#define EP_PEND_BLOCK_MSK__EP2_F6_PEND_BLOCK_MSK__SHIFT                                                       0x16
#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK_MASK                                                         0x00000001L
#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK_MASK                                                         0x00000002L
#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK_MASK                                                         0x00000004L
#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK_MASK                                                         0x00000008L
#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK_MASK                                                         0x00000010L
#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK_MASK                                                         0x00000020L
#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK_MASK                                                         0x00000040L
#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK_MASK                                                         0x00000080L
#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK_MASK                                                         0x00000100L
#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK_MASK                                                         0x00000200L
#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK_MASK                                                         0x00010000L
#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK_MASK                                                         0x00020000L
#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK_MASK                                                         0x00040000L
#define EP_PEND_BLOCK_MSK__EP2_F3_PEND_BLOCK_MSK_MASK                                                         0x00080000L
#define EP_PEND_BLOCK_MSK__EP2_F4_PEND_BLOCK_MSK_MASK                                                         0x00100000L
#define EP_PEND_BLOCK_MSK__EP2_F5_PEND_BLOCK_MSK_MASK                                                         0x00200000L
#define EP_PEND_BLOCK_MSK__EP2_F6_PEND_BLOCK_MSK_MASK                                                         0x00400000L
//NBIF_VWIRE_CTRL
#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT                                                       0x4
#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT                                                                0x8
#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT                                                       0x14
#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT                                                              0x1a
#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK                                                         0x000000F0L
#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK                                                                  0x00000100L
#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK                                                         0x00F00000L
#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK                                                                0x0C000000L
//NBIF_MGCG_CTRL_LCLK
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT                                                         0x0
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT                                                       0x1
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT                                                 0x2
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT                                                    0xa
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT                                                    0xb
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT                                                    0xc
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT                                                    0xd
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK                                                           0x00000001L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK                                                         0x00000002L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK                                                   0x000003FCL
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK                                                      0x00000400L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK                                                      0x00000800L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK                                                      0x00001000L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK                                                      0x00002000L
//NBIF_DS_CTRL_LCLK
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT                                                             0x0
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT                                                          0x10
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK                                                               0x00000001L
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK                                                            0xFFFF0000L
//SMN_MST_CNTL0
#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT                                                                    0x0
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT                                                           0x8
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT                                                           0x9
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT                                                            0xa
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT                                                      0xb
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT                                                      0x10
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT                                                      0x11
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2__SHIFT                                                      0x12
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT                                                      0x14
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT                                                      0x15
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2__SHIFT                                                      0x16
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT                                                       0x18
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT                                                       0x19
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2__SHIFT                                                       0x1a
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT                                                 0x1c
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT                                                 0x1d
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2__SHIFT                                                 0x1e
#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK                                                                      0x00000003L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK                                                             0x00000100L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK                                                             0x00000200L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK                                                              0x00000400L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK                                                        0x00000800L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK                                                        0x00010000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK                                                        0x00020000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2_MASK                                                        0x00040000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK                                                        0x00100000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK                                                        0x00200000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2_MASK                                                        0x00400000L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK                                                         0x01000000L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK                                                         0x02000000L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2_MASK                                                         0x04000000L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK                                                   0x10000000L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK                                                   0x20000000L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2_MASK                                                   0x40000000L
//SMN_MST_EP_CNTL1
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT                                                 0x0
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT                                                 0x1
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT                                                 0x2
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT                                                 0x3
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT                                                 0x4
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT                                                 0x5
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT                                                 0x6
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT                                                 0x7
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT                                                 0x8
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT                                                 0x9
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT                                                 0xa
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT                                                 0xb
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT                                                 0xc
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT                                                 0xd
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT                                                 0xe
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT                                                 0xf
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0__SHIFT                                                 0x10
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1__SHIFT                                                 0x11
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2__SHIFT                                                 0x12
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3__SHIFT                                                 0x13
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4__SHIFT                                                 0x14
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5__SHIFT                                                 0x15
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6__SHIFT                                                 0x16
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7__SHIFT                                                 0x17
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK                                                   0x00000001L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK                                                   0x00000002L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK                                                   0x00000004L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK                                                   0x00000008L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK                                                   0x00000010L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK                                                   0x00000020L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK                                                   0x00000040L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK                                                   0x00000080L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK                                                   0x00000100L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK                                                   0x00000200L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK                                                   0x00000400L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK                                                   0x00000800L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK                                                   0x00001000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK                                                   0x00002000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK                                                   0x00004000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK                                                   0x00008000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0_MASK                                                   0x00010000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1_MASK                                                   0x00020000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2_MASK                                                   0x00040000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3_MASK                                                   0x00080000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4_MASK                                                   0x00100000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5_MASK                                                   0x00200000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6_MASK                                                   0x00400000L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7_MASK                                                   0x00800000L
//SMN_MST_EP_CNTL2
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT                                           0x0
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT                                           0x1
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT                                           0x2
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT                                           0x3
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT                                           0x4
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT                                           0x5
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT                                           0x6
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT                                           0x7
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT                                           0x8
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT                                           0x9
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT                                           0xa
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT                                           0xb
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT                                           0xc
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT                                           0xd
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT                                           0xe
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT                                           0xf
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0__SHIFT                                           0x10
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1__SHIFT                                           0x11
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2__SHIFT                                           0x12
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3__SHIFT                                           0x13
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4__SHIFT                                           0x14
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5__SHIFT                                           0x15
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6__SHIFT                                           0x16
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7__SHIFT                                           0x17
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK                                             0x00000001L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK                                             0x00000002L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK                                             0x00000004L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK                                             0x00000008L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK                                             0x00000010L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK                                             0x00000020L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK                                             0x00000040L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK                                             0x00000080L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK                                             0x00000100L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK                                             0x00000200L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK                                             0x00000400L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK                                             0x00000800L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK                                             0x00001000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK                                             0x00002000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK                                             0x00004000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK                                             0x00008000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0_MASK                                             0x00010000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1_MASK                                             0x00020000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2_MASK                                             0x00040000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3_MASK                                             0x00080000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4_MASK                                             0x00100000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5_MASK                                             0x00200000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6_MASK                                             0x00400000L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7_MASK                                             0x00800000L
//NBIF_SDP_VWR_VCHG_DIS_CTRL
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT                                           0x0
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT                                           0x1
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT                                           0x2
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT                                           0x3
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT                                           0x4
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT                                           0x5
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT                                           0x6
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT                                           0x7
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT                                           0x18
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK                                             0x00000001L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK                                             0x00000002L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK                                             0x00000004L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK                                             0x00000008L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK                                             0x00000010L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK                                             0x00000020L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK                                             0x00000040L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK                                             0x00000080L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK                                             0x01000000L
//NBIF_SDP_VWR_VCHG_RST_CTRL0
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT                                  0x0
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT                                  0x1
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT                                  0x2
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT                                  0x3
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT                                  0x4
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT                                  0x5
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT                                  0x6
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT                                  0x7
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT                                  0x18
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK                                    0x00000001L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK                                    0x00000002L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK                                    0x00000004L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK                                    0x00000008L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK                                    0x00000010L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK                                    0x00000020L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK                                    0x00000040L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK                                    0x00000080L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK                                    0x01000000L
//NBIF_SDP_VWR_VCHG_RST_CTRL1
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT                                 0x0
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT                                 0x1
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT                                 0x2
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT                                 0x3
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT                                 0x4
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT                                 0x5
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT                                 0x6
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT                                 0x7
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT                                 0x18
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK                                   0x00000001L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK                                   0x00000002L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK                                   0x00000004L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK                                   0x00000008L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK                                   0x00000010L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK                                   0x00000020L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK                                   0x00000040L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK                                   0x00000080L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK                                   0x01000000L
//NBIF_SDP_VWR_VCHG_TRIG
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT                                              0x0
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT                                              0x1
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT                                              0x2
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT                                              0x3
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT                                              0x4
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT                                              0x5
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT                                              0x6
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT                                              0x7
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT                                              0x18
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK                                                0x00000001L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK                                                0x00000002L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK                                                0x00000004L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK                                                0x00000008L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK                                                0x00000010L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK                                                0x00000020L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK                                                0x00000040L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK                                                0x00000080L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK                                                0x01000000L
//NBIF_SHUB_TODET_CTRL
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT                                                       0x0
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT                                               0x8
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT                                                  0x10
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK                                                         0x00000001L
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK                                                 0x00000700L
#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK                                                    0xFFFF0000L
//NBIF_SHUB_TODET_CLIENT_CTRL
#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT                                         0x0
#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK                                           0xFFFFFFFFL
//NBIF_SHUB_TODET_CLIENT_STATUS
#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT                                   0x0
#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK                                     0xFFFFFFFFL
//NBIF_SHUB_TODET_SYNCFLOOD_CTRL
#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT                                   0x0
#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK                                     0xFFFFFFFFL
//NBIF_SHUB_TODET_CLIENT_CTRL2
#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT                                       0x0
#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK                                         0xFFFFFFFFL
//NBIF_SHUB_TODET_CLIENT_STATUS2
#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT                                 0x0
#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK                                   0xFFFFFFFFL
//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2
#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT                                 0x0
#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK                                   0xFFFFFFFFL
//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
//DISCON_HYSTERESIS_HEAD_CTRL
#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x0
#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x8
#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x0000000FL
#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x00000F00L
//BIFC_Z10_CTRL0
#define BIFC_Z10_CTRL0__BIFC_Z10_IDLE_MASK__SHIFT                                                             0x0
#define BIFC_Z10_CTRL0__REGS_Z10_IDLE_ASSERT__SHIFT                                                           0x10
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_INTF_ACK_EN__SHIFT                                                     0x11
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_TIMEOUT_EN__SHIFT                                                  0x12
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_ASSERT__SHIFT                                                      0x13
#define BIFC_Z10_CTRL0__Z10_DS_ALLOW_EN_IN_PG__SHIFT                                                          0x1e
#define BIFC_Z10_CTRL0__BIFC_Z10_IDLE_MASK_MASK                                                               0x0000FFFFL
#define BIFC_Z10_CTRL0__REGS_Z10_IDLE_ASSERT_MASK                                                             0x00010000L
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_INTF_ACK_EN_MASK                                                       0x00020000L
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_TIMEOUT_EN_MASK                                                    0x00040000L
#define BIFC_Z10_CTRL0__REGS_Z10_FENCE_ACK_ASSERT_MASK                                                        0x00080000L
#define BIFC_Z10_CTRL0__Z10_DS_ALLOW_EN_IN_PG_MASK                                                            0x40000000L
//BIFC_Z10_CTRL1
#define BIFC_Z10_CTRL1__REGS_Z10_FENCE_ACK_TIMEOUT__SHIFT                                                     0x0
#define BIFC_Z10_CTRL1__REGS_Z10_FENCE_ACK_TIMEOUT_MASK                                                       0xFFFFFFFFL
//BIFC_Z10_STATUS
#define BIFC_Z10_STATUS__REGS_BIFC_Z10_STATUS__SHIFT                                                          0x0
#define BIFC_Z10_STATUS__REGS_BIFC_Z10_STATUS_MASK                                                            0xFFFFFFFFL
//BIFC_PCIE_BDF_CNTL0
#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0__SHIFT                                           0x0
#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1__SHIFT                                           0x10
#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0_MASK                                             0x0000FFFFL
#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1_MASK                                             0xFFFF0000L
//BIFC_PCIE_BDF_CNTL1
#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2__SHIFT                                           0x0
#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3__SHIFT                                           0x10
#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2_MASK                                             0x0000FFFFL
#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3_MASK                                             0xFFFF0000L
//BIFC_EARLY_WAKEUP_CNTL
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                     0x0
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                                    0x1
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                     0x2
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                       0x00000001L
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                      0x00000002L
#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                       0x00000004L
//BIFC_PERF_CNT_MMIO_RD_H16BIT
#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT                                    0x0
#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK                                      0x0000FFFFL
//BIFC_PERF_CNT_MMIO_WR_H16BIT
#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT                                    0x0
#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK                                      0x0000FFFFL
//BIFC_PERF_CNT_DMA_RD_H16BIT
#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT                                      0x0
#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK                                        0x0000FFFFL
//BIFC_PERF_CNT_DMA_WR_H16BIT
#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT                                      0x0
#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK                                        0x0000FFFFL
//NBIF_PERF_COM_COUNT_ENABLE
#define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT                                              0x0
#define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT                                                 0x3
#define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT                                            0x4
#define NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK                                                0x00000001L
#define NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK                                                   0x00000008L
#define NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK                                              0x00000010L
//NBIF_BX_PERF_CNT_FSM
#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT                                     0x4
#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT                                        0x8
#define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT                                                         0xa
#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK                                       0x000000F0L
#define NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK                                          0x00000100L
#define NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK                                                           0x00000400L
//NBIF_COM_COUNT_VALUE
#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT                                                     0x0
#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK                                                       0xFFFFFFFFL


// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
//SION_CL0_RdRsp_BurstTarget_REG0
#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL0_RdRsp_BurstTarget_REG1
#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL0_RdRsp_TimeSlot_REG0
#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL0_RdRsp_TimeSlot_REG1
#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL0_WrRsp_BurstTarget_REG0
#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL0_WrRsp_BurstTarget_REG1
#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL0_WrRsp_TimeSlot_REG0
#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL0_WrRsp_TimeSlot_REG1
#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL0_Req_BurstTarget_REG0
#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL0_Req_BurstTarget_REG1
#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL0_Req_TimeSlot_REG0
#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL0_Req_TimeSlot_REG1
#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL0_ReqPoolCredit_Alloc_REG0
#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL0_ReqPoolCredit_Alloc_REG1
#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL0_DataPoolCredit_Alloc_REG0
#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL0_DataPoolCredit_Alloc_REG1
#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL0_RdRspPoolCredit_Alloc_REG0
#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL0_RdRspPoolCredit_Alloc_REG1
#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL0_WrRspPoolCredit_Alloc_REG0
#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL0_WrRspPoolCredit_Alloc_REG1
#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL1_RdRsp_BurstTarget_REG0
#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL1_RdRsp_BurstTarget_REG1
#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL1_RdRsp_TimeSlot_REG0
#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL1_RdRsp_TimeSlot_REG1
#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL1_WrRsp_BurstTarget_REG0
#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL1_WrRsp_BurstTarget_REG1
#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL1_WrRsp_TimeSlot_REG0
#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL1_WrRsp_TimeSlot_REG1
#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL1_Req_BurstTarget_REG0
#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL1_Req_BurstTarget_REG1
#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL1_Req_TimeSlot_REG0
#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL1_Req_TimeSlot_REG1
#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL1_ReqPoolCredit_Alloc_REG0
#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL1_ReqPoolCredit_Alloc_REG1
#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL1_DataPoolCredit_Alloc_REG0
#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL1_DataPoolCredit_Alloc_REG1
#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL1_RdRspPoolCredit_Alloc_REG0
#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL1_RdRspPoolCredit_Alloc_REG1
#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL1_WrRspPoolCredit_Alloc_REG0
#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL1_WrRspPoolCredit_Alloc_REG1
#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL2_RdRsp_BurstTarget_REG0
#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL2_RdRsp_BurstTarget_REG1
#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL2_RdRsp_TimeSlot_REG0
#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL2_RdRsp_TimeSlot_REG1
#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL2_WrRsp_BurstTarget_REG0
#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL2_WrRsp_BurstTarget_REG1
#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL2_WrRsp_TimeSlot_REG0
#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL2_WrRsp_TimeSlot_REG1
#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL2_Req_BurstTarget_REG0
#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL2_Req_BurstTarget_REG1
#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL2_Req_TimeSlot_REG0
#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL2_Req_TimeSlot_REG1
#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL2_ReqPoolCredit_Alloc_REG0
#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL2_ReqPoolCredit_Alloc_REG1
#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL2_DataPoolCredit_Alloc_REG0
#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL2_DataPoolCredit_Alloc_REG1
#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL2_RdRspPoolCredit_Alloc_REG0
#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL2_RdRspPoolCredit_Alloc_REG1
#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL2_WrRspPoolCredit_Alloc_REG0
#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL2_WrRspPoolCredit_Alloc_REG1
#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CNTL_REG0
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT                                0x0
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT                                0x1
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT                                0x2
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT                                0x3
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT                                0x4
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT                                0x5
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT                                0x6
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT                                0x7
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT                                0x8
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT                                0x9
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT                                0xa
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT                                0xb
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT                                0xc
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT                                0xd
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT                                0xe
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT                                0xf
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT                                0x10
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT                                0x11
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT                                0x12
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT                                0x13
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK                                  0x00000001L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK                                  0x00000002L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK                                  0x00000004L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK                                  0x00000008L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK                                  0x00000010L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK                                  0x00000020L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK                                  0x00000040L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK                                  0x00000080L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK                                  0x00000100L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK                                  0x00000200L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK                                  0x00000400L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK                                  0x00000800L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK                                  0x00001000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK                                  0x00002000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK                                  0x00004000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK                                  0x00008000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK                                  0x00010000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK                                  0x00020000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK                                  0x00040000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK                                  0x00080000L
//SION_CNTL_REG1
#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT                                                    0x0
#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT                                                              0x8
#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK                                                      0x000000FFL
#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK                                                                0x0000FF00L


// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
//BIFL_RAS_CENTRAL_CNTL
#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT                                             0x1d
#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT                                                 0x1e
#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT                                      0x1f
#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK                                               0x20000000L
#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK                                                   0x40000000L
#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK                                        0x80000000L
//BIFL_RAS_CENTRAL_STATUS
#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT                                                  0x0
#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT                                                 0x1
#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT                                                  0x2
#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT                                                 0x3
#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT                                        0x1d
#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT                                            0x1e
#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT                                                     0x1f
#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK                                                    0x00000001L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK                                                   0x00000002L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK                                                    0x00000004L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK                                                   0x00000008L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK                                          0x20000000L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK                                              0x40000000L
#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK                                                       0x80000000L
//BIFL_RAS_LEAF0_CTRL
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
#define BIFL_RAS_LEAF0_CTRL__POISON_DBUG_EN__SHIFT                                                            0xc
#define BIFL_RAS_LEAF0_CTRL__PARITY_DBUG_EN__SHIFT                                                            0xd
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
#define BIFL_RAS_LEAF0_CTRL__POISON_DBUG_EN_MASK                                                              0x00001000L
#define BIFL_RAS_LEAF0_CTRL__PARITY_DBUG_EN_MASK                                                              0x00002000L
#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
//BIFL_RAS_LEAF1_CTRL
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
#define BIFL_RAS_LEAF1_CTRL__POISON_DBUG_EN__SHIFT                                                            0xc
#define BIFL_RAS_LEAF1_CTRL__PARITY_DBUG_EN__SHIFT                                                            0xd
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
#define BIFL_RAS_LEAF1_CTRL__POISON_DBUG_EN_MASK                                                              0x00001000L
#define BIFL_RAS_LEAF1_CTRL__PARITY_DBUG_EN_MASK                                                              0x00002000L
#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
//BIFL_RAS_LEAF2_CTRL
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
#define BIFL_RAS_LEAF2_CTRL__POISON_DBUG_EN__SHIFT                                                            0xc
#define BIFL_RAS_LEAF2_CTRL__PARITY_DBUG_EN__SHIFT                                                            0xd
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
#define BIFL_RAS_LEAF2_CTRL__POISON_DBUG_EN_MASK                                                              0x00001000L
#define BIFL_RAS_LEAF2_CTRL__PARITY_DBUG_EN_MASK                                                              0x00002000L
#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
//BIFL_RAS_LEAF0_STATUS
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
//BIFL_RAS_LEAF1_STATUS
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
//BIFL_RAS_LEAF2_STATUS
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
//BIFL_IOHUB_RAS_IH_CNTL
#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT                                                    0x0
#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK                                                      0x00000001L
//BIFL_RAS_VWR_FROM_IOHUB
#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT                                                 0x0
#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK                                                   0x00000001L


// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV0_1_DN_PCIE_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
//RCC_EP_DEV0_1_EP_PCIE_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_bif_bx_SYSDEC
//BIF_BX0_PCIE_INDEX
#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
//BIF_BX0_PCIE_DATA
#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
//BIF_BX0_PCIE_INDEX2
#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
//BIF_BX0_PCIE_DATA2
#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
//BIF_BX0_SBIOS_SCRATCH_0
#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX0_SBIOS_SCRATCH_1
#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX0_SBIOS_SCRATCH_2
#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX0_SBIOS_SCRATCH_3
#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_0
#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_1
#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_2
#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_3
#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_4
#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_5
#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_6
#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_7
#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_8
#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_9
#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_10
#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_11
#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_12
#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_13
#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_14
#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIOS_SCRATCH_15
#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
//BIF_BX0_BIF_RLC_INTR_CNTL
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX0_BIF_VCE_INTR_CNTL
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX0_BIF_UVD_INTR_CNTL
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
//BIF_BX0_GFX_MMIOREG_CAM_ADDR0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR1
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR2
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR3
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR4
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR5
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR6
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ADDR7
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_CNTL
#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL
#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL
#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL


// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
//BIF_BX_PF0_MM_INDEX
#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
//BIF_BX_PF0_MM_DATA
#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT                                                                    0x0
#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
//BIF_BX_PF0_MM_INDEX_HI
#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
//BIF_BX_PF0_RSMU_INDEX
#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT                                                              0x0
#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK                                                                0xFFFFFFFFL
//BIF_BX_PF0_RSMU_DATA
#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT                                                                0x0
#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK                                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
//BIF_BX0_BIF_MM_INDACCESS_CNTL
#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
//BIF_BX0_BUS_CNTL
#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
//BIF_BX0_BIF_SCRATCH0
#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
//BIF_BX0_BIF_SCRATCH1
#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
//BIF_BX0_BX_RESET_EN
#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
//BIF_BX0_MM_CFGREGS_CNTL
#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
//BIF_BX0_BX_RESET_CNTL
#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
//BIF_BX0_INTERRUPT_CNTL
#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                          0x8
#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                            0x00000100L
#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
//BIF_BX0_INTERRUPT_CNTL2
#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_BX0_CLKREQB_PAD_CNTL
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
//BIF_BX0_BIF_FEATURES_CONTROL_MISC
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
//BIF_BX0_HDP_ATOMIC_CONTROL_MISC
#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT                                      0x0
#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK                                        0x000000FFL
//BIF_BX0_BIF_DOORBELL_CNTL
#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
//BIF_BX0_BIF_DOORBELL_INT_CNTL
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                              0x1f
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK                                0x80000000L
//BIF_BX0_BIF_FB_EN
#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
//BIF_BX0_BIF_INTR_CNTL
#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
//BIF_BX0_BIF_MST_TRANS_PENDING_VF
#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX0_BIF_SLV_TRANS_PENDING_VF
#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX0_BACO_CNTL
#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
#define BIF_BX0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                        0x1
#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
#define BIF_BX0_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
#define BIF_BX0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                          0x00000002L
#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
//BIF_BX0_BIF_BACO_EXIT_TIME0
#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
//BIF_BX0_BIF_BACO_EXIT_TIMER1
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
//BIF_BX0_BIF_BACO_EXIT_TIMER2
#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
//BIF_BX0_BIF_BACO_EXIT_TIMER3
#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
//BIF_BX0_BIF_BACO_EXIT_TIMER4
#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
//BIF_BX0_MEM_TYPE_CNTL
#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
//BIF_BX0_NBIF_GFX_ADDR_LUT_0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_1
#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_2
#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_3
#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_4
#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_5
#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_6
#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_7
#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_8
#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_9
#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_10
#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_11
#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_12
#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_13
#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_14
#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_NBIF_GFX_ADDR_LUT_15
#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX0_GFX_RST_CNTL
#define BIF_BX0_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT                                                0x0
#define BIF_BX0_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK                                                  0x00000001L
//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX0_BIF_RB_CNTL
#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
//BIF_BX0_BIF_RB_BASE
#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
#define BIF_BX0_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
//BIF_BX0_BIF_RB_RPTR
#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX0_BIF_RB_WPTR
#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX0_BIF_RB_WPTR_ADDR_HI
#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
//BIF_BX0_BIF_RB_WPTR_ADDR_LO
#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
//BIF_BX0_MAILBOX_INDEX
#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
//BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
#define BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                 0x0
#define BIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                   0x0000000FL
//BIF_BX0_BIF_PERSTB_PAD_CNTL
#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
//BIF_BX0_BIF_PX_EN_PAD_CNTL
#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x000000FFL
//BIF_BX0_BIF_REFPADKIN_PAD_CNTL
#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
//BIF_BX0_BIF_CLKREQB_PAD_CNTL
#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x00FFFFFFL
//BIF_BX0_BIF_PWRBRK_PAD_CNTL
#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL


// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
//BIF_BX_PF0_BIF_BME_STATUS
#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
//BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
//BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
//BIF_BX_PF0_BIF_TRANS_PENDING
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS
#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_CONTROL
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
//BIF_BX_PF0_MAILBOX_INT_CNTL
#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
//BIF_BX_PF0_BIF_VMHV_MAILBOX
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L


// addressBlock: nbio_nbif0_bif_bx_SYSDEC:1
//BIF_BX1_PCIE_INDEX
#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
//BIF_BX1_PCIE_DATA
#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
//BIF_BX1_PCIE_INDEX2
#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
//BIF_BX1_PCIE_DATA2
#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
//BIF_BX1_SBIOS_SCRATCH_0
#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX1_SBIOS_SCRATCH_1
#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX1_SBIOS_SCRATCH_2
#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX1_SBIOS_SCRATCH_3
#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_0
#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_1
#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_2
#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_3
#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_4
#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_5
#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_6
#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_7
#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_8
#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_9
#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_10
#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_11
#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_12
#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_13
#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_14
#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIOS_SCRATCH_15
#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
//BIF_BX1_BIF_RLC_INTR_CNTL
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX1_BIF_VCE_INTR_CNTL
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX1_BIF_UVD_INTR_CNTL
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
//BIF_BX1_GFX_MMIOREG_CAM_ADDR0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR1
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR2
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR3
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR4
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR5
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR6
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ADDR7
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_CNTL
#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL
#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL
#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1
//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV0_2_DN_PCIE_CNTL
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1
//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1
//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
//RCC_EP_DEV0_2_EP_PCIE_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
//BIF_BX_PF1_MM_INDEX
#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
//BIF_BX_PF1_MM_DATA
#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT                                                                    0x0
#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
//BIF_BX_PF1_MM_INDEX_HI
#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL


// addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1
//BIF_BX1_BIF_MM_INDACCESS_CNTL
#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
//BIF_BX1_BUS_CNTL
#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
//BIF_BX1_BIF_SCRATCH0
#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
//BIF_BX1_BIF_SCRATCH1
#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
//BIF_BX1_BX_RESET_EN
#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
//BIF_BX1_MM_CFGREGS_CNTL
#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
//BIF_BX1_BX_RESET_CNTL
#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
//BIF_BX1_INTERRUPT_CNTL
#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                          0x8
#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                            0x00000100L
#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
//BIF_BX1_INTERRUPT_CNTL2
#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_BX1_CLKREQB_PAD_CNTL
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
//BIF_BX1_BIF_FEATURES_CONTROL_MISC
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
//BIF_BX1_HDP_ATOMIC_CONTROL_MISC
#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT                                      0x0
#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK                                        0x000000FFL
//BIF_BX1_BIF_DOORBELL_CNTL
#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
//BIF_BX1_BIF_DOORBELL_INT_CNTL
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                              0x1f
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK                                0x80000000L
//BIF_BX1_BIF_FB_EN
#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
//BIF_BX1_BIF_INTR_CNTL
#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
//BIF_BX1_BIF_MST_TRANS_PENDING_VF
#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX1_BIF_SLV_TRANS_PENDING_VF
#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX1_BACO_CNTL
#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
#define BIF_BX1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                        0x1
#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
#define BIF_BX1_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
#define BIF_BX1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                          0x00000002L
#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
//BIF_BX1_BIF_BACO_EXIT_TIME0
#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
//BIF_BX1_BIF_BACO_EXIT_TIMER1
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
//BIF_BX1_BIF_BACO_EXIT_TIMER2
#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
//BIF_BX1_BIF_BACO_EXIT_TIMER3
#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
//BIF_BX1_BIF_BACO_EXIT_TIMER4
#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
//BIF_BX1_MEM_TYPE_CNTL
#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
//BIF_BX1_NBIF_GFX_ADDR_LUT_0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_1
#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_2
#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_3
#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_4
#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_5
#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_6
#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_7
#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_8
#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_9
#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_10
#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_11
#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_12
#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_13
#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_14
#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_NBIF_GFX_ADDR_LUT_15
#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX1_GFX_RST_CNTL
#define BIF_BX1_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT                                                0x0
#define BIF_BX1_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK                                                  0x00000001L
//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL
#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL
#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX1_BIF_RB_CNTL
#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
//BIF_BX1_BIF_RB_BASE
#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
#define BIF_BX1_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
//BIF_BX1_BIF_RB_RPTR
#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX1_BIF_RB_WPTR
#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX1_BIF_RB_WPTR_ADDR_HI
#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
//BIF_BX1_BIF_RB_WPTR_ADDR_LO
#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
//BIF_BX1_MAILBOX_INDEX
#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
//BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                 0x0
#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                   0x0000000FL
//BIF_BX1_BIF_PERSTB_PAD_CNTL
#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
//BIF_BX1_BIF_PX_EN_PAD_CNTL
#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x000000FFL
//BIF_BX1_BIF_REFPADKIN_PAD_CNTL
#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
//BIF_BX1_BIF_CLKREQB_PAD_CNTL
#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x00FFFFFFL
//BIF_BX1_BIF_PWRBRK_PAD_CNTL
#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL


// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1
//BIF_BX_PF1_BIF_BME_STATUS
#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
//BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
//BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
//BIF_BX_PF1_BIF_TRANS_PENDING
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS
#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_CONTROL
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
//BIF_BX_PF1_MAILBOX_INT_CNTL
#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
//BIF_BX_PF1_BIF_VMHV_MAILBOX
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L


// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN
#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                     0x0
#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                       0x00000001L
//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE
#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                             0x0
#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                               0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1
//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif0_gdc_GDCDEC
//GDC0_A2S_QUEUE_FIFO_ARB_CNTL
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x0
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x8
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x10
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x11
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x000000FFL
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x0000FF00L
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00010000L
#define GDC0_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00020000L
//GDC0_NBIF_GFX_DOORBELL_STATUS
#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                          0x0
#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                            0x00000001L
//GDC0_BIF_SDMA0_DOORBELL_RANGE
#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_SDMA1_DOORBELL_RANGE
#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_IH_DOORBELL_RANGE
#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
//GDC0_BIF_VCN0_DOORBELL_RANGE
#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC0_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC0_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC0_BIF_RLC_DOORBELL_RANGE
#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC0_BIF_SDMA2_DOORBELL_RANGE
#define GDC0_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_SDMA3_DOORBELL_RANGE
#define GDC0_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_VCN1_DOORBELL_RANGE
#define GDC0_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC0_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC0_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC0_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC0_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC0_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC0_BIF_SDMA4_DOORBELL_RANGE
#define GDC0_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_SDMA5_DOORBELL_RANGE
#define GDC0_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC0_BIF_CSDMA_DOORBELL_RANGE
#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC0_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC0_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
//GDC0_BIF_VPE_DOORBELL_RANGE
#define GDC0_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC0_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC0_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC0_BIF_VPE_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC0_ATDMA_MISC_CNTL
#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
#define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT                                                           0x2
#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT                                                           0x8
#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT                                                           0x10
#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT                                                           0x18
#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK                                                               0x00000001L
#define GDC0_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK                                   0x00000002L
#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK                                                             0x0000000CL
#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK                                                             0x0000FF00L
#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK                                                             0x00FF0000L
#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK                                                             0xFF000000L
//GDC0_BIF_DOORBELL_FENCE_CNTL
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT                                         0x0
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT                                      0x1
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT                                      0x2
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT                                        0x4
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT                                      0x5
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT                                      0x6
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT                                      0x7
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT                                      0x8
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT                                      0x9
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT                                        0xa
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                  0x10
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK                                           0x00000001L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK                                        0x00000002L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK                                        0x00000004L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK                                          0x00000010L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK                                        0x00000020L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK                                        0x00000040L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK                                        0x00000080L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK                                        0x00000100L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK                                        0x00000200L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK                                          0x00000400L
#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                    0x00010000L
//GDC0_S2A_MISC_CNTL
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                           0x0
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                           0x1
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                              0x2
#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                         0x3
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT                                             0x5
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS__SHIFT                                             0x6
#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT                                           0x18
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT                                           0x19
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT                                           0x1a
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT                                           0x1b
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS__SHIFT                                           0x1c
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                             0x00000001L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                             0x00000002L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                0x00000004L
#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                           0x00000008L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK                                               0x00000020L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS_MASK                                               0x00000040L
#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK                                             0x01000000L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK                                             0x02000000L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK                                             0x04000000L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK                                             0x08000000L
#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS_MASK                                             0x10000000L


// addressBlock: nbio_nbif0_gdc_GDC_LINEAR_REGION
//GDC1_A2S_QUEUE_FIFO_ARB_CNTL
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x0
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x8
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x10
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x11
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x000000FFL
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x0000FF00L
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00010000L
#define GDC1_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00020000L
//GDC1_NBIF_GFX_DOORBELL_STATUS
#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                          0x0
#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                            0x00000001L
//GDC1_BIF_SDMA0_DOORBELL_RANGE
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_SDMA1_DOORBELL_RANGE
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_IH_DOORBELL_RANGE
#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
//GDC1_BIF_VCN0_DOORBELL_RANGE
#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC1_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC1_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC1_BIF_RLC_DOORBELL_RANGE
#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC1_BIF_SDMA2_DOORBELL_RANGE
#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_SDMA3_DOORBELL_RANGE
#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_VCN1_DOORBELL_RANGE
#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC1_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC1_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC1_BIF_SDMA4_DOORBELL_RANGE
#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_SDMA5_DOORBELL_RANGE
#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_CSDMA_DOORBELL_RANGE
#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
//GDC1_BIF_VPE_DOORBELL_RANGE
#define GDC1_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC1_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC1_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC1_BIF_VPE_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC1_ATDMA_MISC_CNTL
#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
#define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT                                                           0x2
#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT                                                           0x8
#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT                                                           0x10
#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT                                                           0x18
#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK                                                               0x00000001L
#define GDC1_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK                                   0x00000002L
#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK                                                             0x0000000CL
#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK                                                             0x0000FF00L
#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK                                                             0x00FF0000L
#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK                                                             0xFF000000L
//GDC1_BIF_DOORBELL_FENCE_CNTL
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT                                         0x0
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT                                      0x1
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT                                      0x2
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT                                        0x4
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT                                      0x5
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT                                      0x6
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT                                      0x7
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT                                      0x8
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT                                      0x9
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT                                        0xa
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                  0x10
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK                                           0x00000001L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK                                        0x00000002L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK                                        0x00000004L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK                                          0x00000010L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK                                        0x00000020L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK                                        0x00000040L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK                                        0x00000080L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK                                        0x00000100L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK                                        0x00000200L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK                                          0x00000400L
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                    0x00010000L
//GDC1_S2A_MISC_CNTL
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                           0x0
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                           0x1
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                              0x2
#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                         0x3
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT                                             0x5
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS__SHIFT                                             0x6
#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT                                           0x18
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT                                           0x19
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT                                           0x1a
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT                                           0x1b
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS__SHIFT                                           0x1c
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                             0x00000001L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                             0x00000002L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                0x00000004L
#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                           0x00000008L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK                                               0x00000020L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_VPE_DIS_MASK                                               0x00000040L
#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK                                             0x01000000L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK                                             0x02000000L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK                                             0x04000000L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK                                             0x08000000L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CSDMA_DIS_MASK                                             0x10000000L


// addressBlock: nbio_nbif0_bif_bx_SYSDEC
//BIF_BX2_PCIE_INDEX
#define BIF_BX2_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
#define BIF_BX2_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
//BIF_BX2_PCIE_DATA
#define BIF_BX2_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
#define BIF_BX2_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
//BIF_BX2_PCIE_INDEX2
#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
//BIF_BX2_PCIE_DATA2
#define BIF_BX2_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
#define BIF_BX2_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
//BIF_BX2_SBIOS_SCRATCH_0
#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX2_SBIOS_SCRATCH_1
#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX2_SBIOS_SCRATCH_2
#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX2_SBIOS_SCRATCH_3
#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_0
#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_1
#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_2
#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_3
#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_4
#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_5
#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_6
#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_7
#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_8
#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_9
#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_10
#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_11
#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_12
#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_13
#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_14
#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIOS_SCRATCH_15
#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
//BIF_BX2_BIF_RLC_INTR_CNTL
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX2_BIF_VCE_INTR_CNTL
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
//BIF_BX2_BIF_UVD_INTR_CNTL
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
//BIF_BX2_GFX_MMIOREG_CAM_ADDR0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR1
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR2
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR3
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR4
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR5
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR6
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ADDR7
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_CNTL
#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
//BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL
#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL
#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
//BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
//RCC_DWN_DEV0_3_DN_PCIE_RESERVED
#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
//RCC_DWN_DEV0_3_DN_PCIE_SCRATCH
#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV0_3_DN_PCIE_CNTL
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
//RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
//RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
//RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
//RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L


// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
//RCC_DWNP_DEV0_3_PCIE_ERR_CNTL
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
//RCC_DWNP_DEV0_3_PCIE_RX_CNTL
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
//RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL
//RCC_DWNP_DEV0_3_PCIE_LC_CNTL2
#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
//RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL


// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
//RCC_EP_DEV0_3_EP_PCIE_SCRATCH
#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
//RCC_EP_DEV0_3_EP_PCIE_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
//RCC_EP_DEV0_3_EP_PCIE_INT_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
//RCC_EP_DEV0_3_EP_PCIE_INT_STATUS
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
//RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
//RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
//RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
//RCC_EP_DEV0_3_EP_PCIEP_RESERVED
#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_EP_DEV0_3_EP_PCIE_TX_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
//RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
//RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
//RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL


// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
//BIF_BX_PF2_MM_INDEX
#define BIF_BX_PF2_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
#define BIF_BX_PF2_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
#define BIF_BX_PF2_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
#define BIF_BX_PF2_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
//BIF_BX_PF2_MM_DATA
#define BIF_BX_PF2_MM_DATA__MM_DATA__SHIFT                                                                    0x0
#define BIF_BX_PF2_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
//BIF_BX_PF2_MM_INDEX_HI
#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL


// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
//BIF_BX2_BIF_MM_INDACCESS_CNTL
#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
//BIF_BX2_BUS_CNTL
#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
#define BIF_BX2_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
#define BIF_BX2_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
#define BIF_BX2_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
#define BIF_BX2_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
//BIF_BX2_BIF_SCRATCH0
#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
//BIF_BX2_BIF_SCRATCH1
#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
//BIF_BX2_BX_RESET_EN
#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
//BIF_BX2_MM_CFGREGS_CNTL
#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
//BIF_BX2_BX_RESET_CNTL
#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
//BIF_BX2_INTERRUPT_CNTL
#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
#define BIF_BX2_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                          0x8
#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
#define BIF_BX2_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                            0x00000100L
#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
//BIF_BX2_INTERRUPT_CNTL2
#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_BX2_CLKREQB_PAD_CNTL
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
//BIF_BX2_BIF_FEATURES_CONTROL_MISC
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
//BIF_BX2_HDP_ATOMIC_CONTROL_MISC
#define BIF_BX2_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT                                      0x0
#define BIF_BX2_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK                                        0x000000FFL
//BIF_BX2_BIF_DOORBELL_CNTL
#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
//BIF_BX2_BIF_DOORBELL_INT_CNTL
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                              0x1f
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
#define BIF_BX2_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK                                0x80000000L
//BIF_BX2_BIF_FB_EN
#define BIF_BX2_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
#define BIF_BX2_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
//BIF_BX2_BIF_INTR_CNTL
#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
//BIF_BX2_BIF_MST_TRANS_PENDING_VF
#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX2_BIF_SLV_TRANS_PENDING_VF
#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
//BIF_BX2_BACO_CNTL
#define BIF_BX2_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                        0x1
#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
#define BIF_BX2_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
#define BIF_BX2_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                          0x00000002L
#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
#define BIF_BX2_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
//BIF_BX2_BIF_BACO_EXIT_TIME0
#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
//BIF_BX2_BIF_BACO_EXIT_TIMER1
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
//BIF_BX2_BIF_BACO_EXIT_TIMER2
#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
//BIF_BX2_BIF_BACO_EXIT_TIMER3
#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
//BIF_BX2_BIF_BACO_EXIT_TIMER4
#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
//BIF_BX2_MEM_TYPE_CNTL
#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
//BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
//BIF_BX2_NBIF_GFX_ADDR_LUT_0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_1
#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_2
#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_3
#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_4
#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_5
#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_6
#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_7
#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_8
#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_9
#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_10
#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_11
#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_12
#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_13
#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_14
#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_NBIF_GFX_ADDR_LUT_15
#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
//BIF_BX2_GFX_RST_CNTL
#define BIF_BX2_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION__SHIFT                                                0x0
#define BIF_BX2_GFX_RST_CNTL__GFX_RST_FINISH_INDICATION_MASK                                                  0x00000001L
//BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL
#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL
#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
//BIF_BX2_BIF_RB_CNTL
#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
#define BIF_BX2_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
#define BIF_BX2_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
//BIF_BX2_BIF_RB_BASE
#define BIF_BX2_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
#define BIF_BX2_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
//BIF_BX2_BIF_RB_RPTR
#define BIF_BX2_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX2_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX2_BIF_RB_WPTR
#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
#define BIF_BX2_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
#define BIF_BX2_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
//BIF_BX2_BIF_RB_WPTR_ADDR_HI
#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
//BIF_BX2_BIF_RB_WPTR_ADDR_LO
#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
//BIF_BX2_MAILBOX_INDEX
#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
//BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                 0x0
#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                   0x0000000FL
//BIF_BX2_BIF_PERSTB_PAD_CNTL
#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
//BIF_BX2_BIF_PX_EN_PAD_CNTL
#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x000000FFL
//BIF_BX2_BIF_REFPADKIN_PAD_CNTL
#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
//BIF_BX2_BIF_CLKREQB_PAD_CNTL
#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x00FFFFFFL
//BIF_BX2_BIF_PWRBRK_PAD_CNTL
#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL


// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
//RCC_STRAP3_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
//BIF_BX_PF2_BIF_BME_STATUS
#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
//BIF_BX_PF2_BIF_ATOMIC_ERR_LOG
//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
//BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
//BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
//BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
//BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
//BIF_BX_PF2_GPU_HDP_FLUSH_REQ
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
//BIF_BX_PF2_GPU_HDP_FLUSH_DONE
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
//BIF_BX_PF2_BIF_TRANS_PENDING
#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
//BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS
#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF2_MAILBOX_CONTROL
#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
//BIF_BX_PF2_MAILBOX_INT_CNTL
#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
//BIF_BX_PF2_BIF_VMHV_MAILBOX
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L


// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN
#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                     0x0
#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                       0x00000001L
//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE
#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                             0x0
#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                               0xFFFFFFFFL


// addressBlock: nbio_nbif0_gdc_GDCDEC
//GDC2_A2S_QUEUE_FIFO_ARB_CNTL
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x0
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                   0x8
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x10
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                       0x11
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x000000FFL
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                     0x0000FF00L
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00010000L
#define GDC2_A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK                                         0x00020000L
//GDC2_NBIF_GFX_DOORBELL_STATUS
#define GDC2_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                          0x0
#define GDC2_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                            0x00000001L
//GDC2_BIF_SDMA0_DOORBELL_RANGE
#define GDC2_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_SDMA1_DOORBELL_RANGE
#define GDC2_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_IH_DOORBELL_RANGE
#define GDC2_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
#define GDC2_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
#define GDC2_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
#define GDC2_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
//GDC2_BIF_VCN0_DOORBELL_RANGE
#define GDC2_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC2_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC2_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC2_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC2_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC2_BIF_VCN0_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC2_BIF_RLC_DOORBELL_RANGE
#define GDC2_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC2_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC2_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC2_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC2_BIF_SDMA2_DOORBELL_RANGE
#define GDC2_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_SDMA3_DOORBELL_RANGE
#define GDC2_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_VCN1_DOORBELL_RANGE
#define GDC2_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
#define GDC2_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
#define GDC2_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT__SHIFT                                                      0x15
#define GDC2_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
#define GDC2_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
#define GDC2_BIF_VCN1_DOORBELL_RANGE__NEED_DEDUCT_MASK                                                        0x00200000L
//GDC2_BIF_SDMA4_DOORBELL_RANGE
#define GDC2_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_SDMA5_DOORBELL_RANGE
#define GDC2_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC2_BIF_CSDMA_DOORBELL_RANGE
#define GDC2_BIF_CSDMA_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC2_BIF_CSDMA_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC2_BIF_CSDMA_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC2_BIF_CSDMA_DOORBELL_RANGE__SIZE_MASK                                                              0x00FF0000L
//GDC2_BIF_VPE_DOORBELL_RANGE
#define GDC2_BIF_VPE_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
#define GDC2_BIF_VPE_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
#define GDC2_BIF_VPE_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
#define GDC2_BIF_VPE_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
//GDC2_ATDMA_MISC_CNTL
#define GDC2_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
#define GDC2_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                 0x1
#define GDC2_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT                                                           0x2
#define GDC2_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT                                                           0x8
#define GDC2_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT                                                           0x10
#define GDC2_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT                                                           0x18
#define GDC2_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK                                                               0x00000001L
#define GDC2_ATDMA_MISC_CNTL__ATDMA_MISC_CNTL_INSERT_RD_ON_2ND_WDAT_EN_MASK                                   0x00000002L
#define GDC2_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK                                                             0x0000000CL
#define GDC2_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK                                                             0x0000FF00L
#define GDC2_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK                                                             0x00FF0000L
#define GDC2_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK                                                             0xFF000000L
//GDC2_BIF_DOORBELL_FENCE_CNTL
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT                                         0x0
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT                                      0x1
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT                                      0x2
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT                                        0x4
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT                                      0x5
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT                                      0x6
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT                                      0x7
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT                                      0x8
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE__SHIFT                                      0x9
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE__SHIFT                                        0xa
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                  0x10
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK                                           0x00000001L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK                                        0x00000002L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK                                        0x00000004L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK                                          0x00000010L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK                                        0x00000020L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK                                        0x00000040L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK                                        0x00000080L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK                                        0x00000100L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CSDMA_ENABLE_MASK                                        0x00000200L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_VPE_ENABLE_MASK                                          0x00000400L
#define GDC2_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                    0x00010000L


#endif