)]}'
{
  "commit": "b2d929a1c2a887dd046e0af2d4a06dbf4e7d87a6",
  "tree": "14f01a6ab6f0cb190206c1f3936392ae775da7b0",
  "parents": [
    "b88c841d11641923fa3a4da011d7202cd89df68a",
    "d4f25b097e46d82718bb737d4540c99b7ab0a408"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sun Oct 11 08:13:52 2026 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sun Oct 11 08:13:52 2026 -0700"
  },
  "message": "Merge tag \u0027riscv-for-linus-7.3-rc7\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux\n\nPull RISC-V fixes from Paul Walmsley:\n \"Several security fixes, a significant strnlen() regression fix, and\n  several other miscellaneous fixes:\n\n   - Fix a regression in the Zbb-enabled strnlen() implementation when\n     huge counts are specified\n\n   - When userspace pointer masking is enabled, strip the tag from\n     user-specified pointers in two spots in the RISC-V futex code where\n     this was missing\n\n   - When CONFIG_SHADOW_CALL_STACK\u003dy, use a supervisor mode-only CSR bit\n     to determine whether the trap came from userspace or not, rather\n     than a userspace-writable register\n\n   - Reset the HSTATUS.HU bit during CPU initialization to avoid\n     unexpected behavior, as the RISC-V specification does not require\n     this bit to be hardware-reset\n\n   - Fix the T-Head GhostWrite probing code when\n     !CONFIG_ERRATA_THEAD_MAE\n\n   - Fix RV32 boots using 32-bit.config by constraining NR_CPUS\n\n   - Implement a workaround for SiFive MAL-9092, which requires fences\n     around hypervisor load/store instructions\n\n   - Fix the RISC-V patch_map() code to work properly for EXECMEM\n     addresses when !CONFIG_STRICT_MODULE_RWX\n\n   - Fix ptrace register set access reporting when CFI landing pad or\n     shadow stack support is enabled\n\n   - Avoid copying garbage into the target\u0027s vstate when\n     PTRACE_SETREGSET is called with a short iov_len\n\n   - Fix load_unaligned_zeropad() on RV32 kernels with\n     CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS\u003dy\n\n   - Fix build breakage for any userspace program that includes\n     uapi/asm/vendor/mips.h\n\n   - Fix a build warning for 32-bit allmodconfig builds related to\n     SiFive errata\n\n   - Fix misspecified inline assembly constraints in the vector context\n     save/restore code\"\n\n* tag \u0027riscv-for-linus-7.3-rc7\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:\n  riscv: fix load_unaligned_zeropad() fixup for RV32\n  riscv: entry: gate shadow call stack reload on sstatus.SPP, not tp\n  riscv: ptrace: Zero-initialize regset buffers before copyin\n  riscv: ptrace: reject CFI regset access when extensions are absent\n  riscv: fix NR_CPUS range leaking 64-bit default onto 32-bit builds\n  riscv: errata: select RISCV_ALTERNATIVE_EARLY for THEAD GHOSTWRITE\n  riscv: futex: untag the user pointer before the atomic access\n  riscv: lib: Fix ZBB strnlen wrap-around regression on huge counts\n  riscv: patch: fix handling of bpf-jit execmem addresses\n  RISC-V: Clear HSTATUS.HU on CPU initialization\n  RISC-V: errata: Add SiFive MAL-9092 workaround\n  riscv: vector: Fix output operands in context save\n  riscv: vector: Fix data pointer constraints in context save/restore\n  riscv: limit sifive errata to CONFIG_64BIT\n  riscv: hwprobe: use _BITULL() rather than BIT() in MIPS vendor uapi header\n",
  "tree_diff": []
}