// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 NXP
 */

/dts-v1/;

#include "imx93.dtsi"

/ {
	model = "NXP i.MX93 11X11 EVK board";
	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";

	chosen {
		stdout-path = &lpuart1;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&mu1 {
	status = "okay";
};

&mu2 {
	status = "okay";
};

&lpuart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
	no-sdio;
	no-mmc;
};

&iomuxc {
	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17fe
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x17fe
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17fe
			MX93_PAD_SD2_CMD__USDHC2_CMD		0x13fe
			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};
};