)]}'
{
  "commit": "b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058",
  "tree": "b3eed584ffa7dfc38ccb617ef5fc795741630bf1",
  "parents": [
    "4c45852f494dab827291c656ee9e12f3f4ee64d6"
  ],
  "author": {
    "name": "Gabriele Paoloni",
    "email": "gabriele.paoloni@huawei.com",
    "time": "Thu Oct 08 14:27:53 2015 -0500"
  },
  "committer": {
    "name": "Bjorn Helgaas",
    "email": "bhelgaas@google.com",
    "time": "Mon Nov 02 14:48:45 2015 -0600"
  },
  "message": "PCI: designware: Require config accesses to be naturally aligned\n\nAdd sanity checks on \"addr\" input parameter in dw_pcie_cfg_read() and\ndw_pcie_cfg_write().  These checks make sure that accesses are aligned on\ntheir size, e.g., a 4-byte config access is aligned on a 4-byte boundary.\n\n[bhelgaas: changelog, set *val \u003d 0 in failure case]\nSigned-off-by: Gabriele Paoloni \u003cgabriele.paoloni@huawei.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nAcked-by: Pratyush Anand \u003cpratyush.anand@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "759cd0a509104c1078c0df10242c4e8579329f7a",
      "old_mode": 33188,
      "old_path": "drivers/pci/host/pcie-designware.c",
      "new_id": "b77535f3967b98a031024aab5c9fd6d627ef6ad0",
      "new_mode": 33188,
      "new_path": "drivers/pci/host/pcie-designware.c"
    }
  ]
}