| commit | b9d0b84b3db8552f033d5051393b90852b977a76 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Jul 11 13:54:30 2018 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Mon Aug 27 17:00:18 2018 +0200 |
| tree | a7514d0fb225f895946a9e5a499e6313ff535ebd | |
| parent | 0d2602d750152f9fcf3d9af9466f3d67b60aa646 [diff] |
clk: renesas: rcar-gen3: Add support for RCKSEL clock selection Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>