| commit | ba0074972ee9b3231b3de44650583654422e9758 | [log] [tgz] |
|---|---|---|
| author | Emil Renner Berthing <kernel@esmil.dk> | Thu Nov 30 16:19:27 2023 +0100 |
| committer | Conor Dooley <conor.dooley@microchip.com> | Wed Dec 13 15:50:23 2023 +0000 |
| tree | 0115e2e3344fde7997f86ab444ab8f4212eb06c0 | |
| parent | dd3c1b365fe92eefeae8bb0ac08e29b7ccdc3ca7 [diff] |
riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a40a8544..7c10094 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@2000000 {