/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
 * Author: Yu Tu <yu.tu@amlogic.com>
 */

#ifndef __MESON_S4_PERIPHERALS_H__
#define __MESON_S4_PERIPHERALS_H__

#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 0x008
#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 0x00c
#define CLKCTRL_RTC_CTRL                           0x010
#define CLKCTRL_SYS_CLK_CTRL0                      0x040
#define CLKCTRL_SYS_CLK_EN0_REG0                   0x044
#define CLKCTRL_SYS_CLK_EN0_REG1                   0x048
#define CLKCTRL_SYS_CLK_EN0_REG2                   0x04c
#define CLKCTRL_SYS_CLK_EN0_REG3                   0x050
#define CLKCTRL_CECA_CTRL0                         0x088
#define CLKCTRL_CECA_CTRL1                         0x08c
#define CLKCTRL_CECB_CTRL0                         0x090
#define CLKCTRL_CECB_CTRL1                         0x094
#define CLKCTRL_SC_CLK_CTRL                        0x098
#define CLKCTRL_CLK12_24_CTRL                      0x0a8
#define CLKCTRL_VID_CLK_CTRL                       0x0c0
#define CLKCTRL_VID_CLK_CTRL2                      0x0c4
#define CLKCTRL_VID_CLK_DIV                        0x0c8
#define CLKCTRL_VIID_CLK_DIV                       0x0cc
#define CLKCTRL_VIID_CLK_CTRL                      0x0d0
#define CLKCTRL_HDMI_CLK_CTRL                      0x0e0
#define CLKCTRL_VID_PLL_CLK_DIV                    0x0e4
#define CLKCTRL_VPU_CLK_CTRL                       0x0e8
#define CLKCTRL_VPU_CLKB_CTRL                      0x0ec
#define CLKCTRL_VPU_CLKC_CTRL                      0x0f0
#define CLKCTRL_VID_LOCK_CLK_CTRL                  0x0f4
#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 0x0f8
#define CLKCTRL_VAPBCLK_CTRL                       0x0fc
#define CLKCTRL_HDCP22_CTRL                        0x100
#define CLKCTRL_VDEC_CLK_CTRL                      0x140
#define CLKCTRL_VDEC2_CLK_CTRL                     0x144
#define CLKCTRL_VDEC3_CLK_CTRL                     0x148
#define CLKCTRL_VDEC4_CLK_CTRL                     0x14c
#define CLKCTRL_TS_CLK_CTRL                        0x158
#define CLKCTRL_MALI_CLK_CTRL                      0x15c
#define CLKCTRL_NAND_CLK_CTRL                      0x168
#define CLKCTRL_SD_EMMC_CLK_CTRL                   0x16c
#define CLKCTRL_SPICC_CLK_CTRL                     0x174
#define CLKCTRL_GEN_CLK_CTRL                       0x178
#define CLKCTRL_SAR_CLK_CTRL                       0x17c
#define CLKCTRL_PWM_CLK_AB_CTRL                    0x180
#define CLKCTRL_PWM_CLK_CD_CTRL                    0x184
#define CLKCTRL_PWM_CLK_EF_CTRL                    0x188
#define CLKCTRL_PWM_CLK_GH_CTRL                    0x18c
#define CLKCTRL_PWM_CLK_IJ_CTRL                    0x190
#define CLKCTRL_DEMOD_CLK_CTRL                     0x200

#endif /* __MESON_S4_PERIPHERALS_H__ */