tree e16ecf5ff18566f37ff009843a8b0894f0bd5627
parent 49e6e07e3c806c311e07da14a6d6e406ac9e719c
author Kamal Dasu <kdasu.kdev@gmail.com> 1581114787 -0500
committer Thomas Bogendoerfer <tsbogend@alpha.franken.de> 1584371396 +0100

MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
line can contain two instruction cache lines (64B), or four data cache
lines (32B). Hardware prefetch Cache detects stream access, and prefetches
ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
secondary cache module (ZSCM) on DMA from device so that data returned is
coherent during DMA read operations.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>