// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"

/ {
	chosen {
		stdout-path = &uart2;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "yellow:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ir>;
		linux,autosuspend-period = <125>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ptn5110: tcpc@50 {
		compatible = "nxp,ptn5110";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec1>;
		reg = <0x50>;
		interrupt-parent = <&gpio2>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		port {
			typec1_dr_sw: endpoint {
				remote-endpoint = <&usb1_drd_sw>;
			};
		};

		typec1_con: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			power-role = "dual";
			data-role = "dual";
			try-power-role = "sink";
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
				     PDO_VAR(5000, 20000, 3000)>;
			op-sink-microwatt = <15000000>;
			self-powered;
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&snvs_pwrkey {
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
		>;
	};

	pinctrl_ir: irgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_typec1: typec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
		>;
	};
};