commit c3e838a2cbb0f14af4d718160933523ac4c37adf
author Chris Dearman <chris@mips.com> Thu Jun 21 12:59:57 2007 +0100
committer Ralf Baechle <ralf@linux-mips.org> Fri Jul 06 16:17:11 2007 +0100
tree 37f41332212861826d18aff9c373846d31a93174
parent 6fb88ce04f545ca7da15a7b447783bb7a4615511

[MIPS] Fix timer/performance interrupt detection

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/traps.c

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b123364..3ea7863 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1372,12 +1372,12 @@
 	 */
 	if (cpu_has_mips_r2) {
 		cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
-		cp0_perfcount_irq = -1;
+		cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
+		if (cp0_perfcount_irq == cp0_compare_irq)
+			cp0_perfcount_irq = -1;
 	} else {
 		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-		cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
-		if (cp0_perfcount_irq != cp0_compare_irq)
-			cp0_perfcount_irq = -1;
+		cp0_perfcount_irq = -1;
 	}
 
 #ifdef CONFIG_MIPS_MT_SMTC