/*
 * Copyright (C) 2005 - 2008 ServerEngines
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@serverengines.com
 *
 * ServerEngines
 * 209 N. Fair Oaks Ave
 * Sunnyvale, CA 94085
 */
/*
 * Autogenerated by srcgen version: 0127
 */
#ifndef __cev_amap_h__
#define __cev_amap_h__
#include "ep.h"

/*
 * Host Interrupt Status Register 0. The first of four application
 * interrupt status registers. This register contains the interrupts
 * for Event Queues EQ0 through EQ31.
 */
struct BE_CEV_ISR0_CSR_AMAP {
	u8 interrupt0;	/* DWORD 0 */
	u8 interrupt1;	/* DWORD 0 */
	u8 interrupt2;	/* DWORD 0 */
	u8 interrupt3;	/* DWORD 0 */
	u8 interrupt4;	/* DWORD 0 */
	u8 interrupt5;	/* DWORD 0 */
	u8 interrupt6;	/* DWORD 0 */
	u8 interrupt7;	/* DWORD 0 */
	u8 interrupt8;	/* DWORD 0 */
	u8 interrupt9;	/* DWORD 0 */
	u8 interrupt10;	/* DWORD 0 */
	u8 interrupt11;	/* DWORD 0 */
	u8 interrupt12;	/* DWORD 0 */
	u8 interrupt13;	/* DWORD 0 */
	u8 interrupt14;	/* DWORD 0 */
	u8 interrupt15;	/* DWORD 0 */
	u8 interrupt16;	/* DWORD 0 */
	u8 interrupt17;	/* DWORD 0 */
	u8 interrupt18;	/* DWORD 0 */
	u8 interrupt19;	/* DWORD 0 */
	u8 interrupt20;	/* DWORD 0 */
	u8 interrupt21;	/* DWORD 0 */
	u8 interrupt22;	/* DWORD 0 */
	u8 interrupt23;	/* DWORD 0 */
	u8 interrupt24;	/* DWORD 0 */
	u8 interrupt25;	/* DWORD 0 */
	u8 interrupt26;	/* DWORD 0 */
	u8 interrupt27;	/* DWORD 0 */
	u8 interrupt28;	/* DWORD 0 */
	u8 interrupt29;	/* DWORD 0 */
	u8 interrupt30;	/* DWORD 0 */
	u8 interrupt31;	/* DWORD 0 */
} __packed;
struct CEV_ISR0_CSR_AMAP {
	u32 dw[1];
};

/*
 * Host Interrupt Status Register 1. The second of four application
 * interrupt status registers. This register contains the interrupts
 * for Event Queues EQ32 through EQ63.
 */
struct BE_CEV_ISR1_CSR_AMAP {
	u8 interrupt32;	/* DWORD 0 */
	u8 interrupt33;	/* DWORD 0 */
	u8 interrupt34;	/* DWORD 0 */
	u8 interrupt35;	/* DWORD 0 */
	u8 interrupt36;	/* DWORD 0 */
	u8 interrupt37;	/* DWORD 0 */
	u8 interrupt38;	/* DWORD 0 */
	u8 interrupt39;	/* DWORD 0 */
	u8 interrupt40;	/* DWORD 0 */
	u8 interrupt41;	/* DWORD 0 */
	u8 interrupt42;	/* DWORD 0 */
	u8 interrupt43;	/* DWORD 0 */
	u8 interrupt44;	/* DWORD 0 */
	u8 interrupt45;	/* DWORD 0 */
	u8 interrupt46;	/* DWORD 0 */
	u8 interrupt47;	/* DWORD 0 */
	u8 interrupt48;	/* DWORD 0 */
	u8 interrupt49;	/* DWORD 0 */
	u8 interrupt50;	/* DWORD 0 */
	u8 interrupt51;	/* DWORD 0 */
	u8 interrupt52;	/* DWORD 0 */
	u8 interrupt53;	/* DWORD 0 */
	u8 interrupt54;	/* DWORD 0 */
	u8 interrupt55;	/* DWORD 0 */
	u8 interrupt56;	/* DWORD 0 */
	u8 interrupt57;	/* DWORD 0 */
	u8 interrupt58;	/* DWORD 0 */
	u8 interrupt59;	/* DWORD 0 */
	u8 interrupt60;	/* DWORD 0 */
	u8 interrupt61;	/* DWORD 0 */
	u8 interrupt62;	/* DWORD 0 */
	u8 interrupt63;	/* DWORD 0 */
} __packed;
struct CEV_ISR1_CSR_AMAP {
	u32 dw[1];
};
/*
 * Host Interrupt Status Register 2. The third of four application
 * interrupt status registers. This register contains the interrupts
 * for Event Queues EQ64 through EQ95.
 */
struct BE_CEV_ISR2_CSR_AMAP {
	u8 interrupt64;	/* DWORD 0 */
	u8 interrupt65;	/* DWORD 0 */
	u8 interrupt66;	/* DWORD 0 */
	u8 interrupt67;	/* DWORD 0 */
	u8 interrupt68;	/* DWORD 0 */
	u8 interrupt69;	/* DWORD 0 */
	u8 interrupt70;	/* DWORD 0 */
	u8 interrupt71;	/* DWORD 0 */
	u8 interrupt72;	/* DWORD 0 */
	u8 interrupt73;	/* DWORD 0 */
	u8 interrupt74;	/* DWORD 0 */
	u8 interrupt75;	/* DWORD 0 */
	u8 interrupt76;	/* DWORD 0 */
	u8 interrupt77;	/* DWORD 0 */
	u8 interrupt78;	/* DWORD 0 */
	u8 interrupt79;	/* DWORD 0 */
	u8 interrupt80;	/* DWORD 0 */
	u8 interrupt81;	/* DWORD 0 */
	u8 interrupt82;	/* DWORD 0 */
	u8 interrupt83;	/* DWORD 0 */
	u8 interrupt84;	/* DWORD 0 */
	u8 interrupt85;	/* DWORD 0 */
	u8 interrupt86;	/* DWORD 0 */
	u8 interrupt87;	/* DWORD 0 */
	u8 interrupt88;	/* DWORD 0 */
	u8 interrupt89;	/* DWORD 0 */
	u8 interrupt90;	/* DWORD 0 */
	u8 interrupt91;	/* DWORD 0 */
	u8 interrupt92;	/* DWORD 0 */
	u8 interrupt93;	/* DWORD 0 */
	u8 interrupt94;	/* DWORD 0 */
	u8 interrupt95;	/* DWORD 0 */
} __packed;
struct CEV_ISR2_CSR_AMAP {
	u32 dw[1];
};

/*
 * Host Interrupt Status Register 3. The fourth of four application
 * interrupt status registers. This register contains the interrupts
 * for Event Queues EQ96 through EQ127.
 */
struct BE_CEV_ISR3_CSR_AMAP {
	u8 interrupt96;	/* DWORD 0 */
	u8 interrupt97;	/* DWORD 0 */
	u8 interrupt98;	/* DWORD 0 */
	u8 interrupt99;	/* DWORD 0 */
	u8 interrupt100;	/* DWORD 0 */
	u8 interrupt101;	/* DWORD 0 */
	u8 interrupt102;	/* DWORD 0 */
	u8 interrupt103;	/* DWORD 0 */
	u8 interrupt104;	/* DWORD 0 */
	u8 interrupt105;	/* DWORD 0 */
	u8 interrupt106;	/* DWORD 0 */
	u8 interrupt107;	/* DWORD 0 */
	u8 interrupt108;	/* DWORD 0 */
	u8 interrupt109;	/* DWORD 0 */
	u8 interrupt110;	/* DWORD 0 */
	u8 interrupt111;	/* DWORD 0 */
	u8 interrupt112;	/* DWORD 0 */
	u8 interrupt113;	/* DWORD 0 */
	u8 interrupt114;	/* DWORD 0 */
	u8 interrupt115;	/* DWORD 0 */
	u8 interrupt116;	/* DWORD 0 */
	u8 interrupt117;	/* DWORD 0 */
	u8 interrupt118;	/* DWORD 0 */
	u8 interrupt119;	/* DWORD 0 */
	u8 interrupt120;	/* DWORD 0 */
	u8 interrupt121;	/* DWORD 0 */
	u8 interrupt122;	/* DWORD 0 */
	u8 interrupt123;	/* DWORD 0 */
	u8 interrupt124;	/* DWORD 0 */
	u8 interrupt125;	/* DWORD 0 */
	u8 interrupt126;	/* DWORD 0 */
	u8 interrupt127;	/* DWORD 0 */
} __packed;
struct CEV_ISR3_CSR_AMAP {
	u32 dw[1];
};

/*  Completions and Events block Registers.  */
struct BE_CEV_CSRMAP_AMAP {
	u8 rsvd0[32];	/* DWORD 0 */
	u8 rsvd1[32];	/* DWORD 1 */
	u8 rsvd2[32];	/* DWORD 2 */
	u8 rsvd3[32];	/* DWORD 3 */
	struct BE_CEV_ISR0_CSR_AMAP isr0;
	struct BE_CEV_ISR1_CSR_AMAP isr1;
	struct BE_CEV_ISR2_CSR_AMAP isr2;
	struct BE_CEV_ISR3_CSR_AMAP isr3;
	u8 rsvd4[32];	/* DWORD 8 */
	u8 rsvd5[32];	/* DWORD 9 */
	u8 rsvd6[32];	/* DWORD 10 */
	u8 rsvd7[32];	/* DWORD 11 */
	u8 rsvd8[32];	/* DWORD 12 */
	u8 rsvd9[32];	/* DWORD 13 */
	u8 rsvd10[32];	/* DWORD 14 */
	u8 rsvd11[32];	/* DWORD 15 */
	u8 rsvd12[32];	/* DWORD 16 */
	u8 rsvd13[32];	/* DWORD 17 */
	u8 rsvd14[32];	/* DWORD 18 */
	u8 rsvd15[32];	/* DWORD 19 */
	u8 rsvd16[32];	/* DWORD 20 */
	u8 rsvd17[32];	/* DWORD 21 */
	u8 rsvd18[32];	/* DWORD 22 */
	u8 rsvd19[32];	/* DWORD 23 */
	u8 rsvd20[32];	/* DWORD 24 */
	u8 rsvd21[32];	/* DWORD 25 */
	u8 rsvd22[32];	/* DWORD 26 */
	u8 rsvd23[32];	/* DWORD 27 */
	u8 rsvd24[32];	/* DWORD 28 */
	u8 rsvd25[32];	/* DWORD 29 */
	u8 rsvd26[32];	/* DWORD 30 */
	u8 rsvd27[32];	/* DWORD 31 */
	u8 rsvd28[32];	/* DWORD 32 */
	u8 rsvd29[32];	/* DWORD 33 */
	u8 rsvd30[192];	/* DWORD 34 */
	u8 rsvd31[192];	/* DWORD 40 */
	u8 rsvd32[160];	/* DWORD 46 */
	u8 rsvd33[160];	/* DWORD 51 */
	u8 rsvd34[160];	/* DWORD 56 */
	u8 rsvd35[96];	/* DWORD 61 */
	u8 rsvd36[192][32];	/* DWORD 64 */
} __packed;
struct CEV_CSRMAP_AMAP {
	u32 dw[256];
};

#endif /* __cev_amap_h__ */