# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8195 Pin Controller

maintainers:
  - Sean Wang <sean.wang@mediatek.com>

description: |
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8195-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
      the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.
    const: 2

  gpio-ranges:
    description: gpio valid number range.
    maxItems: 1

  reg:
    description: |
      Physical address base for gpio base registers. There are 8 GPIO
      physical address base in mt8195.
    maxItems: 8

  reg-names:
    description: |
      Gpio base register names.
    maxItems: 8

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: The interrupt outputs to sysirq.
    maxItems: 1

#PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    description: |
      A pinctrl node should contain at least one subnodes representing the
      pinctrl groups available on the machine. Each subnode will list the
      pins it needs, and how they should be configured, with regard to muxer
      configuration, pullups, drive strength, input enable/disable and
      input schmitt.
      An example of using macro:
      pincontroller {
        /* GPIO0 set as multifunction GPIO0 */
        gpio_pin {
          pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
        };
        /* GPIO8 set as multifunction SDA0 */
        i2c0_pin {
          pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
        };
      };
    $ref: "pinmux-node.yaml"

    properties:
      pinmux:
        description: |
          Integer array, represents gpio pin number and mux setting.
          Supported pin number and mux varies for different SoCs, and are defined
          as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.

      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

      input-enable: true

      input-disable: true

      input-schmitt-enable: true

      input-schmitt-disable: true

    required:
      - pinmux

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
            #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
            #include <dt-bindings/interrupt-controller/arm-gic.h>
            pio: pinctrl@10005000 {
                    compatible = "mediatek,mt8195-pinctrl";
                    reg = <0x10005000 0x1000>,
                          <0x11d10000 0x1000>,
                          <0x11d30000 0x1000>,
                          <0x11d40000 0x1000>,
                          <0x11e20000 0x1000>,
                          <0x11eb0000 0x1000>,
                          <0x11f40000 0x1000>,
                          <0x1000b000 0x1000>;
                    reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
                          "iocfg_br", "iocfg_lm", "iocfg_rb",
                          "iocfg_tl", "eint";
                    gpio-controller;
                    #gpio-cells = <2>;
                    gpio-ranges = <&pio 0 0 144>;
                    interrupt-controller;
                    interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
                    #interrupt-cells = <2>;

                    pio-pins {
                      pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
                      output-low;
                    };
            };