blob: a3cb3d988ba4e9aa8086e474850377f91bc1efc3 [file] [log] [blame]
#ifndef A6XX_XML
#define A6XX_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum a6xx_tile_mode {
TILE6_LINEAR = 0,
TILE6_2 = 2,
TILE6_3 = 3,
};
enum a6xx_format {
FMT6_A8_UNORM = 2,
FMT6_8_UNORM = 3,
FMT6_8_SNORM = 4,
FMT6_8_UINT = 5,
FMT6_8_SINT = 6,
FMT6_4_4_4_4_UNORM = 8,
FMT6_5_5_5_1_UNORM = 10,
FMT6_1_5_5_5_UNORM = 12,
FMT6_5_6_5_UNORM = 14,
FMT6_8_8_UNORM = 15,
FMT6_8_8_SNORM = 16,
FMT6_8_8_UINT = 17,
FMT6_8_8_SINT = 18,
FMT6_L8_A8_UNORM = 19,
FMT6_16_UNORM = 21,
FMT6_16_SNORM = 22,
FMT6_16_FLOAT = 23,
FMT6_16_UINT = 24,
FMT6_16_SINT = 25,
FMT6_8_8_8_UNORM = 33,
FMT6_8_8_8_SNORM = 34,
FMT6_8_8_8_UINT = 35,
FMT6_8_8_8_SINT = 36,
FMT6_8_8_8_8_UNORM = 48,
FMT6_8_8_8_X8_UNORM = 49,
FMT6_8_8_8_8_SNORM = 50,
FMT6_8_8_8_8_UINT = 51,
FMT6_8_8_8_8_SINT = 52,
FMT6_9_9_9_E5_FLOAT = 53,
FMT6_10_10_10_2_UNORM = 54,
FMT6_10_10_10_2_UNORM_DEST = 55,
FMT6_10_10_10_2_SNORM = 57,
FMT6_10_10_10_2_UINT = 58,
FMT6_10_10_10_2_SINT = 59,
FMT6_11_11_10_FLOAT = 66,
FMT6_16_16_UNORM = 67,
FMT6_16_16_SNORM = 68,
FMT6_16_16_FLOAT = 69,
FMT6_16_16_UINT = 70,
FMT6_16_16_SINT = 71,
FMT6_32_UNORM = 72,
FMT6_32_SNORM = 73,
FMT6_32_FLOAT = 74,
FMT6_32_UINT = 75,
FMT6_32_SINT = 76,
FMT6_32_FIXED = 77,
FMT6_16_16_16_UNORM = 88,
FMT6_16_16_16_SNORM = 89,
FMT6_16_16_16_FLOAT = 90,
FMT6_16_16_16_UINT = 91,
FMT6_16_16_16_SINT = 92,
FMT6_16_16_16_16_UNORM = 96,
FMT6_16_16_16_16_SNORM = 97,
FMT6_16_16_16_16_FLOAT = 98,
FMT6_16_16_16_16_UINT = 99,
FMT6_16_16_16_16_SINT = 100,
FMT6_32_32_UNORM = 101,
FMT6_32_32_SNORM = 102,
FMT6_32_32_FLOAT = 103,
FMT6_32_32_UINT = 104,
FMT6_32_32_SINT = 105,
FMT6_32_32_FIXED = 106,
FMT6_32_32_32_UNORM = 112,
FMT6_32_32_32_SNORM = 113,
FMT6_32_32_32_UINT = 114,
FMT6_32_32_32_SINT = 115,
FMT6_32_32_32_FLOAT = 116,
FMT6_32_32_32_FIXED = 117,
FMT6_32_32_32_32_UNORM = 128,
FMT6_32_32_32_32_SNORM = 129,
FMT6_32_32_32_32_FLOAT = 130,
FMT6_32_32_32_32_UINT = 131,
FMT6_32_32_32_32_SINT = 132,
FMT6_32_32_32_32_FIXED = 133,
FMT6_G8R8B8R8_422_UNORM = 140,
FMT6_R8G8R8B8_422_UNORM = 141,
FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
FMT6_8_PLANE_UNORM = 148,
FMT6_Z24_UNORM_S8_UINT = 160,
FMT6_ETC2_RG11_UNORM = 171,
FMT6_ETC2_RG11_SNORM = 172,
FMT6_ETC2_R11_UNORM = 173,
FMT6_ETC2_R11_SNORM = 174,
FMT6_ETC1 = 175,
FMT6_ETC2_RGB8 = 176,
FMT6_ETC2_RGBA8 = 177,
FMT6_ETC2_RGB8A1 = 178,
FMT6_DXT1 = 179,
FMT6_DXT3 = 180,
FMT6_DXT5 = 181,
FMT6_RGTC1_UNORM = 183,
FMT6_RGTC1_SNORM = 184,
FMT6_RGTC2_UNORM = 187,
FMT6_RGTC2_SNORM = 188,
FMT6_BPTC_UFLOAT = 190,
FMT6_BPTC_FLOAT = 191,
FMT6_BPTC = 192,
FMT6_ASTC_4x4 = 193,
FMT6_ASTC_5x4 = 194,
FMT6_ASTC_5x5 = 195,
FMT6_ASTC_6x5 = 196,
FMT6_ASTC_6x6 = 197,
FMT6_ASTC_8x5 = 198,
FMT6_ASTC_8x6 = 199,
FMT6_ASTC_8x8 = 200,
FMT6_ASTC_10x5 = 201,
FMT6_ASTC_10x6 = 202,
FMT6_ASTC_10x8 = 203,
FMT6_ASTC_10x10 = 204,
FMT6_ASTC_12x10 = 205,
FMT6_ASTC_12x12 = 206,
FMT6_Z24_UINT_S8_UINT = 234,
FMT6_NONE = 255,
};
enum a6xx_polygon_mode {
POLYMODE6_POINTS = 1,
POLYMODE6_LINES = 2,
POLYMODE6_TRIANGLES = 3,
};
enum a6xx_depth_format {
DEPTH6_NONE = 0,
DEPTH6_16 = 1,
DEPTH6_24_8 = 2,
DEPTH6_32 = 4,
};
enum a6xx_shader_id {
A6XX_TP0_TMO_DATA = 9,
A6XX_TP0_SMO_DATA = 10,
A6XX_TP0_MIPMAP_BASE_DATA = 11,
A6XX_TP1_TMO_DATA = 25,
A6XX_TP1_SMO_DATA = 26,
A6XX_TP1_MIPMAP_BASE_DATA = 27,
A6XX_SP_INST_DATA = 41,
A6XX_SP_LB_0_DATA = 42,
A6XX_SP_LB_1_DATA = 43,
A6XX_SP_LB_2_DATA = 44,
A6XX_SP_LB_3_DATA = 45,
A6XX_SP_LB_4_DATA = 46,
A6XX_SP_LB_5_DATA = 47,
A6XX_SP_CB_BINDLESS_DATA = 48,
A6XX_SP_CB_LEGACY_DATA = 49,
A6XX_SP_UAV_DATA = 50,
A6XX_SP_INST_TAG = 51,
A6XX_SP_CB_BINDLESS_TAG = 52,
A6XX_SP_TMO_UMO_TAG = 53,
A6XX_SP_SMO_TAG = 54,
A6XX_SP_STATE_DATA = 55,
A6XX_HLSQ_CHUNK_CVS_RAM = 73,
A6XX_HLSQ_CHUNK_CPS_RAM = 74,
A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
A6XX_HLSQ_CVS_MISC_RAM = 80,
A6XX_HLSQ_CPS_MISC_RAM = 81,
A6XX_HLSQ_INST_RAM = 82,
A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
A6XX_HLSQ_INST_RAM_TAG = 87,
A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
A6XX_HLSQ_PWR_REST_RAM = 90,
A6XX_HLSQ_PWR_REST_TAG = 91,
A6XX_HLSQ_DATAPATH_META = 96,
A6XX_HLSQ_FRONTEND_META = 97,
A6XX_HLSQ_INDIRECT_META = 98,
A6XX_HLSQ_BACKEND_META = 99,
};
enum a6xx_debugbus_id {
A6XX_DBGBUS_CP = 1,
A6XX_DBGBUS_RBBM = 2,
A6XX_DBGBUS_VBIF = 3,
A6XX_DBGBUS_HLSQ = 4,
A6XX_DBGBUS_UCHE = 5,
A6XX_DBGBUS_DPM = 6,
A6XX_DBGBUS_TESS = 7,
A6XX_DBGBUS_PC = 8,
A6XX_DBGBUS_VFDP = 9,
A6XX_DBGBUS_VPC = 10,
A6XX_DBGBUS_TSE = 11,
A6XX_DBGBUS_RAS = 12,
A6XX_DBGBUS_VSC = 13,
A6XX_DBGBUS_COM = 14,
A6XX_DBGBUS_LRZ = 16,
A6XX_DBGBUS_A2D = 17,
A6XX_DBGBUS_CCUFCHE = 18,
A6XX_DBGBUS_GMU_CX = 19,
A6XX_DBGBUS_RBP = 20,
A6XX_DBGBUS_DCS = 21,
A6XX_DBGBUS_DBGC = 22,
A6XX_DBGBUS_CX = 23,
A6XX_DBGBUS_GMU_GX = 24,
A6XX_DBGBUS_TPFCHE = 25,
A6XX_DBGBUS_GBIF_GX = 26,
A6XX_DBGBUS_GPC = 29,
A6XX_DBGBUS_LARC = 30,
A6XX_DBGBUS_HLSQ_SPTP = 31,
A6XX_DBGBUS_RB_0 = 32,
A6XX_DBGBUS_RB_1 = 33,
A6XX_DBGBUS_UCHE_WRAPPER = 36,
A6XX_DBGBUS_CCU_0 = 40,
A6XX_DBGBUS_CCU_1 = 41,
A6XX_DBGBUS_VFD_0 = 56,
A6XX_DBGBUS_VFD_1 = 57,
A6XX_DBGBUS_VFD_2 = 58,
A6XX_DBGBUS_VFD_3 = 59,
A6XX_DBGBUS_SP_0 = 64,
A6XX_DBGBUS_SP_1 = 65,
A6XX_DBGBUS_TPL1_0 = 72,
A6XX_DBGBUS_TPL1_1 = 73,
A6XX_DBGBUS_TPL1_2 = 74,
A6XX_DBGBUS_TPL1_3 = 75,
};
enum a6xx_cp_perfcounter_select {
PERF_CP_ALWAYS_COUNT = 0,
PERF_CP_BUSY_GFX_CORE_IDLE = 1,
PERF_CP_BUSY_CYCLES = 2,
PERF_CP_NUM_PREEMPTIONS = 3,
PERF_CP_PREEMPTION_REACTION_DELAY = 4,
PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
PERF_CP_PREDICATED_DRAWS_KILLED = 8,
PERF_CP_MODE_SWITCH = 9,
PERF_CP_ZPASS_DONE = 10,
PERF_CP_CONTEXT_DONE = 11,
PERF_CP_CACHE_FLUSH = 12,
PERF_CP_LONG_PREEMPTIONS = 13,
PERF_CP_SQE_I_CACHE_STARVE = 14,
PERF_CP_SQE_IDLE = 15,
PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
PERF_CP_SQE_PM4_STARVE_SDS = 17,
PERF_CP_SQE_MRB_STARVE = 18,
PERF_CP_SQE_RRB_STARVE = 19,
PERF_CP_SQE_VSD_STARVE = 20,
PERF_CP_VSD_DECODE_STARVE = 21,
PERF_CP_SQE_PIPE_OUT_STALL = 22,
PERF_CP_SQE_SYNC_STALL = 23,
PERF_CP_SQE_PM4_WFI_STALL = 24,
PERF_CP_SQE_SYS_WFI_STALL = 25,
PERF_CP_SQE_T4_EXEC = 26,
PERF_CP_SQE_LOAD_STATE_EXEC = 27,
PERF_CP_SQE_SAVE_SDS_STATE = 28,
PERF_CP_SQE_DRAW_EXEC = 29,
PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
PERF_CP_SQE_EXEC_PROFILED = 31,
PERF_CP_MEMORY_POOL_EMPTY = 32,
PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
PERF_CP_AHB_STALL_SQE_GMU = 36,
PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
PERF_CP_CLUSTER0_EMPTY = 39,
PERF_CP_CLUSTER1_EMPTY = 40,
PERF_CP_CLUSTER2_EMPTY = 41,
PERF_CP_CLUSTER3_EMPTY = 42,
PERF_CP_CLUSTER4_EMPTY = 43,
PERF_CP_CLUSTER5_EMPTY = 44,
PERF_CP_PM4_DATA = 45,
PERF_CP_PM4_HEADERS = 46,
PERF_CP_VBIF_READ_BEATS = 47,
PERF_CP_VBIF_WRITE_BEATS = 48,
PERF_CP_SQE_INSTR_COUNTER = 49,
};
enum a6xx_rbbm_perfcounter_select {
PERF_RBBM_ALWAYS_COUNT = 0,
PERF_RBBM_ALWAYS_ON = 1,
PERF_RBBM_TSE_BUSY = 2,
PERF_RBBM_RAS_BUSY = 3,
PERF_RBBM_PC_DCALL_BUSY = 4,
PERF_RBBM_PC_VSD_BUSY = 5,
PERF_RBBM_STATUS_MASKED = 6,
PERF_RBBM_COM_BUSY = 7,
PERF_RBBM_DCOM_BUSY = 8,
PERF_RBBM_VBIF_BUSY = 9,
PERF_RBBM_VSC_BUSY = 10,
PERF_RBBM_TESS_BUSY = 11,
PERF_RBBM_UCHE_BUSY = 12,
PERF_RBBM_HLSQ_BUSY = 13,
};
enum a6xx_pc_perfcounter_select {
PERF_PC_BUSY_CYCLES = 0,
PERF_PC_WORKING_CYCLES = 1,
PERF_PC_STALL_CYCLES_VFD = 2,
PERF_PC_STALL_CYCLES_TSE = 3,
PERF_PC_STALL_CYCLES_VPC = 4,
PERF_PC_STALL_CYCLES_UCHE = 5,
PERF_PC_STALL_CYCLES_TESS = 6,
PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
PERF_PC_PASS1_TF_STALL_CYCLES = 9,
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
PERF_PC_STARVE_CYCLES_DI = 14,
PERF_PC_VIS_STREAMS_LOADED = 15,
PERF_PC_INSTANCES = 16,
PERF_PC_VPC_PRIMITIVES = 17,
PERF_PC_DEAD_PRIM = 18,
PERF_PC_LIVE_PRIM = 19,
PERF_PC_VERTEX_HITS = 20,
PERF_PC_IA_VERTICES = 21,
PERF_PC_IA_PRIMITIVES = 22,
PERF_PC_GS_PRIMITIVES = 23,
PERF_PC_HS_INVOCATIONS = 24,
PERF_PC_DS_INVOCATIONS = 25,
PERF_PC_VS_INVOCATIONS = 26,
PERF_PC_GS_INVOCATIONS = 27,
PERF_PC_DS_PRIMITIVES = 28,
PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
PERF_PC_3D_DRAWCALLS = 30,
PERF_PC_2D_DRAWCALLS = 31,
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
PERF_TESS_BUSY_CYCLES = 33,
PERF_TESS_WORKING_CYCLES = 34,
PERF_TESS_STALL_CYCLES_PC = 35,
PERF_TESS_STARVE_CYCLES_PC = 36,
PERF_PC_TSE_TRANSACTION = 37,
PERF_PC_TSE_VERTEX = 38,
PERF_PC_TESS_PC_UV_TRANS = 39,
PERF_PC_TESS_PC_UV_PATCHES = 40,
PERF_PC_TESS_FACTOR_TRANS = 41,
};
enum a6xx_vfd_perfcounter_select {
PERF_VFD_BUSY_CYCLES = 0,
PERF_VFD_STALL_CYCLES_UCHE = 1,
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
PERF_VFD_STALL_CYCLES_SP_INFO = 3,
PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
PERF_VFD_STARVE_CYCLES_UCHE = 5,
PERF_VFD_RBUFFER_FULL = 6,
PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
PERF_VFD_NUM_ATTRIBUTES = 9,
PERF_VFD_UPPER_SHADER_FIBERS = 10,
PERF_VFD_LOWER_SHADER_FIBERS = 11,
PERF_VFD_MODE_0_FIBERS = 12,
PERF_VFD_MODE_1_FIBERS = 13,
PERF_VFD_MODE_2_FIBERS = 14,
PERF_VFD_MODE_3_FIBERS = 15,
PERF_VFD_MODE_4_FIBERS = 16,
PERF_VFD_TOTAL_VERTICES = 17,
PERF_VFDP_STALL_CYCLES_VFD = 18,
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
PERF_VFDP_STARVE_CYCLES_PC = 21,
PERF_VFDP_VS_STAGE_WAVES = 22,
};
enum a6xx_hlsq_perfcounter_select {
PERF_HLSQ_BUSY_CYCLES = 0,
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
PERF_HLSQ_QUADS = 8,
PERF_HLSQ_CS_INVOCATIONS = 9,
PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
PERF_HLSQ_STALL_CYCLES_VPC = 18,
PERF_HLSQ_PIXELS = 19,
PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
};
enum a6xx_vpc_perfcounter_select {
PERF_VPC_BUSY_CYCLES = 0,
PERF_VPC_WORKING_CYCLES = 1,
PERF_VPC_STALL_CYCLES_UCHE = 2,
PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
PERF_VPC_STALL_CYCLES_PC = 5,
PERF_VPC_STALL_CYCLES_SP_LM = 6,
PERF_VPC_STARVE_CYCLES_SP = 7,
PERF_VPC_STARVE_CYCLES_LRZ = 8,
PERF_VPC_PC_PRIMITIVES = 9,
PERF_VPC_SP_COMPONENTS = 10,
PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
PERF_VPC_LM_TRANSACTION = 14,
PERF_VPC_STREAMOUT_TRANSACTION = 15,
PERF_VPC_VS_BUSY_CYCLES = 16,
PERF_VPC_PS_BUSY_CYCLES = 17,
PERF_VPC_VS_WORKING_CYCLES = 18,
PERF_VPC_PS_WORKING_CYCLES = 19,
PERF_VPC_STARVE_CYCLES_RB = 20,
PERF_VPC_NUM_VPCRAM_READ_POS = 21,
PERF_VPC_WIT_FULL_CYCLES = 22,
PERF_VPC_VPCRAM_FULL_CYCLES = 23,
PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
PERF_VPC_NUM_VPCRAM_WRITE = 25,
PERF_VPC_NUM_VPCRAM_READ_SO = 26,
PERF_VPC_NUM_ATTR_REQ_LM = 27,
};
enum a6xx_tse_perfcounter_select {
PERF_TSE_BUSY_CYCLES = 0,
PERF_TSE_CLIPPING_CYCLES = 1,
PERF_TSE_STALL_CYCLES_RAS = 2,
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
PERF_TSE_STARVE_CYCLES_PC = 5,
PERF_TSE_INPUT_PRIM = 6,
PERF_TSE_INPUT_NULL_PRIM = 7,
PERF_TSE_TRIVAL_REJ_PRIM = 8,
PERF_TSE_CLIPPED_PRIM = 9,
PERF_TSE_ZERO_AREA_PRIM = 10,
PERF_TSE_FACENESS_CULLED_PRIM = 11,
PERF_TSE_ZERO_PIXEL_PRIM = 12,
PERF_TSE_OUTPUT_NULL_PRIM = 13,
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
PERF_TSE_CINVOCATION = 15,
PERF_TSE_CPRIMITIVES = 16,
PERF_TSE_2D_INPUT_PRIM = 17,
PERF_TSE_2D_ALIVE_CYCLES = 18,
PERF_TSE_CLIP_PLANES = 19,
};
enum a6xx_ras_perfcounter_select {
PERF_RAS_BUSY_CYCLES = 0,
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
PERF_RAS_STALL_CYCLES_LRZ = 2,
PERF_RAS_STARVE_CYCLES_TSE = 3,
PERF_RAS_SUPER_TILES = 4,
PERF_RAS_8X4_TILES = 5,
PERF_RAS_MASKGEN_ACTIVE = 6,
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
PERF_RAS_PRIM_KILLED_INVISILBE = 9,
PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
PERF_RAS_BLOCKS = 12,
};
enum a6xx_uche_perfcounter_select {
PERF_UCHE_BUSY_CYCLES = 0,
PERF_UCHE_STALL_CYCLES_ARBITER = 1,
PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
PERF_UCHE_VBIF_READ_BEATS_TP = 4,
PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
PERF_UCHE_VBIF_READ_BEATS_SP = 8,
PERF_UCHE_READ_REQUESTS_TP = 9,
PERF_UCHE_READ_REQUESTS_VFD = 10,
PERF_UCHE_READ_REQUESTS_HLSQ = 11,
PERF_UCHE_READ_REQUESTS_LRZ = 12,
PERF_UCHE_READ_REQUESTS_SP = 13,
PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
PERF_UCHE_WRITE_REQUESTS_SP = 15,
PERF_UCHE_WRITE_REQUESTS_VPC = 16,
PERF_UCHE_WRITE_REQUESTS_VSC = 17,
PERF_UCHE_EVICTS = 18,
PERF_UCHE_BANK_REQ0 = 19,
PERF_UCHE_BANK_REQ1 = 20,
PERF_UCHE_BANK_REQ2 = 21,
PERF_UCHE_BANK_REQ3 = 22,
PERF_UCHE_BANK_REQ4 = 23,
PERF_UCHE_BANK_REQ5 = 24,
PERF_UCHE_BANK_REQ6 = 25,
PERF_UCHE_BANK_REQ7 = 26,
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
PERF_UCHE_GMEM_READ_BEATS = 29,
PERF_UCHE_TPH_REF_FULL = 30,
PERF_UCHE_TPH_VICTIM_FULL = 31,
PERF_UCHE_TPH_EXT_FULL = 32,
PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
PERF_UCHE_VBIF_READ_BEATS_PC = 36,
PERF_UCHE_READ_REQUESTS_PC = 37,
PERF_UCHE_RAM_READ_REQ = 38,
PERF_UCHE_RAM_WRITE_REQ = 39,
};
enum a6xx_tp_perfcounter_select {
PERF_TP_BUSY_CYCLES = 0,
PERF_TP_STALL_CYCLES_UCHE = 1,
PERF_TP_LATENCY_CYCLES = 2,
PERF_TP_LATENCY_TRANS = 3,
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
PERF_TP_L1_CACHELINE_REQUESTS = 6,
PERF_TP_L1_CACHELINE_MISSES = 7,
PERF_TP_SP_TP_TRANS = 8,
PERF_TP_TP_SP_TRANS = 9,
PERF_TP_OUTPUT_PIXELS = 10,
PERF_TP_FILTER_WORKLOAD_16BIT = 11,
PERF_TP_FILTER_WORKLOAD_32BIT = 12,
PERF_TP_QUADS_RECEIVED = 13,
PERF_TP_QUADS_OFFSET = 14,
PERF_TP_QUADS_SHADOW = 15,
PERF_TP_QUADS_ARRAY = 16,
PERF_TP_QUADS_GRADIENT = 17,
PERF_TP_QUADS_1D = 18,
PERF_TP_QUADS_2D = 19,
PERF_TP_QUADS_BUFFER = 20,
PERF_TP_QUADS_3D = 21,
PERF_TP_QUADS_CUBE = 22,
PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
PERF_TP_OUTPUT_PIXELS_POINT = 25,
PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
PERF_TP_OUTPUT_PIXELS_MIP = 27,
PERF_TP_OUTPUT_PIXELS_ANISO = 28,
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
PERF_TP_FLAG_CACHE_REQUESTS = 30,
PERF_TP_FLAG_CACHE_MISSES = 31,
PERF_TP_L1_5_L2_REQUESTS = 32,
PERF_TP_2D_OUTPUT_PIXELS = 33,
PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
PERF_TP_TPA2TPC_TRANS = 38,
PERF_TP_L1_MISSES_ASTC_1TILE = 39,
PERF_TP_L1_MISSES_ASTC_2TILE = 40,
PERF_TP_L1_MISSES_ASTC_4TILE = 41,
PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
PERF_TP_L1_BANK_CONFLICT = 44,
PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
PERF_TP_FRONTEND_WORKING_CYCLES = 48,
PERF_TP_L1_TAG_WORKING_CYCLES = 49,
PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
PERF_TP_BACKEND_WORKING_CYCLES = 52,
PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
PERF_TP_STARVE_CYCLES_SP = 55,
PERF_TP_STARVE_CYCLES_UCHE = 56,
};
enum a6xx_sp_perfcounter_select {
PERF_SP_BUSY_CYCLES = 0,
PERF_SP_ALU_WORKING_CYCLES = 1,
PERF_SP_EFU_WORKING_CYCLES = 2,
PERF_SP_STALL_CYCLES_VPC = 3,
PERF_SP_STALL_CYCLES_TP = 4,
PERF_SP_STALL_CYCLES_UCHE = 5,
PERF_SP_STALL_CYCLES_RB = 6,
PERF_SP_NON_EXECUTION_CYCLES = 7,
PERF_SP_WAVE_CONTEXTS = 8,
PERF_SP_WAVE_CONTEXT_CYCLES = 9,
PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
PERF_SP_WAVE_CTRL_CYCLES = 16,
PERF_SP_WAVE_LOAD_CYCLES = 17,
PERF_SP_WAVE_EMIT_CYCLES = 18,
PERF_SP_WAVE_NOP_CYCLES = 19,
PERF_SP_WAVE_WAIT_CYCLES = 20,
PERF_SP_WAVE_FETCH_CYCLES = 21,
PERF_SP_WAVE_IDLE_CYCLES = 22,
PERF_SP_WAVE_END_CYCLES = 23,
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
PERF_SP_WAVE_JOIN_CYCLES = 26,
PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
PERF_SP_LM_STORE_INSTRUCTIONS = 28,
PERF_SP_LM_ATOMICS = 29,
PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
PERF_SP_GM_STORE_INSTRUCTIONS = 31,
PERF_SP_GM_ATOMICS = 32,
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
PERF_SP_VS_INSTRUCTIONS = 43,
PERF_SP_FS_INSTRUCTIONS = 44,
PERF_SP_ADDR_LOCK_COUNT = 45,
PERF_SP_UCHE_READ_TRANS = 46,
PERF_SP_UCHE_WRITE_TRANS = 47,
PERF_SP_EXPORT_VPC_TRANS = 48,
PERF_SP_EXPORT_RB_TRANS = 49,
PERF_SP_PIXELS_KILLED = 50,
PERF_SP_ICL1_REQUESTS = 51,
PERF_SP_ICL1_MISSES = 52,
PERF_SP_HS_INSTRUCTIONS = 53,
PERF_SP_DS_INSTRUCTIONS = 54,
PERF_SP_GS_INSTRUCTIONS = 55,
PERF_SP_CS_INSTRUCTIONS = 56,
PERF_SP_GPR_READ = 57,
PERF_SP_GPR_WRITE = 58,
PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
PERF_SP_LM_BANK_CONFLICTS = 61,
PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
PERF_SP_LM_WORKING_CYCLES = 65,
PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
PERF_SP_STARVE_CYCLES_HLSQ = 69,
PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
PERF_SP_WORKING_EU = 71,
PERF_SP_ANY_EU_WORKING = 72,
PERF_SP_WORKING_EU_FS_STAGE = 73,
PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
PERF_SP_WORKING_EU_VS_STAGE = 75,
PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
PERF_SP_WORKING_EU_CS_STAGE = 77,
PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
PERF_SP_GPR_READ_PREFETCH = 79,
PERF_SP_GPR_READ_CONFLICT = 80,
PERF_SP_GPR_WRITE_CONFLICT = 81,
PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
PERF_SP_EXECUTABLE_WAVES = 84,
};
enum a6xx_rb_perfcounter_select {
PERF_RB_BUSY_CYCLES = 0,
PERF_RB_STALL_CYCLES_HLSQ = 1,
PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
PERF_RB_STARVE_CYCLES_SP = 5,
PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
PERF_RB_STARVE_CYCLES_CCU = 7,
PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
PERF_RB_Z_WORKLOAD = 10,
PERF_RB_HLSQ_ACTIVE = 11,
PERF_RB_Z_READ = 12,
PERF_RB_Z_WRITE = 13,
PERF_RB_C_READ = 14,
PERF_RB_C_WRITE = 15,
PERF_RB_TOTAL_PASS = 16,
PERF_RB_Z_PASS = 17,
PERF_RB_Z_FAIL = 18,
PERF_RB_S_FAIL = 19,
PERF_RB_BLENDED_FXP_COMPONENTS = 20,
PERF_RB_BLENDED_FP16_COMPONENTS = 21,
PERF_RB_PS_INVOCATIONS = 22,
PERF_RB_2D_ALIVE_CYCLES = 23,
PERF_RB_2D_STALL_CYCLES_A2D = 24,
PERF_RB_2D_STARVE_CYCLES_SRC = 25,
PERF_RB_2D_STARVE_CYCLES_SP = 26,
PERF_RB_2D_STARVE_CYCLES_DST = 27,
PERF_RB_2D_VALID_PIXELS = 28,
PERF_RB_3D_PIXELS = 29,
PERF_RB_BLENDER_WORKING_CYCLES = 30,
PERF_RB_ZPROC_WORKING_CYCLES = 31,
PERF_RB_CPROC_WORKING_CYCLES = 32,
PERF_RB_SAMPLER_WORKING_CYCLES = 33,
PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
PERF_RB_STALL_CYCLES_VPC = 38,
PERF_RB_2D_INPUT_TRANS = 39,
PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
PERF_RB_BLENDED_FP32_COMPONENTS = 42,
PERF_RB_COLOR_PIX_TILES = 43,
PERF_RB_STALL_CYCLES_CCU = 44,
PERF_RB_EARLY_Z_ARB3_GRANT = 45,
PERF_RB_LATE_Z_ARB3_GRANT = 46,
PERF_RB_EARLY_Z_SKIP_GRANT = 47,
};
enum a6xx_vsc_perfcounter_select {
PERF_VSC_BUSY_CYCLES = 0,
PERF_VSC_WORKING_CYCLES = 1,
PERF_VSC_STALL_CYCLES_UCHE = 2,
PERF_VSC_EOT_NUM = 3,
PERF_VSC_INPUT_TILES = 4,
};
enum a6xx_ccu_perfcounter_select {
PERF_CCU_BUSY_CYCLES = 0,
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
PERF_CCU_DEPTH_BLOCKS = 4,
PERF_CCU_COLOR_BLOCKS = 5,
PERF_CCU_DEPTH_BLOCK_HIT = 6,
PERF_CCU_COLOR_BLOCK_HIT = 7,
PERF_CCU_PARTIAL_BLOCK_READ = 8,
PERF_CCU_GMEM_READ = 9,
PERF_CCU_GMEM_WRITE = 10,
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
PERF_CCU_2D_RD_REQ = 27,
PERF_CCU_2D_WR_REQ = 28,
};
enum a6xx_lrz_perfcounter_select {
PERF_LRZ_BUSY_CYCLES = 0,
PERF_LRZ_STARVE_CYCLES_RAS = 1,
PERF_LRZ_STALL_CYCLES_RB = 2,
PERF_LRZ_STALL_CYCLES_VSC = 3,
PERF_LRZ_STALL_CYCLES_VPC = 4,
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
PERF_LRZ_STALL_CYCLES_UCHE = 6,
PERF_LRZ_LRZ_READ = 7,
PERF_LRZ_LRZ_WRITE = 8,
PERF_LRZ_READ_LATENCY = 9,
PERF_LRZ_MERGE_CACHE_UPDATING = 10,
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
PERF_LRZ_FULL_8X8_TILES = 14,
PERF_LRZ_PARTIAL_8X8_TILES = 15,
PERF_LRZ_TILE_KILLED = 16,
PERF_LRZ_TOTAL_PIXEL = 17,
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
PERF_LRZ_FULLY_COVERED_TILES = 19,
PERF_LRZ_PARTIAL_COVERED_TILES = 20,
PERF_LRZ_FEEDBACK_ACCEPT = 21,
PERF_LRZ_FEEDBACK_DISCARD = 22,
PERF_LRZ_FEEDBACK_STALL = 23,
PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
PERF_LRZ_STALL_CYCLES_VC = 26,
PERF_LRZ_RAS_MASK_TRANS = 27,
};
enum a6xx_cmp_perfcounter_select {
PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
PERF_CMPDECMP_VBIF_READ_DATA = 7,
PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
PERF_CMPDECMP_2D_RD_DATA = 28,
PERF_CMPDECMP_2D_WR_DATA = 29,
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
PERF_CMPDECMP_2D_PIXELS = 39,
};
enum a6xx_2d_ifmt {
R2D_UNORM8 = 16,
R2D_INT32 = 7,
R2D_INT16 = 6,
R2D_INT8 = 5,
R2D_FLOAT32 = 4,
R2D_FLOAT16 = 3,
R2D_UNORM8_SRGB = 1,
R2D_RAW = 0,
};
enum a6xx_ztest_mode {
A6XX_EARLY_Z = 0,
A6XX_LATE_Z = 1,
A6XX_EARLY_LRZ_LATE_Z = 2,
};
enum a6xx_rotation {
ROTATE_0 = 0,
ROTATE_90 = 1,
ROTATE_180 = 2,
ROTATE_270 = 3,
ROTATE_HFLIP = 4,
ROTATE_VFLIP = 5,
};
enum a6xx_tess_spacing {
TESS_EQUAL = 0,
TESS_FRACTIONAL_ODD = 2,
TESS_FRACTIONAL_EVEN = 3,
};
enum a6xx_tess_output {
TESS_POINTS = 0,
TESS_LINES = 1,
TESS_CW_TRIS = 2,
TESS_CCW_TRIS = 3,
};
enum a6xx_threadsize {
THREAD64 = 0,
THREAD128 = 1,
};
enum a6xx_tex_filter {
A6XX_TEX_NEAREST = 0,
A6XX_TEX_LINEAR = 1,
A6XX_TEX_ANISO = 2,
A6XX_TEX_CUBIC = 3,
};
enum a6xx_tex_clamp {
A6XX_TEX_REPEAT = 0,
A6XX_TEX_CLAMP_TO_EDGE = 1,
A6XX_TEX_MIRROR_REPEAT = 2,
A6XX_TEX_CLAMP_TO_BORDER = 3,
A6XX_TEX_MIRROR_CLAMP = 4,
};
enum a6xx_tex_aniso {
A6XX_TEX_ANISO_1 = 0,
A6XX_TEX_ANISO_2 = 1,
A6XX_TEX_ANISO_4 = 2,
A6XX_TEX_ANISO_8 = 3,
A6XX_TEX_ANISO_16 = 4,
};
enum a6xx_reduction_mode {
A6XX_REDUCTION_MODE_AVERAGE = 0,
A6XX_REDUCTION_MODE_MIN = 1,
A6XX_REDUCTION_MODE_MAX = 2,
};
enum a6xx_tex_swiz {
A6XX_TEX_X = 0,
A6XX_TEX_Y = 1,
A6XX_TEX_Z = 2,
A6XX_TEX_W = 3,
A6XX_TEX_ZERO = 4,
A6XX_TEX_ONE = 5,
};
enum a6xx_tex_type {
A6XX_TEX_1D = 0,
A6XX_TEX_2D = 1,
A6XX_TEX_CUBE = 2,
A6XX_TEX_3D = 3,
};
#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
#define REG_A6XX_CP_RB_BASE 0x00000800
#define REG_A6XX_CP_RB_BASE_HI 0x00000801
#define REG_A6XX_CP_RB_CNTL 0x00000802
#define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
#define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
#define REG_A6XX_CP_RB_RPTR 0x00000806
#define REG_A6XX_CP_RB_WPTR 0x00000807
#define REG_A6XX_CP_SQE_CNTL 0x00000808
#define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
#define REG_A6XX_CP_HW_FAULT 0x00000821
#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
#define REG_A6XX_CP_MISC_CNTL 0x00000840
#define REG_A6XX_CP_APRIV_CNTL 0x00000844
#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
}
#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
{
return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
}
#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
#define REG_A6XX_CP_CHICKEN_DBG 0x00000841
#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
{
return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
}
#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
{
return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
#define A6XX_CP_PROTECT_REG_READ 0x80000000
#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
#define REG_A6XX_CP_IB1_BASE 0x00000928
#define REG_A6XX_CP_IB1_BASE_HI 0x00000929
#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
#define REG_A6XX_CP_IB2_BASE 0x0000092b
#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
#define REG_A6XX_CP_SDS_BASE 0x0000092e
#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
#define REG_A6XX_CP_MRB_BASE 0x00000931
#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
#define REG_A6XX_CP_VSD_BASE 0x00000934
#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
#define REG_A6XX_CP_MRB_DWORDS 0x00000946
#define REG_A6XX_CP_VSD_DWORDS 0x00000947
#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
{
return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
}
#define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
#define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
{
return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
}
#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
{
return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
}
#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
#define REG_A6XX_CP_AHB_CNTL 0x0000098d
#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
#define REG_A6XX_RBBM_STATUS 0x00000210
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
#define REG_A6XX_RBBM_STATUS3 0x00000213
#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
#define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
#define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
#define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
#define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
#define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
#define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
#define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
#define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
#define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
#define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
#define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
#define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
#define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
#define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
#define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
#define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
#define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
#define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
#define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
#define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
#define REG_A6XX_RBBM_INT_0_MASK 0x00000038
#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
}
#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
}
#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
}
#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
}
#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
{
return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
}
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
{
return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
}
static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
#define REG_A6XX_VBIF_VERSION 0x00003000
#define REG_A6XX_VBIF_CLKON 0x00003001
#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
{
return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
}
#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
{
return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
}
#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
#define REG_A6XX_GBIF_HALT 0x00003c45
#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
{
return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
}
#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
{
return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
}
static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
{
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
{
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
{
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
{
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
}
#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
#define REG_A6XX_GRAS_CL_CNTL 0x00008000
#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
#define A6XX_GRAS_CL_CNTL_UNK5 0x00000020
#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
#define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
}
#define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
}
#define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
}
#define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
#define REG_A6XX_GRAS_CNTL 0x00008005
#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
#define A6XX_GRAS_CNTL_SIZE 0x00000008
#define A6XX_GRAS_CNTL_UNK4 0x00000010
#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
}
#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
{
return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
}
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
{
return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
}
static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
{
return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
}
#define REG_A6XX_GRAS_SU_CNTL 0x00008090
#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
{
return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
}
#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
{
return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
}
#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
{
return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
}
#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
{
return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
}
#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
{
return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
}
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
{
return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
}
#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
#define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
{
return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
}
#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
{
return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
}
#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
{
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
}
#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
{
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
{
return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
}
#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
{
return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
}
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
{
return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
}
#define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
#define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a
#define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
#define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
#define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
{
return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
#define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000
#define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
{
return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000
#define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
{
return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
#define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000
#define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
{
return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
}
#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
{
return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
}
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
{
return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
}
#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
#define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
#define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
}
static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
}
static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
}
static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
}
#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
}
#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
}
#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
{
return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
}
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
{
return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
}
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
{
return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
}
#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
{
return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
}
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
{
return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
}
#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
#define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a
#define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff
#define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
{
return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
}
#define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000
#define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
{
return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
}
#define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000
#define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
{
return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
}
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078
#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
}
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
#define REG_A6XX_GRAS_2D_DST_TL 0x00008405
#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
}
#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
}
#define REG_A6XX_GRAS_2D_DST_BR 0x00008406
#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
}
#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
}
#define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
#define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
#define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
}
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
}
#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
}
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
{
return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
}
#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
#define REG_A6XX_RB_BIN_CONTROL 0x00008800
#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
{
return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
#define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000
#define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
{
return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
}
#define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000
#define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
{
return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
}
#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
#define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000
#define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
{
return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
}
#define REG_A6XX_RB_RENDER_CNTL 0x00008801
#define A6XX_RB_RENDER_CNTL_UNK3 0x00000008
#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
#define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060
#define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5
static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
}
#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00
#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
}
#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
}
#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
{
return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
}
#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
{
return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
}
#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
#define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
#define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}
#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
#define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010
#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
}
#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
#define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002
#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
#define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080
#define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100
#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
{
return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
}
#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
}
#define REG_A6XX_RB_DITHER_CNTL 0x0000880e
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
{
return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
}
#define REG_A6XX_RB_SRGB_CNTL 0x0000880f
#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
{
return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
}
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
{
return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
}
static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
{
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
{
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
{
return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum