tree 4e5f79fbdeb8fa7bf9a886a30f5168a25186db14
parent 5acd351427361131c583dfb11c7bf4c364c98a9b
author Thierry Reding <treding@nvidia.com> 1510567693 +0100
committer Thierry Reding <treding@nvidia.com> 1513170997 +0100

drm/tegra: Add Tegra186 display hub support

The display architecture has changed in several significant ways with
the new Tegra186 SoC. Shared between all display controllers is a set
of common resources referred to as the display hub. The hub generates
accesses to memory and feeds them into various composition pipelines,
each of which being a window that can be assigned to arbitrary heads.

Atomic state is subclassed in order to track the global bandwidth
requirements and select and adjust the hub clocks appropriately. The
plane code is shared to a large degree with earlier SoC generations,
except where the programming differs.

Signed-off-by: Thierry Reding <treding@nvidia.com>