tree feaa1b07055f397282704a4da0590a9b07b4415f
parent 8b09f0da0f873698a7e8b329dfb7b10fd42d5cdf
author Tejun Heo <htejun@gmail.com> 1200648990 +0900
committer Jeff Garzik <jeff@garzik.org> 1201083856 -0500

ata_piix: implement SIDPR SCR access

For ICH8, SCRs can be accessed using index and data register pair
located at BAR 5.  This patch implements support for it such that PHY
status, errors and hardreset are available for those controllers.

This is the only case where two devices on a PATA channel have access
to SCRs and creates a unique problem of mapping two SCRs to one link.
Note that this is different from PMP case in that they aren't quite
separate links - e.g. softreset resets both devices.

This problem is worked around by merging the SCR values.  To upper
layer, it looks like there is a single link with one set of SCRs but
with two devices.  This works well enough for PHY event, error
reporting and hardreset.

Supporting hardreset is important because in rare cases SATA devices
fail to recover without it after PHY errors.

Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>